AD9212BCPZ-65

AD9212 AD | Alldatasheet

Document overview

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Technical content

Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter AD9212 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

Eight ADCs integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs

325 MHz, full power analog bandwidth

2 V p-p input voltage range

1.8 V supply operation

Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9212 is an octal, 10-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. FUNCTIONAL BLOCK DIAGRAM 05968-001 SERIAL LVDS REF SELECT AD9212 AGND VIN–A VIN+A VIN–B VIN+B VIN–D VIN+D VIN–C VIN+C SENSE VREF AVDD DRVDD PDWN REFT REFB D–A D+A D–B D+B D–D D+D D–C D+C FCO– FCO+ DCO+ DCO– CLK+ DRGND CLK– SERIAL PORT INTERFACE CSB SCLK/ DTP SDIO/ ODM RBIAS SERIAL LVDS SERIAL LVDS SERIAL LVDS ADC ADC ADC ADC DATA RATE MULTIPLIER 0.5V SERIAL LVDSVIN–E VIN+E VIN–F VIN+F VIN–H VIN+H VIN–G VIN+G D–E D+E D–F D+F D–H D+H D–G D+G SERIAL LVDS SERIAL LVDS SERIAL LVDS ADC ADC ADC ADC Figure 1. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI®). The AD9212 is available in a Pb-free, 64-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. Small Footprint. Eight ADCs are contained in a small, space- saving package; low power of 100 mW/channel at 65 MSPS. 2. Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate operation (DDR). 3. User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. 4. Pin-Compatible Family. This includes the AD9222 (12-bit), and AD9252 (14-bit).

Rev. 0 | Page 2 of 56 TABLE OF CONTENTS

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 56 SPECIFICATIONS Table 1. AD9212-40 AD9212-65 Parameter1 Temperature Min Typ Max Min Typ Max Unit RESOLUTION 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±1.5 ±8 ±1.5 ±8 mV Offset Matching Full ±3 ±8 ±3 ±8 mV Gain Error Full ±0.4 ±1.2 ±3.2 ±4.3 % FS Gain Matching Full ±0.3 ±0.7 ±0.4 ±0.9 % FS Differential Nonlinearity (DNL) Full ±0.1 ±0.4 ±0.3 ±0.65 LSB Integral Nonlinearity (INL) Full ±0.15 ±0.5 ±0.4 ±1 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±17 ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ±21 ppm/°C REFERENCE Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 mV Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 3 mV Input Resistance Full 6 6 kΩ ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Full 2 2 V p-p Common-Mode Voltage Full AVDD/2 AVDD/2 V Differential Input Capacitance Full 7 7 pF Analog Bandwidth, Full Power Full 325 325 MHz POWER SUPPLY IAVDD Full 252 260 390 405 mA IDRVDD Full 49.5 53 54 58 mA Total Power Dissipation (Including Output Drivers) Full 542 560 800 833 mW Power-Down Dissipation Full 3 11 3 11 mW Standby Dissipation2 Full 83 95 mW CROSSTALK Full −90 −90 dB CROSSTALK (Overrange Condition)3 Full −90 −90 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range.

Rev. 0 | Page 4 of 56 AC SPECIFICATIONS Table 2. AD9212-40 AD9212-65 Parameter1 Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz Full 61.2 60.8 dB f IN = 19.7 MHz Full 60.2 61.2 60.8 dB f IN = 35 MHz Full 61.2 58.5 60.8 dB f IN = 70 MHz Full 61.0 60.7 dB SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 61.2 60.7 dB f IN = 19.7 MHz Full 60.0 61.0 60.6 dB f IN = 35 MHz Full 61.0 57.0 60.5 dB f IN = 70 MHz Full 60.8 60.4 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 9.87 9.81 Bits f IN = 19.7 MHz Full 9.71 9.87 9.81 Bits f IN = 35 MHz Full 9.87 9.43 9.81 Bits f IN = 70 MHz Full 9.84 9.79 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 87 81 dBc f IN = 19.7 MHz Full 72 85 79 dBc f IN = 35 MHz Full 79 62 77 dBc f IN = 35 MHz 25°C 69 77 dBc f IN = 70 MHz Full 74 72 dBc WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −87 −81 dBc f IN = 19.7 MHz Full −85 −72 −79 dBc f IN = 35 MHz Full −79 −77 −62 dBc f IN = 35 MHz 25°C −77 −69 dBc f IN = 70 MHz Full −74 −72 dBc WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz Full −90 −86 dBc f IN = 19.7 MHz Full −85 −72 −86 dBc f IN = 35 MHz Full −85 −85 −70 dBc f IN = 70 MHz Full −85 −85 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 77.0 dBc fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 77.0 77.0 dBc 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. 0 | Page 5 of 56 DIGITAL SPECIFICATIONS Table 3. AD9212-40 AD9212-65 Parameter1 Temperature Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 250 mV p-p Input Common-Mode Voltage Full 1.2 1.2 V Input Resistance (Differential) 25°C 20 20 kΩ Input Capacitance 25°C 1.5 1.5 pF LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 0.5 0.5 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 V Input Resistance 25°C 70 70 kΩ Input Capacitance 25°C 0.5 0.5 pF LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 0 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 2 2 pF LOGIC OUTPUT (SDIO/ODM) Logic 1 Voltage (IOH = 50 μA) Full 1.79 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 V DIGITAL OUTPUTS (D+, D−), (ANSI-644) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 247 454 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V Output Coding (Default) Offset binary Offset binary DIGITAL OUTPUTS (D+, D−), (Low Power, Reduced Signal Option) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 150 250 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 V Output Coding (Default) Offset binary Offset binary 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only.

Rev. 0 | Page 6 of 56 SWITCHING SPECIFICATIONS Table 4. AD9212-40 AD9212-65 Parameter1 Temp Min Typ Max Min Typ Max Unit CLOCK2 Maximum Clock Rate Full 40 65 MSPS Minimum Clock Rate Full 10 10 MSPS Clock Pulse Width High (tEH) Full 12.5 7.7 ns Clock Pulse Width Low (tEL) Full 12.5 7.7 ns OUTPUT PARAMETERS2, 3 Rise Time (tR) (20% to 80%) Full 300 300 ps Fall Time (tF) (20% to 80%) Full 300 300 ps DCO Propagation Delay (tCPD)4 Full tFCO + (tSAMPLE/20) tFCO + (tSAMPLE/20) ns DCO to Data Delay (tDATA)4 Full (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 ps DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 ps Data to Data Skew (tDATA-MAX − tDATA-MIN) Full ±50 ±200 ±50 ±200 ps Wake-Up Time (Standby) 25°C 600 600 ns Wake-Up Time (Power-Down) 25°C 375 375 μs Pipeline Latency Full 8 8 CLK cycles APERTURE Aperture Delay (tA) 25°C 750 750 ps Aperture Uncertainty (Jitter) 25°C <1 <1 ps rms Out-of-Range Recovery Time 25°C 1 1 CLK cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR4 material. 4 tSAMPLE/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Figure 4. 10-Bit Data Serial Stream, LSB First

Rev. 0 | Page 9 of 56 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter With Respect To Rating ELECTRICAL AVDD AGND −0.3 V to +2.0 V DRVDD DRGND −0.3 V to +2.0 V AGND DRGND −0.3 V to +0.3 V AVDD DRVDD −2.0 V to +2.0 V Digital Outputs (D+, D−, DCO+, DCO−, FCO+, FCO−) DRGND −0.3 V to +2.0 V CLK+, CLK− AGND −0.3 V to +3.9 V VIN+, VIN− AGND −0.3 V to +2.0 V SDIO/ODM AGND −0.3 V to +2.0 V PDWN, SCLK/DTP , CSB AGND −0.3 V to +3.9 V REFT, REFB, RBIAS AGND −0.3 V to +2.0 V VREF , SENSE AGND −0.3 V to +2.0 V ENVIRONMENTAL Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL IMPEDANCE Table 6. Air Flow Velocity (m/s) θJA1 θJB θJC 0.0 17.7°C/W 2.5 13.9°C/W 1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. ESD CAUTION

Figure 5. 64-Lead LFCSP Top View Table 7. Pin Function Descriptions

0 AGND Analog Ground (Exposed Paddle)

2 VIN+G ADC G Analog Input—True

3 VIN−G ADC G Analog Input—Complement

5 VIN−H ADC H Analog Input—Complement

6 VIN+H ADC H Analog Input—True

9 CLK− Input Clock—Complement

10 CLK+ Input Clock—True

15 D−H ADC H Digital Output—Complement

16 D+H ADC H True Digital Output—True

17 D−G ADC G Digital Output—Complement

18 D+G ADC G True Digital Output—True

19 D−F ADC F Digital Output—Complement

20 D+F ADC F True Digital Output—True

21 D−E ADC E Digital Output—Complement

22 D+E ADC E True Digital Output—True

23 DCO− Data Clock Digital Output—Complement

24 DCO+ Data Clock Digital Output—True

25 FCO− Frame Clock Digital Output—Complement

26 FCO+ Frame Clock Digital Output—True

27 D−D ADC D Digital Output—Complement

28 D+D ADC D True Digital Output—True

29 D−C ADC C Digital Output—Complement

30 D+C ADC C True Digital Output—True

31 D−B ADC B Digital Output—Complement

32 D+B ADC B True Digital Output—True

Rev. 0 | Page 11 of 56 Pin No. Mnemonic Description

33 D−A ADC A Digital Output—Complement

34 D+A ADC A True Digital Output—True

38 SCLK/DTP Serial Clock/Digital Test Pattern

39 SDIO/ODM Serial Data Input-Output/Output Driver Mode

40 CSB Chip Select Bar

41 PDWN Power Down

43 VIN+A ADC A Analog Input—True

44 VIN−A ADC A Analog Input—Complement

46 VIN−B ADC B Analog Input—Complement

47 VIN+B ADC B Analog Input—True

49 VIN+C ADC C Analog Input—True

50 VIN−C ADC C Analog Input—Complement

52 VIN−D ADC D Analog Input—Complement

53 VIN+D ADC D Analog Input—True

54 RBIAS External Resistor to Set the Internal ADC Core Bias Current

55 SENSE Reference Mode Selection

56 VREF Voltage Reference Input/Output

57 REFB Differential Reference (Negative)

58 REFT Differential Reference (Positive)

60 VIN+E ADC E Analog Input—True

61 VIN−E ADC E Analog Input—Complement

63 VIN−F ADC F Analog Input—Complement

64 VIN+F ADC F Analog Input—True

0.096 LSB rms

Figure 39. Input-Referred Noise Histogram, AD9212-65 Figure 40. Noise Power Ratio (NPR), AD9212- 65 Figure 41. Full Power Bandwidth vs. Frequency, AD9212-65

applications are particularly sensitive to jitter (see Figure 56). where aperture jitter may affect the dynamic range of the AD9212. be retimed by the original clock at the last step. performance as it relates to ADCs (visit www.analog.com).

16 BITS

14 BITS

12 BITS

10 BITS

8 BITS

Figure 56. Ideal SNR vs. Input Frequency and Jitter by the DRVDD supply and bias current of the LVDS output drivers. Figure 57. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, AD9212-40 Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, AD9212-65

both 1.8 V and 3.3 V tolerant. 375 μs to restore full operation. Memory Map section for more details on using these features. 350 mV swing at the receiver. for superior switching performance in noisy environments. trace length and position can be found in Figure 59. Figure 59. LVDS Output Timing Example in ANSI Mode (Default)

Table 9. Flex Output Test Modes

0000 Off (default) N/A N/A N/A

0001 Midscale short 1000 0000 (8-bit)

0100 Checker board 1010 1010 (8-bit)

0101 PN sequence long1 N/A N/A Yes

0110 PN sequence short1 N/A N/A Yes

0111 One/zero word toggle 1111 1111 (8-bit)

1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No

1001 One/zero bit toggle 1010 1010 (8-bit)

1011 One bit high 1000 0000 (8-bit)

1100 Mixed frequency 1010 0011 (8-bit)

(short), defines the pseudorandom sequence.

enables the user to refine system timing margins if required. resolution to a 12-bit serial stream, the data stream is lengthened. data capture to the receiver. the serial port interface or SPI. This pin is for applications that do not require SPI mode operation. with this pin to limit the current. Table 10. Output Driver Mode Pin Settings This pin is for applications that do not require SPI mode operation. both 1.8 V and 3.3 V tolerant. Table 11. Digital Test Pattern Pin Settings section to choose from the different options available. is both 1.8 V and 3.3 V tolerant.

Figure 63. SNR/SFDR vs. RBIAS, AD9212-40 Figure 64. IAVDD vs. RBIAS, AD9212-40 Figure 65. SNR/SFDR vs. RBIAS, AD9212-65 Figure 66. IAVDD vs. RBIAS, AD9212-65 Table 12. Reference Settings

2 V p-p FSR

resistor divider (see Figure 67), setting VREF to 1 V . pin for either an internal or an external reference configuration. depicts how the internal reference voltage is affected by loading.

manual Interfacing to High Speed ADCs via SPI. disables the read and write cycles (see Table 13). Table 13. Serial Port Pins synchronize serial interface reads and writes. CSB remains low until the communication cycle is complete. the device waits for a new instruction. line, streaming mode can be entered but not exited. appropriate point in the serial frame. as an input during write phases and as an output during readback. the ADC (see the AN-812 Application Note). when the CSB is strapped to AVDD during device power-up. strappable functions are supported on the SPI pins. that can be connected together and the resulting VOH level.

Rev. 0 | Page 32 of 56 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), device index and transfer register map (Address 0x05 and Address 0xFF), and program register map (Address 0x08 to Address 0x25). The left-hand column of the memory map indicates the register address number in hexadecimal. The default value of this address is shown in hexadecimal in the right-hand column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, Clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 at this address, the duty cycle stabilizer turns off. For more information on this and other functions, consult the user manual Interfacing to High Speed ADCs via SPI. RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES Coming out of reset, critical registers are preloaded with default values. These values are indicated in Table 15, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ”

Table 15. Memory Map Register

Rev. 0 | Page 34 of 56 Addr. (Hex) Parameter Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 14 output_mode X 0 = LVDS ANSI (default) 1 = LVDS low power, (IEEE 1596.3 similar) X X X Output invert 1 = on 0 = off (default) 00 = offset binary (default) 01 = twos complement 0x00 Configures the outputs and the format of the data. 15 output_adjust X X Output driver termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω X X X DCO and FCO 2× drive strength 1 = on 0 = off (default) 0x00 Determines LVDS or other output properties. Primarily func- tions to set the LVDS span and common-mode levels in place of an external resistor. 16 output_phase X X X X 0011 = output clock phase adjust (0000 through 1010) (Default: 180° relative to DATA edge) 0000 = 0° relative to DATA edge 0001 = 60° relative to DATA edge 0010 = 120° relative to DATA edge 0011 = 180° relative to DATA edge 0100 = 240° relative to DATA edge 0101 = 300° relative to DATA edge 0110 = 360° relative to DATA edge 0111 = 420° relative to DATA edge 1000 = 480° relative to DATA edge 1001 = 540° relative to DATA edge 1010 = 600° relative to DATA edge 1011 to 1111 = 660° relative to DATA edge 0x03 On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. 19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB. 1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB. 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB. 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB. 21 serial_control LSB first 1 = on 0 = off (default) X X X <10 MSPS, low encode rate mode 1 = on 0 = off (default) 000 = 10 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 Serial stream control. Default causes MSB first and the native bit stream (global). 22 serial_ch_stat X X X X X X Channel output reset 1 = on 0 = off (default) Channel power- down 1 = on 0 = off (default) 0x00 Used to power down individual sections of a converter (local).

optimum performance is easily achieved. path for heat dissipation to flow through the bottom of the PCB. These vias should be solder filled or plugged. several tie points between the two during the reflow process. Figure 73. Typical PCB Layout

are provided to isolate the DUT from the AD8334 drive circuitry. input is also necessary to achieve the specified noise performance. techniques that should be applied at the system level. to each of the various sections on the board. have a 1 A current capability as well. be connected directly to the evaluation board if possible. optional settings, visit www.analog.com/FIFO. Figure 74. Evaluation Board Connection

modes allowed on the AD9212 Rev. A evaluation board.

• POWER: Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.
• AIN: The evaluation board is set up for a transformer- coupled analog input with optimum 50 Ω impedance matching out to 150 MHz (see Figure 75). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2. –14 –13 –12 –11 –10 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) AMPLITUDE (dBFS) –3dB CUTOFF = 186MHz 05968-086

Figure 75. Evaluation Board Full Power Bandwidth

• VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Simply populate R312 and R313 and remove C307. Proper use of the VREF options is noted in the Voltage Reference section.
• RBIAS: RBIAS has a default setting of 10 kΩ (R301) to ground and is used to set the ADC core bias current. To further lower the core power (excluding the LVDS driver supply), simply change the resistor setting. However, performance of the ADC will degrade depending on the resistor chosen. See RBIAS section for more information.
• CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U401). Simply populate R406 and R407 with 0 Ω resistors and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 μF capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default working condition. Consult the AD9515 data sheet for more information about these and other options. If using an oscillator, two oscillator footprint options are also available (OSC401) to check the ADC performance. J401 gives the user flexibility in using the enable pin, which is common on most oscillators.
• PDWN: To enable the power-down feature, simply short J301 to the on position (AVDD) on the PDWN pin.
• SCLK/DTP: To enable a digital test pattern on the digital outputs of the ADC, use J304. If J304 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 will be enabled. See the SCLK/DTP Pin section for details.
• SDIO/ODM: To enable the low power, reduced signal option similar to the IEEE 1595.3 reduced range link LVDS output standard, use J303. If J303 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, which reduces the power of the DRVDD supply. See the SDIO/ODM Pin section for more details.
• CSB: To enable the SPI information on the SDIO and SCLK pins that is to be processed, simply tie J302 low in the always enable mode. To ignore the SDIO and SCLK information, tie J302 to AVDD.
• Non-SPI Mode: For users who wish to operate the DUT without using SPI, simply remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP , and SDIO/OMD pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level.
• D+, D−: If an alternative data capture method to the setup described in Figure 76 is used, optional receiver terminations, R318, R320 to R328, can be installed next to the high speed backplane connector.

Rev. 0 | Page 38 of 56 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this particular drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 16. For more details on the AD8334 dual VGA, including how it works and its optional pin settings, consult the AD8334 data sheet. To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed.

• Remove R102, R115, R128, R141, R202, R218, R234, R252, T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path.
• Populate R101, R114, R127, R140, R201, R217, R233, and R251 with 0 Ω resistors in the analog input path.
• Populate R106, R107, R119, R120, R132, R133, R144, R145, R206, R207, R223, R224, R239, R240, R257, and R258 with 10 kΩ resistors to provide an input common-mode level to the analog input.
• Populate R105, R113, R118, R124, R131, R137, R151, and R160, R205, R213, R221, R222, R239, R240, R255, and R256 with 0 Ω resistors in the analog input path. Currently, L505 to L520 and L605 to L620 are populated with 0 Ω resistors to allow signal connection. This area allows the user to design a filter if additional requirements are necessary.

Figure 76. Evaluation Board Schematic, DUT Analog Inputs

Figure 77. Evaluation Board Schematic, DUT Analog Inputs (Continued)

1 J304

1 J301

05968-074DNP: DO NOT POPULATE. Figure 78. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface

Figure 79. Evaluation Board Schematic, Clock Circuitry

resistors or design your own filter. Figure 80. Evaluation Board Schematic, Optional DUT Analog Input Drive

Figure 81. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued)

Figure 82. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry

Figure 83. Evaluation Board Layout, Primary Side

Figure 84. Evaluation Board Layout, Ground Plane

Figure 85. Evaluation Board Layout, Power Plane

Figure 86. Evaluation Board Layout, Secondary Side (Mirrored Image)

Table 16. Evaluation Board Bill of Materials (BOM)1

10 V, 10% tol

6.3 V, 10% tol

25 V, 10% tol

16 V, 10% tol

Rev. 0 | Page 51 of 56 Item Qty per Board REFDES Device Package Value Manufacturer Manufacturer Part Number 8 8 C503, C514, C520, C526, C603, C614, C620, C626 Capacitor 402 22 pF, ceramic, NPO, 5% tol, 50 V Murata GRM1555C1H220JZ01D 9 1 C704 Capacitor 1206 10 μF, tantalum,

16 V, 20% tol

10 9 C307, C714, C715, C716, C717, C719, C720, C721, C722 Capacitor 603 1 μF , ceramic, X5R, 11 16 C540, C541, C544, C545, C548, C549, C552, C553, C640, C641, C644, C645, C648, C649, C652, C653 Capacitor 805 0.1 μF , ceramic, X7R,

50 V, 10% tol

12 4 C705, C707, C709, C711 Capacitor 603 10 μF , ceramic, X5R,

6.3 V, 20% tol

13 1 CR401 Diode SOT-23 30 V, 20 mA, dual Schottky Agilent Technologies HSMS-2812-TR1G 14 2 CR701, CR702 LED 603 Green, 4 V, 5 m candela Panasonic LNJ314G8TRA 15 1 D702 Diode DO- 214AB

3 A, 30 V, SMC Micro

Commercial Co. SK33-TP 16 1 D701 Diode DO- 214AA

5 A, 50 V, SMC Micro

Commercial Co. S2A-TP 17 1 F701 Fuse 1210 6.0 V, 2.2 A trip-current resettable fuse Tyco/Raychem NANOSMDC110F-2 18 1 FER701 Choke coil 2020 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz Murata DLW5BSN191SQ2L 19 24 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212 Ferrite bead 603 10 Ω, test frequency

100 MHz, 25% tol,

20 4 JP501, JP502, JP601, JP602 Connector 2-pin 100 mil header jumper, 2-pin Samtec TSW-102-07-G-S 21 6 J301, J302, J303, J304, J401, J701 Connector 3-pin 100 mil header jumper, 3-pin Samtec TSW-103-07-G-S 23 1 J702 Connector 10-pin 100 mil header, male, 2 × 5 double row straight Samtec TSW-105-08-G-D 24 8 L701, L702, L703, L704, L705, L706, L707, L708 Ferrite bead 1210 10 μH, bead core 3.2 × 2.5 × 1.6 SMD, 2 A Murata BLM31PG500SN1L 25 8 L501, L502, L503, L504, L601, L602, L603, L604 Inductor 402 120 nH, test freq

100 MHz, 5% tol,

Rev. 0 | Page 52 of 56 Item Qty per Board REFDES Device Package Value Manufacturer Manufacturer Part Number 26 32 L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 Resistor 805 0 Ω, 1/8 W, 5% tol NIC Components Corp. NRC04Z0TRF 27 1 OSC401 Oscillator SMT Clock oscillator, 65.00 MHz, 3.3 V, ±5% duty cycle Valphey Fisher VFAC3H-L-65MHz 28 9 P101, P103, P105, P107, P201, P203, P205, P207, P401 Connector SMA Side-mount SMA for 0.063" board thickness Johnson Components 142-0701-851 29 1 P301 Connector HEADER 1469169-1, right angle 2-pair, 25 mm, header assembly Tyco 6469169-1 30 1 P701 Connector 0.1" , PCMT RAPC722, power supply connector Switchcraft RAPC722X 31 21 R301, R307, R401, R402, R410, R413, R504, R505, R511, R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715 Resistor 402 10 kΩ, 1/16 W, 5% tol NIC Components Corp. NRC04J103TRF 32 18 R103, R117, R129, R142, R203, R219, R235, R253, R317, R405, R415, R416, R417, R418, R706, R707, R708, R709 Resistor 402 0 Ω, 1/16 W, 5% tol NIC Components Corp. NRC04Z0TRF 33 8 R102, R115, R128, R141, R202, R218, R234, R252 Resistor 402 64.9 Ω, 1/16 W, 1% tol NIC Components Corp. NRC04F64R9TRF 34 8 R104, R116, R130, R143, R204, R220, R236, R254 Resistor 603 0 Ω, 1/10 W, 5% tol NIC Components Corp. NRC06Z0TRF 35 28 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713 Resistor 402 1 kΩ, 1/16 W, 1% tol NIC Components Corp. NRC04F1001TRF 36 16 R108, R110, R121, R122, R134, R136, R146, R147, R209, R210, R226, R227, R242, R245, R260, R261 Resistor 402 33 Ω, 1/16 W, 5% tol NIC Components Corp. NRC04J330TRF

Rev. 0 | Page 53 of 56 Item Qty per Board REFDES Device Package Value Manufacturer Manufacturer Part Number 37 8 R161, R162, R163, R164, R208, R225, R241, R259 Resistor 402 499 Ω, 1/16 W, 1% tol NIC Components Corp. NRC04F4990TRF 38 3 R303, R305, R306 Resistor 402 100 kΩ, 1/16 W, 1% tol NIC Components Corp. NRC04F1003TRF 39 1 R414 Resistor 402 4.12 kΩ, 1/16W, 1% tol NIC Components Corp. NRC04F4121TRF 40 1 R404 Resistor 402 49.9 Ω, 1/16 W, 0.5% tol Susumu RR0510R-49R9-D 41 1 R309 Resistor 402 4.99 kΩ, 1/16 W, 5% tol NIC Components Corp. NRC04F4991TRF 42 5 R310, R501, R535, R601, R634 Potentiometer 3-lead 10 kΩ, Cermet trimmer potentiometer, 18 turn top adjust, 10%, 1/2 W COPAL ELECTRONICS CT94EW103 43 1 R308 Resistor 402 470 kΩ, 1/16 W, 5% tol NIC Components Corp. NRC04J474TRF 44 4 R502, R536, R602, R635 Resistor 402 39 kΩ, 1/16 W, 5% tol NIC Components Corp. NRC04J393TRF 45 16 R513, R514, R518, R519, R525, R526, R530, R531, R613, R614, R618, R619, R625, R626, R630, R631 Resistor 402 187 Ω, 1/16 W, 1% tol NIC Components Corp. NRC04F1870TRF 46 8 R515, R520, R527, R532, R615, R620, R627, R632 Resistor 402 374 Ω, 1/16 W, 1% tol NIC Components Corp. NRC04F3740TRF 47 8 R503, R507, R508, R509, R603, R607, R608, R609 Resistor 402 274 Ω, 1/16 W, 1% tol NIC Components Corp. NRC04F2740TRF 48 11 R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445 Resistor 201 0 Ω, 1/20 W, 5% tol NIC Components Corp. NRC02Z0TRF 49 1 R701 Resistor 402 4.7 kΩ, 1/16 W, 1% tol NIC Components Corp. NRC04J472TRF 50 1 R702 Resistor 402 261 Ω, 1/16 W, 1% tol NIC Components Corp. NRC04F2610TRF 51 1 R716 Resistor 603 261 Ω, 1/16 W, 1% tol NIC Components Corp. NRC06F261OTRF 52 2 R420, R421 Resistor 402 240 Ω, 1/16 W, 5% tol NIC Components Corp. NRC04J241TRF 53 2 R422, R423 Resistor 402 100 Ω, 1/16 W, 1% tol NIC Components Corp. NRC04F1000TRF 54 1 S701 Switch SMD LIGHT TOUCH, 100GE, 5 mm Panasonic EVQ-PLDA15

Rev. 0 | Page 54 of 56 Item Qty per Board REFDES Device Package Value Manufacturer Manufacturer Part Number 55 9 T101, T102, T103, T104, T201, T202, T203, T204, T401 Transformer CD542 ADT1-1WT+, 1:1 impedance ratio transformer Mini-Circuits ADT1-1WT+ 56 2 U704, U707 IC SOT-223 ADP33339AKC-1.8-RL, 1.5 A, 1.8 V LDO regulator Analog Devices ADP3339AKCZ-1.8-RL 57 2 U501, U601 IC CP-64-3 AD8334ACPZ-REEL, ultralow noise precision dual VGA Analog Devices AD8334ACPZ-REEL 58 1 U706 IC SOT-223 ADP33339AKC-5-RL7 Analog Devices ADP3339AKCZ-5-RL7 59 1 U705 IC SOT-223 ADP33339AKC-3.3-RL Analog Devices ADP3339AKCZ-3.3-RL 60 1 U301 IC CP-64-3 AD9212BCPZ-50, octal, 10-bit, 65 MSPS serial LVDS 1.8 V ADC Analog Devices AD9212BCPZ-65 61 1 U302 IC SOT-23 ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference Analog Devices ADR510ARTZ 62 1 U401 IC LFCSP CP-32-2 AD9515BCPZ, 1.6 GHz clock distribution IC Analog Devices AD9515BCPZ 63 1 U702 IC SC70, MAA06A NC7WZ07P6X_NL, UHS dual buffer Fairchild NC7WZ07P6X_NL 64 1 U703 IC SC70, MAA06A NC7WZ16P6X_NL, UHS dual buffer Fairchild NC7WZ16P6X_NL 65 1 U701 IC 8-SOIC Flash prog mem 1kx14, RAM size 64 × 8,

20 MHz speed, PIC12F

1 This BOM is RoHS compliant.

0.25 MIN

0.05 MAX

0.02 NOM

0.60 MAX

Figure 87. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 56 of 56 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05968-0-10/06(0)