AD9211 AD | Alldatasheet
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Technical content
10-Bit, 170/200/250 MSPS
1.8 V A/D Converter
Preliminary Technical Data AD9211 Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 60 dBFs @ fIN up to 70 MHz @ 250 MSPS ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (–0.5 dBFS) SFDR = 80 dBc@ fIN up to 70 MHz @ 250 MSPS (–0.5 dBFS) Excellent Linearity DNL = ±0.3 LSB (Typical) INL = ±0.5 LSB (Typical) LVDS at 250 MSPS (ANSI-644 levels)
900 MHz Full Power Analog Bandwidth
On-Chip Reference and Track-and-Hold Power Dissipation = 380 mW Typical @ 250 MSPS
1.25 V Input Voltage Range
1.8 V Analog Supply Operation
Data Clock Output Provided Clock Duty Cycle Stabilizer
APPLICATIONS
Wireless and Wired Broadband Communications Cable Reverse Path Communications Test Equipment Radar and Satellite Subsystems Power Amplifier Linearization PRODUCT DESCRIPTION The AD9211 is a 10-Bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format or gray code. A data clock output is available for proper output data timing.
10 Output
(D4-D0 DDR mode) DCO- DCO+ AVDD (1.8V) DrVDD (1.8V) OTR+ Ref ADC 10-bit Core T/H Clock Mgmt CLK+ CLK- SCLK CSB DGND (Pin 0) AGND VIN+ VIN- SDIO Serial Port OTR- RESET AD9211 Figure 1. Functional Block Diagram over the industrial temperature range (–40°C to +85°C).
- High Performance—Maintains 60 dB SNR @ 250 MSPS
- Low Power—Consumes only 380mW @ 250 MSPS.
- Ease of Use—LVDS output data and output clock signal
- Serial Port Control - Standard serial port interface
down, gain adjust and output test pattern generation.
- Pin compatible family – 12-bit pin compatible family
AD9211 Preliminary Technical Data Rev. PrA | Page 2 of 21 TABLE OF CONTENTS
Table 1. DC SPECIFICATIONS (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, Internal Reference,
1 All ac specifications tested by driving CLK+ and CLK– differentially.
Preliminary Technical Data AD9211 Rev. PrA | Page 5 of 21 DIGITAL SPECIFICATIONS Table 3 (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = –40°C, TMAX = +85°C, DCS Enabled unless otherwise noted.) AD9211-170/-200 AD9211-250 Parameter Temp Min Typ Max Min Typ Max Unit C L O C K I N P U T S Differential Input Voltage1 Full tbd tbd V Common-Mode Voltage2 Full tbd tbd V Input Resistance Full tbd tbd kΩ Input Capacitance 25°C 4 4 pF L O G I C I N P U T S Logic 1 Voltage Full .8 x VDD 2.0 V Logic 0 Voltage Full .2 x AVDD 0.8 V Logic 1 Input Current Full 10 10 μA Logic 0 Input Current Full 10 10 μA Input Capacitance 25°C 4 4 pF LOGIC OUTPUTS3 VOD Differential Output Voltage Full 247 454 247 454 mV VOS Output Offset Voltage Full 1.125 1.375 1.125 1.375 V Output Coding Twos Complement, or Binary Twos Complement, or Binary 1 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+)– (CLK–)| > 200 mV. 2 Clock inputs’ common mode can be externally set, such that xx.xV < (Clk+ or Clk- ) < zzz V.
3 LVDS RTermination = 100 Ω
Table 4. (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = –40°C, TMAX = +85°C, DCS Enabled unless otherwise noted.) 1 All ac specifications tested by driving CLK+ and CLK– differentially. Figure 2. Timing Diagram (L=5 Cycles)
Preliminary Technical Data AD9211 Rev. PrA | Page 7 of 21 ABSOLUTE MAXIMUM RATINGS1 Parameter Rating AVDD 2.0 V DRVDD 2.0V Analog Inputs –0.5 V to AVDD + 0.5 V Digital Inputs –0.5 V to DRVDD + 0.5 V REFIN Inputs –0.5 V to AVDD + 0.5 V Digital Output Current 20 mA Operating Temperature –40ºC to +125°C Storage Temperature –65ºC to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C θJA 2 TBD°C/W 1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
2 Typical θJA = TBD C/W (heat slug soldered) for multilayer board in still air
with solid ground plane. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
56 Lead for
29 PDN
Figure 3. Pinout Table 5. PIN FUNCTION DESCRIPTIONS 7, 24,47 DRVDD 1.8 V Digital Output Supply. 8, 23,48 DRGND 1 Digital Output Ground. 36 VIN– Analog Input—Complement.
40 CML Analog input common mode output pin
45 CLK– Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% X kohm resistor terminated to ground).
28 RESET Chip Reset ( Active high)
25 SDIO Serial port input/output pin
26 SCLK Serial port clock
49 DCO– Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 55 D0– D0 Complement Output Bit. 1 AGND and DRGND should be tied to a common quiet ground plane.
Preliminary Technical Data AD9211 Rev. PrA | Page 9 of 21 Pin Number Mnemonic Description 1 D1– D1 Complement Output Bit. 2 D1+ D1 True Output Bit. 3 D2– D2 Complement Output Bit. 4 D2+ D2 True Output Bit. 5 D3– D3 Complement Output Bit. 5 D3+ D3 True Output Bit. 9 D4– D4 Complement Output Bit. 10 D4+ D4 True Output Bit. 11 D5– D5 Complement Output Bit. 12 D5+ D5 True Output Bit. 13 D6– D6 Complement Output Bit. 14 D6+ D6 True Output Bit. 15 D7– D7 Complement Output Bit. 16 D7+ D7 True Output Bit. 17 D8– D8 Complement Output Bit. 18 D8+ D8 True Output Bit. 19 D9– D9 Complement Output Bit. 20 D9+ D9 True Output Bit. 21 OTR– Overrange Complement Output Bit. 22 OTR+ Overrange True Output Bit.
AD9211 Preliminary Technical Data Rev. PrA | Page 10 of 21 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the Clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a low level (–40 dBFS) signal when the adjacent interfering channel is driven by a fullscale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the input’s phase 180° and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation 02.6 76.1 dBSNRENOB MEASURED −= Clock Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time the Clock pulse should be left in low state. At a given clock rate, these specifications define an acceptable Clock duty cycle. Full-Scale Input Power Expressed in dBm. Computed using the following equation: 001.0 log10 INPUT RMSFULLSCALE FULLSCALE Z VPower Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The Clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The Clock rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK– and the time when all output data bits are within valid logic levels. Noise (for Any Range within the ADC) Calculated as follows: ⎛ −−××= 1010001.0 dBFSdBcdBM NOISE SignalSNRFSZV where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value of the particular input level, and Signal is the signal level within the ADC
Preliminary Technical Data AD9211 Rev. PrA | Page 11 of 21 reported in dB below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Preliminary Technical Data AD9211 Rev. PrA | Page 13 of 21 TYPICAL PERFORMANCE CHARACTERISTICS TBD
Figure 10. Single-Ended Input Configuration using SPI enabled CML function (CLK+ and CLK-) should be clocked with a differential signal. and require no additional bias (See Figure X). Figure X shows one preferred method for clocking the AD9211.
Figure 14. AD9211-250, Supply Current vs. fSAMPLE for fIN = 10.3 MHz standby, the output drivers are placed in a high impedance state. resume normal operation after allowing for the pipeline latency. 350 mV swing at the receiver. close together and at equal lengths. the output coding format can be found in Table 7. Table 7. Digital Output Coding
1.252 V p-p (V)
Figure 15. OTR will remain high until the analog input returns to within the input range and another conversion is completed. over-range high or under-range low conditions can be detected. Figure 15. OTR Relation to Input Voltage and Output Data for delay (tPD) after the rising edge of the clock signal.
AD9211 Preliminary Technical Data Rev. PrA | Page 18 of 21 The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9211. These transients can degrade the converter’s dynamic performance. The AD9211 also provides data clock output (DCO) intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO. The lowest typical conversion rate of the AD9211 is 40 MSPS. At clock rates below 1 MSPS, the AD9211 will assume standby mode. RBIAS The AD9211 requires the user to place a 10KΩ resistor between the RBIAS pin and ground. This resister should have a 1% tolerance, and is used to set the master current reference of the ADC core. AD9211 CONFIGURATION USING THE SPI The AD9211 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space inside the ADC. This gives the user added flexibility to customize device operation depending on the application. Addresses are accessed (programmed or read back) serially in one-byte words. Each byte may be further divided down into fields which are documented in the Memory Map Section below. There are three pins that define the serial port interface or SPI to this particular ADC. They are the SPI SCLK / DFS, SPI SDIO / DCS, and CSB pins. The SCLK/DFS (serial clock) is used to synchronize the read and write data presented the ADC.. The SDIO / DCS (serial data input/output) is a dual purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB or chip select bar is an active low control that enables or disables the read and write cycles. See Table X. Table X. Serial Port Pins Pin Function SCLK SCLK (Serial Clock) is the serial shift clock in. SCLK is used to synchronize serial interface reads and writes. SDIO SDIO (Serial Data Input/Output) is a dual purpose pin. The typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame. CSB RESET CSB (Chip Select Bar) is active low controls that gates the read and write cycles. Master device reset. When asserted, device assumes default settings. The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing. An example of the serial timing and its definitions can be found in Figure X and Table X. Table X. SPI Timing Diagram specifications Spec Name Meaning tDS Setup time between data and rising edge of SCLK tDH Hold time between data and rising edge of SCLK tCLK Period of the clock tS Setup time between CSB and SCLK tH Hold time between CSB and SCLK tHI Minimum period that SCLK should be in a logic high state tLO Minimum period that SCLK should be in a logic low state During an instruction phase a 16bit instruction is transmitted. Data then follows the instruction phase and is determined by the W0 and W1 bits which is 1 or more bytes of data. All data is composed of 8bit words. The first bit of each individual byte of serial data indicates whether this is a read or write command. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. Data may be sent in MSB or in LSB first mode. MSB first is default on power up and may be changed by changing the configuration register. For more information about this feature and others see SPI Doc at www.analog.com.
resistor (suggested value 10 kΩ). AVDD, which will disable the serial port interface. Table 6. Mode Selection Each row in the memory map table has eight address locations. flexible ADC functions register map is product specific. to the Nominal DCO edge and 180deg relative to the data edge. part of an address location is open (for example, Address 0x14). 0x13), then this address location does not need to be written. registers are given in the Table X.
AD9211 Preliminary Technical Data Rev. PrA | Page 20 of 21 Table X. AD9211 Device Configuration Register Memory Map
0.50 BSC
0.20 REF
0.65 TYP
0.60 MAX
0.05 MAX
0.02 NOM
0.30 MIN
Figure 16. Mechanical Drawing (Subject to change)
1 Z=Pb-free part
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