AD9211

AD9230 10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet (Rev. 0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 28

Technical content

10-Bit, 200 MSPS/250 MSPS/300 MSPS,

1.8 V Analog-to-Digital Converter

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.

FEATURES

SNR = 60.1 dBFS @ fIN up to 70 MHz @ 300 MSPS ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS) SFDR = −80 dBc @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS) Excellent linearity DNL = ±0.1 LSB typical INL = ±0.2 LSB typical LVDS at 300 MSPS (ANSI-644 levels)

700 MHz full power analog bandwidth

On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 437 mW @ 300 MSPS—LVDS SDR mode 410 mW @ 300 MSPS—LVDS DDR mode Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal

1.8 V analog and digital supply operation

Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock

APPLICATIONS

Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM AGND AVDD (1.8V) VIN+ VIN– TRACK-AND-HOLD REFERENCE ADC 10-BIT CORE OUTPUT STAGING LVDS CLK+ CLK– CLOCK MANAGEMENT SERIAL PORT RESET SCLK SDIO CSB DCO– DCO+ OR– OR+ D9 TO D0 DGND DRVDD 10 10 AD9211 PWDNRBIAS 06041-001 Figure 1. GENERAL DESCRIPTION The AD9211 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 300 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9211 is available in a 56-lead LFCSP , specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. High Performance—Maintains 60.1 dBFS SNR @ 300 MSPS with a 70 MHz input. 2. Low Power—Consumes only 410 mW @ 300 MSPS. 3. Ease of Use—LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. 4. Serial Port Control—Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power- down, gain adjust, and output test pattern generation. 5. Pin-Compatible Family—12-bit pin-compatible family offered as AD9230.

Rev. 0 | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 3 of 28 SPECIFICATIONS DC SPECIFICATIONS Table 1. AD9211-200 AD9211-250 AD9211-300 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 10 10 10 Bits A C C U R A C Y No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error 25°C 4.3 4.6 4.4 mV Full −12 +12 −13 +13 −13 +13 mV Gain Error 25°C 1.0 1.3 1.1 % FS Differential Nonlinearity (DNL) 25°C ±0.1 ±0.1 ±0.1 LSB Integral Nonlinearity (INL) 25°C ±0.2 ±0.2 ±0.2 LSB T E M P E R A T U R E D R I F T Offset Error Full ±8 ±7 ±6 μV/°C Gain Error Full 0.018 0.018 0.018 %/°C ANALOG INPUTS (VIN+, VIN−) Input Common-Mode Voltage Full 1.4 1.4 1.4 V Input Resistance (Differential) Full 4.3 4.3 4.3 kΩ Input Capacitance 25°C 2 2 2 pF POWER SUPPLY S u p p l y C u r r e n t s IAVDD3 Full 134 144 158 169 189 203 mA IDRVDD3/SDR Mode4 Full 51 54 53 55 54 57 mA IDRVDD3/DDR Mode5 Full 35 38 39 mA Power Dissipation3 F u l l m W SDR Mode4 Full 333 356 380 403 437 468 mW DDR Mode5 Full 304 353 410 mW 1 See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9211. 5 Double data rate mode; user-programmable feature. See the Memory Map section.

Rev. 0 | Page 4 of 28 AC SPECIFICATIONS1 Table 2. AD9211-200 AD9211-250 AD9211-300 Parameter2 Temp Min Typ Max Min Typ Max Min Typ Max Unit SNR Full 58.9 58.7 57.5 dB Full 58.8 58.7 57.0 dB Full 58.4 58.4 57.0 dB S I N A D Full 58.9 58.7 57.3 dB Full 58.7 58.6 57.0 dB Full 58.1 58.1 56.7 dB EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz 25°C 9.8 9.7 9.7 Bits fIN = 70 MHz 25°C 9.7 9.7 9.7 Bits fIN = 170 MHz 25°C 9.6 9.7 9.6 Bits WORST HARMONIC (Second or Third) fIN = 10 MHz 25°C −85 −78 −86 −79 −80 −75 dBc Full −78 −77 −70 dBc fIN = 70 MHz 25°C −77 −75 −80 −76 −80 −74 dBc Full −75 −74 −67 dBc fIN = 170 MHz 25°C −77 −72 −79 −70 −80 −73 dBc Full −72 −70 −67 dBc WORST OTHER (SFDR Excluding Second and Third) fIN = 10 MHz 25°C −86 −82 −82 −80 −82 −75 dBc Full −82 −77 −70 dBc fIN = 70 MHz 25°C −83 −81 −82 −79 −80 −75 dBc Full −81 −77 −71 dBc fIN = 170 MHz 25°C −81 −74 −79 −77 −80 −75 dBc Full −74 −75 −70 dBc T W O - T O N E I M D 140.2 MHz/141.3 MHz @ −7 dBFS 25°C −78 −87 −81 dBc 170.2 MHz/171.3 MHz @ −7 dBFS 25°C −86 −82 −82 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. 0 | Page 5 of 28 DIGITAL SPECIFICATIONS Table 3. AD9211-200 AD9211-250 AD9211-300 Parameter1 T emp Min Typ Max Min Typ Max Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 1.2 1.2 V Differential Input Voltage Full 0.2 6 0.2 6 0.2 6 V p-p Input Voltage Range Full AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 AVDD − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD 1.1 AVDD 1.1 AVDD V Low Level Input Voltage (VIL) Full 0 0.8 0 0.8 0 0.8 V High Level Input Current (IIH) Full −10 +10 −10 +10 −10 +10 μA Low Level Input Current (IIL) Full −10 +10 −10 +10 −10 +10 μA Input Resistance (Differential) Full 16 20 24 16 20 24 16 20 24 kΩ Input Capacitance Full 4 4 4 pF LOGIC INPUTS Logic 1 Voltage Full 0.8 × VDD 0.8 × VDD 0.8 × VDD V Logic 0 Voltage Full 0.2 × AVDD 0.2 × AVDD 0.2 × AVDD V Logic 1 Input Current (SDIO) Full 0 0 0 μA Logic 0 Input Current (SDIO) Full −60 −60 −60 μA Logic 1 Input Current (SCLK, PWDN, CSB, RESET) Full 55 55 50 μA Logic 0 Input Current (SCLK, PWDN, CSB, RESET) Full 0 0 0 μA Input Capacitance 25°C 4 4 4 pF LOGIC OUTPUTS2 VOD Differential Output Voltage Full 247 454 247 454 247 454 mV Output Coding Twos complement, Gray code, or offset binary (default) 1 See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 LVDS RTERMINATION = 100 Ω.

Rev. 0 | Page 6 of 28 SWITCHING SPECIFICATIONS Table 4. AD9211-200 AD9211-250 AD921-300 Parameter (Conditions) Temp Min Typ Max Min Typ Max Min Typ Max Unit Maximum Conversion Rate Full 200 250 300 MSPS Minimum Conversion Rate Full 40 40 40 MSPS Output (LVDS − SDR Mode)1 Data Propagation Delay (tPD) Full 3.0 3.0 3.0 ns Rise Time (tR) (20% to 80%) 25°C 0.2 0.2 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 0.2 0.2 ns DCO Propagation Delay (tCPD) Full 3.9 3.9 3.9 ns Latency Full 7 7 7 Cycles Output (LVDS − DDR Mode)2 Data Propagation Delay (tPD) Full 3.8 3.8 3.8 ns Rise Time (tR) (20% to 80%) 25°C 0.2 0.2 0.2 ns Fall Time (tF) (20% to 80%) 25°C 0.2 0.2 0.2 ns DCO Propagation Delay (tCPD) Full 3.9 3.9 3.9 ns Latency Full 7 7 7 Cycles Aperture Uncertainty (Jitter, tJ) 25°C 0.2 0.2 ps rms 1 See Figure 2. 2 See Figure 3.

Figure 2. Single Data Rate Mode

5 MSBs

5 LSBs

Figure 3. Double Data Rate Mode

Rev. 0 | Page 8 of 28 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL AVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +2.0 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −2.0 V to +2.0 V D0+/D0− through D9+/D9− to DRGND −0.3 V to DRVDD + 0.3 V DCO to DRGND −0.3 V to DRVDD + 0.3 V OR to DGND −0.3 V to DRVDD + 0.3 V CLK+ to AGND −0.3 V to +3.9 V CLK− to AGND −0.3 V to +3.9 V VIN+ to AGND −0.3 V to AVDD + 0.2 V VIN− to AGND −0.3 V to AVDD + 0.2 V SDIO/DCS to DGND −0.3 V to DRVDD + 0.3 V PWDN to AGND −0.3 V to +3.9 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to AGND −0.3 V to +3.9 V ENVIRONMENTAL Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6. Package Type θJA θJC Unit 56-Lead LFCSP (CP-56-2) 30.4 2.9 °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the θJA. ESD CAUTION

35 VIN+

36 VIN–

37 AVDD

38 AVDD

39 AVDD

40 CML

41 AVDD

42 AVDD

34 AVDD

33 AVDD

32 AVDD

31 RBIAS

30 AVDD

29 PWDN

Figure 4. AD9211 Single Data Rate Mode Pin Configuration Table 7. Single Data Rate Mode Pin Function Descriptions 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 36 VIN− Analog Input—Complement. optimized internal bias voltage for VIN+/VIN−. 45 CLK− Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 51 to 54 DNC Do Not Connect. 55 D0− D0 Complement Output Bit (LSB). 56 D0+ D0 True Output Bit (LSB). 1 D1− D1 Complement Output Bit. 3 D2− D2 Complement Output Bit. 5 D3− D3 Complement Output Bit. 9 D4− D4 Complement Output Bit.

Rev. 0 | Page 10 of 28 Pin No. Mnemonic Description 11 D5− D5 Complement Output Bit. 12 D5+ D5 True Output Bit. 13 D6− D6 Complement Output Bit. 14 D6+ D6 True Output Bit. 15 D7− D7 Complement Output Bit. 16 D7+ D7 True Output Bit. 17 D8− D8 Complement Output Bit. 18 D8+ D8 True Output Bit. 19 D9− D9 Complement Output Bit (MSB). 20 D9+ D9 True Output Bit (MSB). 21 OR− Overrange Complement Output Bit. 22 OR+ Overrange True Output Bit. 1 AGND and DRGND should be tied to a common quiet ground plane.

Figure 5. AD9211 Double Data Rate Pin Configuration Table 8. Double Data Rate Mode Pin Function Descriptions 7, 24, 47 DRVDD 1.8 V Digital Output Supply. 8, 23, 48 DRGND1 Digital Output Ground. 36 VIN− Analog Input—Complement. optimized internal bias voltage for VIN+/VIN−. 45 CLK− Clock Input—Complement. 31 RBIAS Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. 28 RESET CMOS-Compatible Chip Reset (Active Low). 26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). 27 CSB Serial Port Chip Select (Active Low). 49 DCO− Data Clock Output—Complement. 50 DCO+ Data Clock Output—True. 53 D0/D5− D1/D7 Complement Output Bit (LSB). 54 D0/D5+ D1/D7 True Output Bit (LSB). 55 D1/D6− D2/D8 Complement Output Bit. 56 D1/D6+ D2/D8 True Output Bit. 1 D2/D7− D3/D9 Complement Output Bit. 2 D2/D7+ D3/D9 True Output Bit. 3 D3/D8− D4/D10 Complement Output Bit. 4 D3/D8+ D4/D10 True Output Bit. 5 D4/D9− D5/D11 Complement Output Bit (MSB). 6 D4/D9+ D5/D11 True Output Bit (MSB).

Rev. 0 | Page 12 of 28 Pin No. Mnemonic Description 9 OR− D6 Complement Output Bit. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.) 10 OR+ D6 True Output Bit. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.) 11 to 20, 51, 52 DNC Do Not Connect. 21 DNC/(OR−) Do Not Connect. (This pin can be reconfigured as the Overrange Complement Output Bit through the serial port register.) 22 DNC/(OR+) Do Not Connect. (This pin can be reconfigured as the Overrange True Output Bit through the serial port register.) 1 AGND and DRGND should be tied to a common quiet ground plane.

Figure 6. AD9211-200 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz Figure 7. AD9211-200 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz Figure 8. AD9211-200 64k Point Single-Tone FFT; 200 MSPS, 170.3 MHz Figure 9. AD9211-200 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with

1.25 V p-p Full Scale; 200 MSPS

Figure 10. AD9211-200 SNR/SFDR vs. Input Amplitude; 170.3 MHz Figure 11. AD9211-200 INL; 200 MSPS

Figure 12. AD9211-200 DNL; 200 MSPS Figure 13. AD9211-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz Figure 14. AD9211-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz Figure 15. AD9211-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz Figure 16. AD9211-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with

1.25 V p-p Full Scale; 250 MSPS

Figure 17. AD9211-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz

Figure 18. AD9211-250 INL; 250 MSPS Figure 19. AD9211-250 DNL; 250 MSPS Figure 20. AD9211-300 64k Point Single-Tone FFT; 300 MSPS, 10.3 MHz Figure 21. AD9211-300 64k Point Single-Tone FFT; 300 MSPS, 70.3 MHz Figure 22. AD9211-300 64k Point Single-Tone FFT; 300 MSPS, 170.3 MHz Figure 23. AD9211-300 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with

1.25 V p-p Full Scale; 300 MSPS

where aperture jitter may affect the dynamic range of the AD9211. be retimed by the original clock at the last step. performance as it relates to ADCs (visit www.analog.com).

16 BITS

14 BITS

12 BITS

10 BITS

8 BITS

Figure 47. Ideal SNR vs. Input Frequency and Jitter bias current of the LVDS output drivers. low returns the AD9211 to its normal operational mode. operation after allowing for the pipeline latency. for superior switching performance in noisy environments. Figure 48. Figure 49 shows an example of when the of the design when the trace lengths exceed 24 inches. Figure 48. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less

Table 11. Serial Timing Definitions Table 12. Output Data Format

Each row in the memory map table has eight address locations. (Address 0x08 to Address 0x2A). Address 0x09, clock, has a hexadecimal default value of 0x01. application note, Interfacing to High Speed ADCs via SPI. have a 0 written into their registers during power-up. Table 13. Memory Map Register

Rev. 0 | Page 26 of 28 Addr. (Hex) Parameter Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments ADC Functions 08 modes 0 0 PWDN: 0 = full (default) 1 = standby 0 0 Internal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = normal (power-up) Note: External PWDN pin overrides this setting. 0x00 Determines various generic modes of chip operation. 09 clock 0 0 0 0 0 0 0 Duty cycle stabilizer: 0 = disabled 1 = enabled (default) 0x01 OD test_io Reset PN23 gen: 1 = on 0 = off (default) Reset PN9 gen: 1 = on 0 = off (default) Output test mode: 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused (Format determined by output_mode) 0x00 When set, the test data is placed on the output pins in place of normal data. OF ain_config 0 0 0 0 0 Analog input disable: 1 = on 0 = off (default) CML enable: 1 = on 0 = off (default) 0 0x00 14 output_mode 0 0 Output enable: 0 = enable (default) 1 = disable DDR: 1 = enabled 0 = disabled (default) Output invert: 1 = on 0 = off (default) Data format select: 00 = offset binary (default) 01 = twos complement 10 = Gray code 0x00 0 15 output_adjust 0 0 LVDS course adjust: 0 = 3.5 mA (default) 1 = 2.0 mA LVDS fine adjust: 001 = 3.50 mA 010 = 3.25 mA 011 = 3.00 mA 100 = 2.75 mA 101 = 2.50 mA 110 = 2.25 mA 111 = 2.00 mA 0x00 0 16 output_phase Output clock polarity 1 = inverted 0 = normal (default) 0 0 0 0x03

Rev. 0 | Page 27 of 28 Addr. (Hex) Parameter Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 17 flex_output_delay Output delay enable: 0 = enable 1 = disable Output clock delay: 00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns 18 flex_vref Input voltage range setting: 10000 = 0.98 V 10001 = 1.00 V 10010 = 1.02 V 10011 = 1.04 V 11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V 01110 = 1.48 V 01111 = 1.50 V 2A ovr_config OR position (DDR mode only): 0 = Pin 9, Pin 10 1 = Pin 21, Pin 22 OR enable: 1 = on (default) 0 = off 00000001

0.50 BSC

0.20 REF

0.65 TYP

0.60 MAX

0.05 MAX

0.02 NOM

0.30 MIN

Figure 52. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the property of their respective owners.