AD9208-3000EBZ

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14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9208 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

JESD204B (Subclass 1) coded serial digital outputs Support for lane rates up to 16 Gbps per lane

1.65 W total power per channel at 3 GSPS (default settings)

Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation

9 GHz analog input full power bandwidth (−3 dB)

Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO 4 cascaded half-band filters Phase coherent NCO switching Up to 4 channels available Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

APPLICATIONS

Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, L TE, L TE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers FUNCTIONAL BLOCK DIAGRAM ADC CORE FAST DETECT SIGNAL MONITOR DIGITAL DOWN- CONVERTER CROSSBAR MUX CROSSBAR MUX PROGRAMMABLE FIR FILTER DIGITAL DOWN- CONVERTER BUFFER VIN+A VIN–A VIN+B CLK+ CLK– VREF PDWN/STBY SYSREF± AGND DRGND DGND AVDD1 (0.975V) DVDD (0.975V) DRVDD1 (0.975V) DRVDD2 (1.9V) SPIVDD (1.9V) AVDD2 (1.9V) AVDD3 (2.5V) AVDD1_SR (0.975V) SPI AND CONTROL REGISTERS SDIO SCLK CSB VIN–B BUFFER ADC CORE ÷4 AD9208 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SERDOUT4± SERDOUT5± SERDOUT6± SERDOUT7± JESD204B LINK AND Tx OUTPUTS JESD204B SUBCLASS 1 CONTROL CLOCK DISTRIBUTION SYNCINB± GPIO_A1 FD_A/GPIO_A0 FD_B/GPIO_B0 GPIO_B1 GPIO MUX 15547-001 Figure 1.

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Rev. 0 | Page 2 of 136 TABLE OF CONTENTS

Rev. 0 | Page 3 of 136

REVISION HISTORY

4/2017—Revision 0: Initial Version

Rev. 0 | Page 4 of 136 GENERAL DESCRIPTION The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and- hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimation filters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles. In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC. The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four- lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI). The AD9208 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent. Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant. PRODUCT HIGHLIGHTS 1. Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. 2. Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers. 3. Fast NCO switching enabled through the GPIO pins. 4. A SPI controls various product features and functions to meet specific system requirements. 5. Programmable fast overrange detection and signal monitoring. 6. On-chip temperature diode for system thermal management. 7. 12 mm × 12 mm, 196-ball BGA.

Rev. 0 | Page 5 of 136 SPECIFICATIONS DC SPECIFICATIONS SPIVDD = 1.9 V , specified maximum sampling rate, 1.7 V p-p full-scale differential input, input amplitude (AIN) = −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 1. Parameter Min Typ Max Unit RESOLUTION 14 Bits ACCURACY No Missing Codes Guaranteed Offset Error 0 %FSR Offset Matching 0 %FSR Gain Error −5.89 ±1 +5.89 %FSR Gain Matching −2.9 ±0.2 +2.9 %FSR Differential Nonlinearity (DNL) −0.63 ±0.4 +0.74 LSB Integral Nonlinearity (INL) −26 ±6 +21 LSB TEMPERATURE DRIFT Offset Error ±15 ppm/°C Gain Error 440 ppm/°C INTERNAL VOLTAGE REFERENCE 0.5 V INPUT-REFERRED NOISE 5.6 LSB rms ANALOG INPUTS Differential Input Voltage Range 1.7 V p-p Common-Mode Voltage(VCM) 1.32 1.35 1.52 V Differential Input Resistance 200 Ω Differential Input Capacitance 0.25 pF Differential Input Return Loss at 2.1 GHz2 −7 dB −3 dB Bandwidth 9 GHz POWER SUPPLY AVDD1 0.95 0.975 1.0 V AVDD2 1.85 1.9 1.95 V AVDD3 2.44 2.5 2.56 V AVDD1_SR 0.95 0.975 1.0 V DVDD 0.95 0.975 1.0 V DRVDD1 0.95 0.975 1.0 V DRVDD2 1.85 1.9 1.95 V SPIVDD 1.85 1.9 1.95 V IAVDD1 640 765 mA IAVDD2 790 885 mA IAVDD3 110 120 mA IAVDD1_SR 24 50 mA IDVDD 480 1020 mA IDRVDD13 320 590 mA IDRVDD2 30 35 mA ISPIVDD 1 5 mA POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)4 3.3 W Power-Down Dissipation 300 mW Standby5 1.65 mW 1 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C. 2 For more information, see the Analog Input Considerations section. 3 All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used. 4 Default mode. No DDCs used. 5 Can be controlled by the SPI.

Rev. 0 | Page 6 of 136 AC SPECIFICATIONS SPIVDD = 1.9 V , specified maximum sampling rate, 1.7 V p-p full-scale differential input, default SPI settings, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 2. AIN = −2 dBFS A IN = −9 dBFS Parameter2 Min Typ Max Min Typ Max Unit NOISE DENSITY3

1.7 V p-p Setting −152 −152 dBFS/Hz

2.04 V p-p Setting −154 −154 dBFS/Hz

NOISE FIGURE 24.5 24.5 dB SIGNAL-TO-NOISE RATIO (SNR) fIN = 255 MHz 60.2 60.2 dBFS fIN = 255 MHz (2.04 V p-p Setting) 61.4 61.8 dBFS fIN = 765 MHz 59.8 60.2 dBFS fIN = 900 MHz 59.5 60.2 dBFS fIN = 1800 MHz 58.7 60.0 dBFS fIN = 2100 MHz 58.2 59.8 dBFS fIN = 2600 MHz 52.1 57.2 59.5 dBFS fIN = 3950 MHz 55.1 58.6 dBFS SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 255 MHz 59.7 60.0 dBFS fIN = 255 MHz (2.04 V p-p Setting) 60.0 61.5 dBFS fIN = 765 MHz 58.8 60.0 dBFS fIN = 900 MHz 58.6 59.9 dBFS fIN = 1800 MHz 57.4 59.7 dBFS fIN = 2100 MHz 56.7 59.4 dBFS fIN = 2600 MHz 46.6 56.1 59.2 dBFS fIN = 3950 MHz 52.8 58.2 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 255 MHz 9.6 9.7 Bits fIN = 765 MHz 9.5 9.7 dBFS fIN = 900 MHz 9.4 9.7 Bits fIN = 1800 MHz 9.2 9.6 Bits fIN = 2100 MHz 9.1 9.6 Bits fIN = 2600 MHz 7.5 9.0 9.5 Bits fIN = 3950 MHz 8.5 9.4 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD HARMONIC fIN = 255 MHz 71 78 dBFS fIN = 255 MHz (2.04 V p-p Setting) 65 83 dBFS fIN = 765 MHz 71 79 dBFS fIN = 900 MHz 71 78 dBFS fIN = 1800 MHz 69 81 dBFS fIN = 2100 MHz 67 73 dBFS fIN = 2600 MHz 51 70 78 dBFS fIN = 3950 MHz 58 73 dBFS

Rev. 0 | Page 7 of 136 AIN = −2 dBFS A IN = −9 dBFS Parameter2 Min Typ Max Min Typ Max Unit WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC fIN = 255 MHz −89 −90 dBFS fIN = 255 MHz (2.04 V p-p Setting) −90 −90 dBFS fIN = 765 MHz −90 −89 dBFS fIN = 900 MHz −89 −90 dBFS fIN = 1800 MHz −81 −94 dBFS fIN = 2100 MHz −80 −98 dBFS fIN = 2600 MHz −75 −84 −90 dBFS fIN = 3950 MHz −80 −90 dBFS TWO-TONE, THIRD-ORDER INTERMODULATION DISTORTION (IMD3) fIN1 = 1.842 GHz, fIN2 = 1.847 GHz, AIN1 and AIN2 = −8.0 dBFS −73 dBFS fIN1 = 1.842 GHz, fIN2 = 1.847 GHz, AIN1 and AIN2 = −15.0 dBFS −87 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −8.0 dBFS −69 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −15.0 dBFS −88 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −8.0 dBFS; Full-Scale Voltage (VFS) = 1.13 V p-p −75 dBFS fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −15.0 dBFS; VFS = 1.13 V p-p −111 dBFS CROSSTALK4 >90 >90 dB Overrange Condition5 >90 >90 dB ANALOG INPUT BANDWIDTH, FULL POWER6 5 5 GHz 1 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to+ 85°C. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 3 Noise density is measured at a low analog input frequency (30 MHz). 4 Crosstalk is measured at 950 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel. 5 The overrange condition is specified with 3 dB of the full-scale input range. 6 Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved. DIGITAL SPECIFICATIONS SPIVDD = 1.9 V , specified maximum sampling rate, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 3. Parameter Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance LVDS/LVPECL Differential Input Voltage 300 800 1800 mV p-p Input Common-Mode Voltage 0.675 V Input Resistance (Differential) 106 Ω Input Capacitance 0.9 pF Differential Input Return Loss at 3 GHz2 −9.4 dB SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−) Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.675 2.0 V Input Resistance (Differential) 18 kΩ Input Capacitance (Differential) 1 pF LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0, FD_B/GPIO_B0, GPIO_A1, GPIO_B1) Logic Compliance CMOS Logic 1 Voltage 0.65 × SPIVDD V Logic 0 Voltage 0 0.35 × SPIVDD V Input Resistance 30 kΩ

Rev. 0 | Page 8 of 136 Parameter Min Typ Max Unit LOGIC OUTPUTS (SDIO, FD_A, FD_B) Logic Compliance CMOS Logic 1 Voltage (IOH = 4 mA) SPIVDD − 0.45V V Logic 0 Voltage (IOL = 4 mA) 0 0.45 V SYNCIN INPUT (SYNCINB+/SYNCINB−) Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.675 2.0 V Input Resistance (Differential) 18 kΩ Input Capacitance 1 pF SYNCINB+ INPUT Logic Compliance CMOS Logic 1 Voltage 0.9 × DRVDD1 2 × DRVDD1 V Logic 0 Voltage 0.1 × DRVDD1 V Input Resistance 2.6 kΩ DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7) Logic Compliance SST Differential Output Voltage 360 560 770 mV p-p Differential Termination Impedance 80 100 120 Ω 1 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to+85°C. 2 Reference impedance = 100 Ω.

Rev. 0 | Page 9 of 136 SWITCHING SPECIFICATIONS SPIVDD = 1.9 V , specified maximum sampling rate, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, default SPI settings, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C). Table 4. Parameter Min Typ Max Unit CLOCK Clock Rate (at CLK+/CLK− Pins) 3 6 GHz Sample Rate2 2500 3000 3100 MSPS Clock Pulse Width High 161.29 166.67 192.31 ps Clock Pulse Width Low 161.29 166.67 192.31 ps OUTPUT PARAMETERS Unit Interval (UI)3 62.5 66.67 592.6 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 26 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 26 ps Phase-Locked Loop (PLL) Lock Time 5 ms Data Rate per Channel (Nonreturn to Zero)4 1.6875 15 16 Gbps LATENCY5 Pipeline Latency6 75 Clock cycles Fast Detect Latency 26 Clock cycles WAKE-UP TIME Standby 400 μs Power-Down 15 ms NCO CHANNEL SELECTION TO OUTPUT 8 Clock cycles APERTURE Aperture Delay (tA) 250 ps Aperture Uncertainty (Jitter, tJ) 55 fs rms Out of Range Recovery Time 1 Clock cycles 1 The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C. 2 The maximum sample rate is the clock rate after the divider. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 Default L = 8. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 8, M = 2, and F = 1. 6 Refer to the Latency section for more details.

Figure 2. Data Output Timing Diagram

JC is the junction to case thermal resistance. Table 7. Thermal Resistance

1 Test Condition 1: Thermal impedance simulated values are based on JEDEC

2S2P thermal test board with 190 thermal vias. See JEDEC JESD51.

Figure 5. Pin Configuration (Top View)

Table 8. Pin Function Descriptions1 A3, A12, B3, B12, C3, C12 AVDD1 Power Analog Power Supply (0.975 V Nominal). AVDD2 Power Analog Power Supply (1.9 V Nominal). D1, D14, G1, G14 AVDD3 Power Analog Power Supply (2.5 V Nominal). E7 AVDD1_SR Power Analog Power Supply for SYSREF± (0.975 V Nominal). L3, L10 SPIVDD Power Digital Power Supply for SPI (1.9 V Nominal). M14, N1, N2, N14, P1, P2, P14 DVDD Power Digital Power Supply (0.975 V Nominal). M5 to M8, M11 DRVDD1 Power Digital Driver Power Supply (0.975 V Nominal). M13 DRVDD2 Power Digital Driver Power Supply (1.9 V Nominal). A6, A9, B6 to B9, C6 to C9, D7, D8 AGND 2 Ground Ground Reference for the Clock Domain. E6, E8 AGND3 Ground Ground Reference for SYSREF±. K1 to K14 AGND4 Ground Isolation Ground. the digital driver ground plane. E1, F1 VIN−B, VIN+B Input ADC B Analog Input Complement/True. E14, F14 VIN−A, VIN+A Input ADC A Analog Input Complement/True. A7, A8 CLK+, CLK− Input Clock Input True/Complement. input if using an external voltage reference source. L2 GPIO_B1 Input/output GPIO B1. L4 FD_B/GPIO_B0 Input/output Fast Detect Outputs for Channel B/GPIO B0. L9 FD_A/GPIO_A0 Input/output Fast Detect Outputs for Channel A/GPIO A0. L11 GPIO_A1 Input/output GPIO A1. N13 SYNCINB+ Input Active Low JESD204B LVDS/CMOS Sync Input True. P13 SYNCINB− Input Active Low JESD204B LVDS Sync Input Complement. N4, P4 SERDOUT7+, SERDOUT7− Output Lane 7 Output Data True/Complement. N5, P5 SERDOUT6+, SERDOUT6− Output Lane 6 Output Data True/Complement. N6, P6 SERDOUT5+, SERDOUT5− Output Lane 5 Output Data True/Complement. N7, P7 SERDOUT4+, SERDOUT4− Output Lane 4 Output Data True/Complement. N8, P8 SERDOUT3+, SERDOUT3− Output Lane 3 Output Data True/Complement. N9, P9 SERDOUT2+, SERDOUT2− Output Lane 2 Output Data True/Complement. N10, P10 SERDOUT1+, SERDOUT1− Output Lane 1 Output Data True/Complement. N11, P11 SERDOUT0+, SERDOUT0− Output Lane 0 Output Data True/Complement.

Rev. 0 | Page 15 of 136 Pin No. Mnemonic Type Description Digital Controls L8 PDWN/STBY Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby. L5 CSB Input SPI Chip Select (Active Low). L6 SCLK Input SPI Serial Clock. L7 SDIO Input/output SPI Serial Data Input/Output. 1 See the Theory of Operation section and the Applications Information section for more information on isolating the planes for optimal performance. 2 Denotes clock domain. 3 Denotes SYSREF± domain. 4 Denotes isolation domain.

Figure 36. SNR vs. Sample Frequency (fS), fIN = 1.8 GHz; AIN = −2 dBFS and −9 dBFS Figure 37. SFDR vs. Sample Frequency (fS), fIN = 1.8 GHz; AIN = −2 dBFS and Figure 38. Power Dissipation vs. Sample Frequency (fS), fIN = 1.8 GHz; AIN = −2 dBFS Figure 39. Input Bandwidth (See Figure 55 for the Input Configuration)

10000 NUMBER OF HITS

Figure 40. Input Referred Noise Histogram

Figure 57. Analog Input Controls adjustment. All the available controls are shown in Figure 57. reference voltage results in a change in the input full-scale voltage. AVDD3 supply changes. This relationship is shown in Figure 58. For a complete list of buffer current settings, see Table 46. Figure 58. AVDD3 Current (IAVDD3) vs. Buffer Current Setting (Buffer Control 1 Table 10. SFDR Optimization for Input Frequencies

1500 MHz to 3000 MHz 500 μA

The dither is on by default. It is not recommended to turn it off.

in this register, and the chip Q ignore is controlled by Bit 5. sample rate/the chip decimation ratio. separate virtual converters. the transport layer mapping when channel swapping is disabled. the DDC outputs when complex outputs are used. eight virtual converters, depending on the DDC configuration. is used with two real converters producing I/Q outputs. for I/Q transport layer mapping. Table 11. Virtual Converter Mapping

1 One DDC mode

2 One DDC mode

2 Two DDC mode

4 Two DDC mode

4 Four DDC mode

8 Four DDC mode

Figure 77. DDCs and Virtual Converter Mapping

Figure 78. I/Q Transport Layer Mapping

1. Enable the sample clock to the device.
2. Configure the mode registers as follows:

Register 0x0DF8 and Register 0x0DF9.

1. Wait at least 5 μs to allow the programmable filter to power up.
2. Program the I path coefficients to the internal shadow

Register 0x0E2F (see Table 14 and Table 15). Register 0x0F2F (see Table 14 and Table 15). that this step is optional).

1. Program the Q path coefficients to the internal shadow

Register 0x0DF9 (see Table 12 and Table 13). that this step is optional).

1. Set the chip transfer bit using either of the following

bit (Register 0x000F = 0x01). transfer bit in Register 0x0040 to Register 0x0042. (the rising edge is triggered).

1. When the I or Q path mode register changes in

Register 0x0DF8, all coefficients must be reprogrammed. Table 12. Register 0x0DF8 Definition Table 13. Register 0x0DF9 Definition

7 Reserved

3 Reserved

are Q1.15 format (sign bit + 15 fractional bits).

Table 14. I Coefficient Table (Device Selection = 0x1)1 1 XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n. 2 When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode. 3 When using the I path in 96-tap filter mode, the Q path must be in bypass mode. Table 15. Q Coefficient Table (Device Selection = 0x2)1 1 XQ Cn means Q Path X Coefficient n. YQ Cn means Q Path Y Coefficient n. 2 When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode. 3 When using the I path in 96-tap filter mode, the Q path must be in bypass mode.

Figure 84. DDC Detailed Block Diagram

4 DIGITAL HALF-BAND FILTERS

Figure 85. DDC Theory of Operation Example (Real Input)

baseband complex digital output (carrier frequency = 0 Hz). frequency can be used to digitally tune the IF frequency.

0 Hz IF (ZIF) Mode

In this mode, the mixers are bypassed, and the NCO is disabled. directly drive the decimation filters. translation stage for both real and complex inputs. Figure 86. DDC NCO Frequency Tuning Word Selection—Real Inputs

2 ADCs + QUADRATURE DIGITAL

Figure 87. DDC NCO Frequency Tuning Word Selection—Complex Inputs

Rev. 0 | Page 46 of 136 NCO FTW/POW/MAW/MAB Description The NCO frequency value is determined by the following settings:  48-bit twos complement number entered in the FTW  48-bit unsigned number entered in the MAW  48-bit unsigned number entered in the MBW Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are represented using the following values:  FTW = 0x8000_0000_0000 and MAW = 0x0000_0000_0000 represents a frequency of –fS/2.  FTW = 0x0000_0000_0000 and MAW = 0x0000_0000_0000 represents dc (frequency is 0 Hz).  FTW = 0x7FFF_FFFF_FFFF and MAW = 0x0000_0000_0000 represents a frequency of +f S/2. NCO FTW/POW/MAW/MAB Programmable Modulus Mode For programmable modulus mode, the MAW must be set to a nonzero value (not equal to 0x0000_0000_0000). This mode is only needed when frequency accuracy of >48 bits is required. One example of a rational frequency synthesis requirement that requires >48 bits of accuracy is a carrier frequency of 1/3 the sample rate. When frequency accuracy of ≤48 bits is required, coherent mode must be used (see the NCO FTW/POW/ MAW/MAB Coherent Mode section). In programmable modulus mode, the FTW , MAW , and MBW must satisfy the following four equations (for a detailed description of the programmable modulus feature, see the DDS architecture described in the AN-953 Application Note): 482 ) , mod( MBW MAWFTW N M f f f s s c   (1) )) , mod(2 floor(48 s s c f f fFTW  (2) MAW = mod(248 × M,N) (3) MBW = N (4) where: fC is the desired carrier frequency. fS is the ADC sampling frequency. M is the integer representing the rational numerator of the frequency ratio. N is the integer representing the rational denominator of the frequency ratio. FTW is the 48-bit twos complement number representing the NCO FTW . MA W is the 48-bit unsigned number representing the NCO MAW (must be <2 47). MBW is the 48-bit unsigned number representing the NCO MBW . mod(x) is a remainder function. For example, mod(110,100) = 10 and for negative numbers, mod(–32,10)= –2. floor(x) is defined as the largest integer less than or equal to x. For example, floor(3.6) = 3. Note that Equation 1 to Equation 4 apply to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). M and N are integers reduced to their lowest terms. MAW and MBW are integers reduced to their lowest terms. When MAW is set to zero, the programmable modulus logic is automatically disabled. For example, if the ADC sampling frequency (f S) is 3000 MSPS and the carrier frequency (fC) is 1001.5 MHz, then, 6000 2003 3000 ) 3000 , 5 . 1001 mod(  N M 0_FB380x5576_19F )3000 ) 3000 , 5 . 1001 mod(2 floor(48 FTW MAW = mod(248 × 2003, 6000) = 0x0000_0000_0F80 MBW = 0x0000_0000_1770 The actual carrier frequency can be calculated based on the following equation: 48_ S ACTUALC fMBW MAWFTW f   For the previous example, the actual carrier frequency (fC_ACTUAL) is MHz 5 . 1001 0_17700x0000_000 0_0F800x0000_0000_FB380x5576_19F ACTUALCf A 48-bit POW is available for each NCO to create a known phase relationship between multiple chips or individual DDC channels inside the chip. While in programmable modulus mode, the FTW and POW registers can be updated at any time while still maintaining deterministic phase results in the NCO. However, the following procedure must be followed to update the MAW and/or MBW registers to ensure proper operation of the NCO: Write to the MAW and MBW registers for all the DDCs. 2. Synchronize the NCOs either through the DDC soft reset bit accessible through the SPI or through the assertion of the SYSREF± pin (see the Memory Map section).

Rev. 0 | Page 49 of 136 The phase coherent NCO switching feature allows an infinite number of frequency hops that are all phase coherent. The initial phase of the NCO is established at time, t 0, from SYSREF± synchronization. Switching the NCO FTW does not affect the phase. With this feature, only one FTW is required, but the user may wish to use all 16 channels to queue up the next hop. After SYSREF± synchronization at startup, all NCOs across multiple chips are inherently synchronized. Setting Up the Multichannel NCO Feature The first step to configure the multichannel NCO is to program the FTWs. The AD9208 memory map has an FTW index register for each DDC. This index determines which NCO channel receives the FTW from the register map. The following sequence describes the method for programming the FTWs: 1. Write the FTW index register with the desired DDC channel. 2. Write the FTW with the desired value. This value is applied to the NCO channel index mentioned in Step 1. 3. Repeat Step 1 and Step 2 for other NCO channels. After setting the FTWs, the user must then select an active NCO channel. This selection can be performed either through the SPI registers or through the external GPIO pins. The following sequence describes the method for selecting the active NCO channel using the SPI: Set the NCO channel select mode bits (Bits[7:4] in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374) to 0x0 to enable SPI selection. 2. Choose the active NCO channel using Bits[3:0] in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374. The following sequence describes the method for selecting the active NCO channel using the GPIO CMOS pins: Set the NCO channel select mode bits (Bits[7:4] in Register 0x0314, Register 0x0334, Register 0x0354, and Register 0x0374) to a nonzero value to enable GPIO pin selection. Configure the GPIO pins as NCO channel selection inputs by writing to Register 0x0040, Register 0x0041, and Register 0x0042. NCO switching is performed by externally controlling the GPIO CMOS pins. NCO Synchronization Each NCO contains a separate phase accumulator word (PAW). The initial reset value of each PAW is set to zero and incremented every clock cycle. The instantaneous phase of the NCO is c a l c u l a t e d u s i n g t h e PAW, F T W, M AW, M B W, a n d P O W. D u e t o this architecture, the FTW and POW registers can be updated at any time while still maintaining deterministic phase results in the PAW of the NCO. Two methods can be used to synchronize multiple PAWs within the chip: Using the SPI. Use the DDC soft reset bit in the DDC synchronization control register (Register 0x0300, Bit 4) to reset all the PAWs in the chip. This reset is accomplished by setting the DDC soft reset bit high, and then setting this bit low. Note that this method can only be used to synchronize DDC channels within the same chip. Using the SYSREF± pin. When the SYSREF± pin is enabled in the SYSREF control registers (Register 0x0120 and Register 0x0121), and the DDC synchronization is enabled in the DDC synchronization control register (Register 0x0300, Bits[1:0]), any subsequent SYSREF± event resets all the PAWs in the chip. Note that this method can be used to synchronize DDC channels within the same chip or DDC channels within separate chips. NCO Multichip Synchronization In some applications, it is necessary to synchronize all the NCOs and local multiframe clocks (LMFCs) within multiple devices in a system. For applications requiring multiple NCO tuning frequencies in the system, a designer likely needs to generate a single SYSREF pulse at all devices simultaneously. For many systems, generating or receiving a single-shot SYSREF pulse at all devices is challenging because of the following factors: Enabling or disabling the SYSREF pulse is often an asynchronous event.  Not all clock generation chips support this feature. For these reasons, the AD9208 contains a synchronization triggering mechanism that allows the following:  Multichip synchronization of all NCOs and LMFCs at system startup.  Multichip synchronization of all NCOs after applying new tuning frequencies during normal operation. The synchronization triggering mechanism uses a master/slave arrangement, as shown in Figure 91.

1 LINK,

Figure 91. System Using Master/Slave Synchronization Triggering their NSTE from an external slave next trigger input (SNTI) pin. the FD/GPIO pins for this operation. synchronizes all the NCOs and LMFCs in the system at once. See the Setting Up the Multichannel NCO Feature section. Figure 92. NCO Multichip Synchronization at Startup (Using Triggering and SYSREF)

Register 0x0350, and Register 0x0370). image. An additional −0.05 dB of loss is introduced by the NCO. signal mixed down to baseband is −3.11 dB. 102 dBc SFDR for all output frequencies.

0 Hz), these filters efficiently lower the sample rate, while

carriers around the bandwidth of interest. the different finite impulse response (FIR) filter blocks.

1. TB1 IS ONLY SUPPORTED IN DDC0 AND DDC1

Figure 93. DDC Decimation Filter Block Diagram

Table 16. DDC Decimation Filter Characteristics 1 TB1 is only supported in DDC0 and DDC1. Table 17. DDC Filter Configurations1 2 Ideal SNR improvement due to oversampling + filtering = 10log(bandwidth/fS/2). 3 TB1 is only supported in in DDC0 and DDC1. Table 18. DDC Filter Configurations (fS = 3000 MSPS)1

3000 HB1 1 3000 2 1500 (I) + 1500 (Q) 1200

2 TB1 is only supported in in DDC0 and DDC1.

filter response. TB1 is only supported in DDC0 and DDC1. Table 24. TB1 Filter Coefficients Figure 99. TB1 Filter Response

Table 25. FB2 Filter Coefficients Figure 100. FB2 Filter Response

decimation ratio is different than the DDC decimation ratio. resulting output samples are shown in Table 27. Table 26. Sample Mapping when the Chip Decimation Ratio (DCM) Does Not Match DDC DCM

0 N N N N

1 N + 1 N N N

2 N + 2 N + 1 N N

3 N + 3 N + 1 N N

4 N + 4 N + 2 N + 1 N

5 N + 5 N + 2 N + 1 N

6 N + 6 N + 3 N + 1 N

7 N + 7 N + 3 N + 1 N

8 N + 8 N + 4 N + 2 N + 1

9 N + 9 N + 4 N + 2 N + 1

10 N + 10 N + 5 N + 2 N + 1

11 N + 11 N + 5 N + 2 N + 1

12 N + 12 N + 6 N + 3 N + 1

13 N + 13 N + 6 N + 3 N + 1

14 N + 14 N + 7 N + 3 N + 1

15 N + 15 N + 7 N + 3 N + 1

16 N + 16 N + 8 N + 4 N + 2

17 N + 17 N + 8 N + 4 N + 2

18 N + 18 N + 9 N + 4 N + 2

19 N + 19 N + 9 N + 4 N + 2

20 N + 20 N + 10 N + 5 N + 2

21 N + 21 N + 10 N + 5 N + 2

22 N + 22 N + 11 N + 5 N + 2

23 N + 23 N + 11 N + 5 N + 2

24 N + 24 N + 12 N + 6 N + 3

25 N + 25 N + 12 N + 6 N + 3

26 N + 26 N + 13 N + 6 N + 3

27 N + 27 N + 13 N + 6 N + 3

28 N + 28 N + 14 N + 7 N + 3

29 N + 29 N + 14 N + 7 N + 3

30 N + 30 N + 15 N + 7 N + 3

31 N + 31 N + 15 N + 7 N + 3

Table 27. Chip DCM = 4, DDC0 DCM = 4 (Complex), and DDC1 DCM = 8 (Real)1 Table 28 describes the register settings for multiple DDC example configurations. Table 28. DDC Example Configurations (Per ADC Channel Pair)

Rev. 0 | Page 60 of 136 Chip Application Layer Chip Decimation Ratio DDC Input Type DDC Output Type Bandwidth Per DDC1 No. of Virtual Converters Required Register Settings Two DDCs 4 Complex Real 10% × f S 2 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311, 0x0331 = 0x04 (DDC I Input = ADC Channel A; DDC Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 Two DDCs 4 Real Real 10% × f S 2 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 Two DDCs 4 Real Complex 20% × f S 4 0x0200 = 0x02 (two DDCs; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain; variable IF; complex output; HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 Two DDCs 8 Real Real 5% × f S 2 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1

Rev. 0 | Page 61 of 136 Chip Application Layer Chip Decimation Ratio DDC Input Type DDC Output Type Bandwidth Per DDC1 No. of Virtual Converters Required Register Settings Four DDCs 8 Real Complex 10% × f S 8 0x0200 = 0x03 (four DDCs; I/Q selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330, 0x0350, 0x0370 = 0x41 (real mixer; 6 dB gain; variable IF; complex output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3 Four DDCs 8 Real Real 5% × f S 4 0x0200 = 0x23 (four DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330, 0x0350, 0x0370 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3

Rev. 0 | Page 62 of 136 Chip Application Layer Chip Decimation Ratio DDC Input Type DDC Output Type Bandwidth Per DDC1 No. of Virtual Converters Required Register Settings Four DDCs 16 Real Complex 5% × f S 8 0x0200 = 0x03 (four DDCs; I/Q selected) 0x0201 = 0x04 (chip decimate by 16) 0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer; 6 dB gain; variable IF; complex output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC3 1 fS is the ADC sample rate.

Table 29 describes the typical and maximum DVDD and DRVDD1 power for certain DDC modes; fS = 3 GHz in all cases. Table 29. DDC Power Consumption for Example Configurations 1 See Table 17 and Table 18 for details on decimation filter selection, the associated alias protected bandwidths, and SNR improvements.

range of the ADC in the presence of real-world signals. shows the simplified block diagram of the signal monitor block. Figure 102. Signal Monitor Block before activating this mode.

deserialized from the samples to reconstruct the statistical data. however, only one control bit is required for the signal monitor. program Register 0x0559, Register 0x055A, and Register 0x058F. See Table 46 for more information on setting these bits. that can be used by a receiver to validate the deserialized data. data with a monitor period timer set to 80 samples.

1 TAIL

Figure 103. Signal Monitor Control Bit Locations

0 P [ 0 ] 000

Figure 104. SPORT over JESD204B Signal Monitor Frame Data

80 SAMPLE PERIOD

Figure 105. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples

mode signal by default, but it can also be driven single-ended. operation, refer to Register 0x0572. sequence is never scrambled. ends with an /A/ character (/K28.3/). are of the value − 1 notation. ends with an /A/ character (/K28.3/). ends with an /A/ character (/K28.3/). enabled by default; however, it can be disabled using the SPI. it is at the end of a multiframe. the Memory Map section, Register 0x0571. and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 30. using the same number of ones and zeros across multiple symbols. for information on configuring the 8-bit/10-bit encoder.

• ●●D A R Q D A R D D A R D D END OF MULTIFRAME A DC C D START OF LINK CONFIGURATION DATA START OF USER DATA 15547-104

Figure 109. Initial Lane Alignment Sequence Table 30. AD9208 Control Characters used in JESD204B 1 RD means running disparity.

Figure 110. AC-Coupled Digital Output Termination Example 100 Ω internal termination to reduce unwanted reflections. Register 0x05C3 in Table 46) for more details. the receiver inputs as possible. together and at equal lengths. the Memory Map section (Register 0x0561 in Table 46). Figure 111. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps Figure 112. Digital Outputs Jitter Histogram, External 100 Ω Terminations at

16 Gbps

Figure 113. Digital Outputs Bathtub Curve, External 100 Ω Terminations at in Table 46) for more details. following a link power cycle. lane rates supported by the AD9208 using Register 0x056E. Table 31. AD9208 Register 0x056E Supported Lane Rates

Hard reset, as with power-up.  Power-up using the PDWN pin.  Power-up using the SPI via Register 0x0002, Bits[1:0].  SPI soft reset by setting Register 0x0000 = 0x81.  Datapath soft reset by setting Register 0x0001 = 0x02. The initialization SPI writes are as shown in Table 32. Table 32. AD9208 JESD204B Initialization mapping setup is shown in Figure 77.

1. Select the JESD204B link configuration options.
2. Configure the detailed options.
3. Set output lane mapping (optional).
4. Set additional driver configuration options (optional).
5. Initialize the JESD204B link by issuing the commands

Table 33. JESD204B Output Configurations for N΄ = 161

1.7 Gbps to

3.4 Gbps

3.4 Gbps to

6.8 Gbps

6.8 Gbps to

13.6 Gbps

13.6 Gbps to

15.5 Gbps L M F S HD N N' CS K

Rev. 0 | Page 73 of 136 Number of Virtual Converters Supported (Same as M) JESD204B Serial Lane Rate Supported Decimation Rates JESD204B Transport Layer Settings3 Lane Rate = Lane Rate = Lane Rate = Lane Rate =

15.5 Gbps

L M F S HD N N' CS K 2 40 × fOUT 4, 8, 10, 12, 15, 16, 20, 24, 30, 40, 48 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1 2 4 1 0 8 to 16 16 0 to See Note 4 40 × fOUT 4, 8, 10, 12, 15, 16, 20, 24, 30, 40, 48 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1 2 8 2 0 8 to 16 16 0 to See Note 4 20 × fOUT 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 2 2 2 1 0 8 to 16 16 0 to See Note 4 20 × fOUT 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 2 2 4 2 0 8 to 16 16 0 to See Note 4 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 4 2 1 1 1 8 to 16 16 0 to See Note 4 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 4 2 2 2 0 8 to 16 16 0 to See Note 4 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 8 2 1 2 1 8 to 16 16 0 to See Note 4 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 8 2 2 4 0 8 to 16 16 0 to See Note 4 4 80 × fOUT 8, 16, 20, 24, 30, 40, 48 4, 8, 10, 12, 16, 20, 24, 30, 40, 16, 20, 24, 30 1 4 8 1 0 8 to 16 16 0 to See Note 4 40 × fOUT 4, 8, 10, 12, 15, 16, 20, 24, 30, 40, 48 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 2 4 4 1 0 8 to 16 16 0 to See Note 4 40 × fOUT 4, 8, 10, 12, 15, 16, 20, 24, 30, 40, 48 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 2 4 8 2 0 8 to 16 16 0 to See Note 4 20 × fOUT 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 4 4 2 1 0 8 to 16 16 0 to See Note 4 20 × fOUT 2, 4, 5, 6, 8, 10, 12, 15, 16, 20, 24, 30 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 4 4 4 2 0 8 to 16 16 0 to See Note 4 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 8 4 1 1 1 8 to 16 16 0 to See Note 4 10, 12, 15, 16 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 8 4 2 2 0 8 to 16 16 0 to See Note 4 8 160 × fOUT 16, 40, 48 8, 16, 20, 24, 40, 4, 8, 12, 16, 20, 24, 40, 48 4, 8, 12, 16, 20, 1 8 16 1 0 8 to 16 16 0 to See Note 4 80 × fOUT 8, 16, 20, 24, 40, 48 4, 8, 10, 12, 16, 20, 24, 40, 48 16, 20, 24 2 8 8 1 0 8 to 16 16 0 to See Note 4 40 × fOUT 4, 8, 10, 12, 16, 20, 24, 40, 48 16, 20, 24 2, 4, 6, 8 4 8 4 1 0 8 to 16 16 0 to See Note 4 40 × fOUT 4, 8, 10, 12, 16, 20, 24, 40, 48 16, 20, 24 2, 4, 6, 8 4 8 8 2 0 8 to 16 16 0 to See Note 4 20 × fOUT 2, 4, 6, 8, 10, 12, 16, 20, 24 2, 4, 6, 8 2, 4 8 8 2 1 0 8 to 16 16 0 to See Note 4 20 × fOUT 2, 4, 6, 8, 10, 12, 16, 20, 24 2, 4, 6, 8 2, 4 8 8 4 2 0 8 to 16 16 0 to See Note 4 1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. 2 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 3 fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

Table 34. JESD204B Output Configurations (N' = 12)1

13.5 Gbps

1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64.

Table 32. JESD204B Output Configurations for N΄ = 81

13.5 Gbps to

1 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64.

Figure 116. Full Bandwidth Mode  Two 14-bit converters at 2.94912 GSPS.  Full bandwidth application layer mode.  Decimation filters bypassed. Two virtual converters required (see Table 33).  Output serial lane rate = 14.7456 Gbps per lane.  The PLL control register, Register 0x056E, is set to 0x30.

Figure 117. Two ADCs Plus Two DDCs Mode (L = 4, M = 4, F = 2, S = 1)  Two 14-bit converters at 2.94912 GSPS.  Chip decimation ratio = 8.  DDC decimation ratio = 8 (see Table 46).  Four virtual converters required (see Table 33). For L = 2, set the PLL control register, Register 0x056E, to 0x30. For L = 4, set the PLL control register, Register 0x056E, to 0x00.

defined as Subclass 1 and Subclass 2. of the receiver to capture and align the lanes within the link. and multiframes as described in the Transport Layer section. power cycles and link reset conditions. latency in a JESD204B Subclass 1 system. be less than the desired uncertainty for the system. for each device in the system. Figure 118. SYSREF and LMFC

by the chip synchronization mode bit (Register 0x01FF, Bit 0). Each method involves different applications of the SYSREF signal. that the JESD204B receivers are configured appropriately. used for synchronization of multiple channels and/or devices.  Register 0x0559, Bits[3:0] = 5 if using Control Bit 0.  Register 0x0559, Bits[7:4] = 5 if using Control Bit 1.  Register 0x055A, Bits[3:0] = 5 if using Control Bit 2. operating modes that use decimation.

2 CONTROL BITS

Figure 121. AD9208 Timestamping Example—CS = 2 (Register 0x058F, Bits[7:6] = 2), Control Bit 0 is SYSREF (Register 0x0559, Bits[3:0] = 5)

Figure 122. SYSREF Capture Scenarios and Multichip Synchronization

Figure 130. SYSREF± Hold Detector Table 36. SYSREF± Setup/Hold Monitor, Register 0x0128 0x0 0x0 to 0x7 Possible setup error. The smaller this number, the smaller the setup margin. 0x0 to 0x8 0x8 No setup or hold error (best hold margin). 0x8 0x9 to 0xF No setup or hold error (best setup and hold margin). 0x8 0x0 No setup or hold error (best setup margin). 0x9 to 0xF 0x0 Possible hold error. The larger this number, the smaller the hold margin. 0x0 0x0 Possible setup or hold error.

Rev. 0 | Page 86 of 136 LATENCY END TO END TOTAL LATENCY Tot a l l ate nc y in t he AD9208 is dependent on the chip application mode and the JESD204B configuration. For any given combination of these parameters, the latency is deterministic, however, the value of this deterministic latency must be calculated as described in the Example Latency Calculations section. Table 34 shows the combined latency through the ADC and DSP for the different chip application modes supported by the AD9208. Table 35 shows the latency through the JESD204B block for each application mode based on the M/L ratio. For both tables, latency is typical and is in units of the encode clock. The latency through the JESD204B block does not depend on the output data type (real or complex). Therefore, data type is not included in Table 35. To determine the total latency, select the appropriate ADC + DSP latency from Table 34 and add it to the appropriate JESD204B latency from Table 35. Example calculations are provided in the following section. EXAMPLE LATENCY CALCULATIONS Example Configuration 1 is as follows:  ADC application mode = full bandwidth  Real outputs  L = 8, M = 2, F = 1, S = 2 (JESD204B mode)  20 × (M/L) = 5  Latency = 31 + 44 = 75 encode clocks Example Configuration 2 is as follows:  ADC application mode = DCM4  Complex outputs  L = 4, M = 2, F = 1, S = 1 (JESD204B mode)  20 × (M/L) = 10  Latency = 162 + 88 = 250 encode clocks LMFC REFERENCED LATENCY Some FPGA vendors may require the end user to know LMFC- referenced latency to make appropriate deterministic latency adjustments. If they are required, the latency values in Table 34 and Table 35 can be used for the analog in to LMFC and LMFC to data out latency values.

Table 37. Latency Through the ADC + DSP Blocks (Number of Sample Clocks)1 1 DCMx indicates the decimation ratio. Table 38. Latency Through JESD204B Block (Number of Sample Clocks)1 1 N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed. 2 M/L ratio is the number of converters divided by the number of lanes for the configuration. 3 The application mode at the M/L ratio listed is only supported in real output mode. 4 The application mode at the M/L ratio listed is only supported in complex output mode.

Table 39. When an output test mode is enabled, the analog section and the test pattern is run through the output formatting block. Table 39. ADC Test Modes

0000 Off (default) Not applicable Not applicable Not applicable

0001 Midscale short 0000 0000 0000 Not applicable Not applicable

0100 Checkerboard 10 1010 1010 1010 Not applicab le 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555

0101 PN sequence long x 23 + x18 + 1 0x3AFF 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6

0110 PN sequence short x 9 + x5 + 1 0x0092 0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697

0111 One-/zero-word toggle 11 1111 1111 1111 Not appl icable 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000

1000 User input Register 0x0551 to

1111 Ramp output (x) % 214 Not applicable (x) % 2 14, (x +1) % 214, (x +2) % 214, (x +3) % 214

reset. This is done by writing 0x81 to Register 0x0000 (self cleared). defined by Section 5.1.6.3 in the JEDEC JESD204B specification. is equivalent to the raw samples from the ADC. The interface test modes are described in Register 0x0573, Bits[3:0]. Bits[5:4] show where these tests are injected. Table 40. JESD204B Interface Test Modes

0000 Off (default) Not applicable Not applicable

0001 Alternating checker board 0x5555, 0xAAAA, 0x5555, … Not applicable

1000 Ramp output (x) % 216 Ramp size depends on test injection point

1111 Single user test Register 0x0551 to Register 0x0558 User Pattern 1 to User Pattern 4, then zeros

Table 41. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00)

Table 42. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01) Table 43. Scrambler 8-bit Input (Register 0x0573, Bits[5:4] = 'b10)

flexibility and customization, depending on the application. see the Serial Control Interface Standard (Rev. 1.0). Table 44. SPI Pins synchronize serial interface, reads, and writes. mode turns on any SPI pin secondary functions. direction from an input to an output. Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. device specific features are described in the Memory Map section. Table 45. Features Accessible Using the SPI Mode Allows the user to set either power-down mode or standby mode. Clock Allows the user to access the clock divider via the SPI. DDC Allows the user to set up decimation filters for different applications. Test Input/Output Allows the user to set test modes to have known data on output bits. Output Mode Allows the user to set up outputs. SERDES Output Setup Allows the user to vary SERDES settings such as swing and emphasis.

Rev. 0 | Page 92 of 136 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is divided into the following sections:  Analog Devices SPI registers (Register 0x0000 to Register 0x000F)  Clock/SYSREF/chip power-down pin control registers (Register 0x003F to Register 0x0201)  Fast detect and signal monitor control registers (Register 0x0245 to Register 0x027A)  DDC function registers (Register 0x0300 to Register 0x03CD) Digital outputs and test modes registers (Register 0x0550 to Register 0x05CB)  Programmable filter control and coefficients registers (Register 0x0DF8 to Register 0x0F7F)  VREF/analog input control registers (Register 0x18A6 to Register 0x1A4D) Table 43 (see the Memory Map Register Details section) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x0561, the output sample mode register, has a hexadecimal default value of 0x01, which means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see Table 43. Open and Reserved Locations All address and bit locations that are not included in Table 43 are not currently supported for this device. Write unused bits of a valid address location with 0s unless the default value is set otherwise. Writing to these locations is required only when part of an address location is unassigned (for example, Address 0x0561). If the entire address location is open (for example, Address 0x0013), do not write to this address location. Default Values After the AD9208 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 43. Logic Levels An explanation of logic level terminology follows:  “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ”  “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” X denotes a don’t care bit. Channel Specific Registers Some channel setup functions, such as the buffer control register (Register 0x1A4C), can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 43 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x0008. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the device returns the value for Channel A. Registers and bits designated as global in Table 43 affect the entire device and the channel features for which independent settings are not allowed between channels. The settings in Register 0x0005 do not affect the global registers and bits. SPI Soft Reset After issuing a soft reset by programming 0x81 to Register 0x0000, the AD9208 requires 5 ms to recover. When programming the AD9208 for application setup, ensure that an adequate delay is programmed into the firmware after asserting the soft reset and before starting the device setup.

All address locations that are not included in Table 46 are not currently supported for this device and must not be written. Table 46. Memory Map Register Details the boot loader to complete. 1 Reset the SPI and registers (self clearing).

6 LSB first mirror 0x0 R/W

1 Least significant bit (LSB) sh ifted first for all SPI operations. 0 Most significant bit (MSB) shifted first for all SPI operations.

5 Address ascension mirror 0x0 R/W

0 Multibyte SPI operations ca use addresses to autodecrement. 1 Multibyte SPI operations ca use addresses to autoincrement.

2 Address ascension 0x0 R/W

0 Multibyte SPI operations ca use addresses to auto-decrement. 1 Multibyte SPI operations cause addresses to auto-increment.

1 LSB first 0x0 R/W

1 LSB shifted first for all SPI operations. 0 MSB shifted first for all SPI operations.

0 Soft reset (self clearing) Whenever a soft reset is issued, the user must wait 5 ms before

the boot loader to complete. 1 Reset the SPI and registers (self clearing).

1 Datapath soft reset

1 Datapath soft reset (self clearing).

10 Standby mode; digital datapath clocks disabled; JESD204B

11 Power-down mode; digital datapath clocks disabled; digital

datapath held in reset; JESD204B interface disabled.

1 Channel B 0x1 R/W

0 ADC Core B does not receive the next SPI command. 1 ADC Core B receives the next SPI command.

0 Channel A 0x1 R/W

0 ADC Core A does not receive the next SPI command. 1 ADC Core A receives the next SPI command. memory location for software debugging.

Rev. 0 | Page 94 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x000C Vendor ID LSB [7:0] Vendor ID LSB Vendor ID [7:0]. 0x56 R 0x000D Vendor ID MSB [7:0] Vendor ID MSB Vendor ID [15:8]. 0x04 R 0x000F Transfer [7:1] Reserved Reserved. 0x0 R 0 Chip transfer Self clearing chip tran sfer bit. This bit is used to update the DDC phase increment and phase offset registers when DDC phase update mode (Register 0x0300, Bit 7 ) = 1. This makes it possible to synchronously update the DDC mixer frequencies. This bit is also used to update the coefficients for the programmable filter (PFILT). 0x0 R/W 0 Do nothing. Bit is only cl eared after transfer is complete.

1 Self clearing bit used to synchronize the transfer of data from

master to slave registers. Clock/SYSREF/Chip PDWN Pin Control Registers 0x003F Chip PDWN pin (local)

7 Local chip PDWN pin

Function is determined by Regi ster 0x0040, Bits[7:6]. 0x0 R/W 0 Power-down pin (PDWN/STBY) enabled (default). 1 Power-down pin (PDWN/STBY) disabled/ignored. [6:0] Reserved Reserved. 0x0 R 0x0040 Chip Pin Control 1 [7:6] Global chip PDWN pin functionality External power-down pin functionality. Assertion of the external power-down pin (PDWN/STBY) has higher priority than the channel power mode control bits (Register 0x0002, Bits[1:0]). The PDWN/STBY pin is only used when Register 0x0040, Bits[7:6] = 00 or 01. 0x0 R/W 00 Power-down pin (default). Assertion of external power-down pin (PDWN/STBY) causes the chip to enter full power-down mode. 01 Standby pin. Assertion of external power-down pin (PDWN/STBY) causes the chip to enter standby mode. 10 Pin disabled. Power-down pin (PDWN/STBY) is ignored. [5:3] Chip FD_B/GPIO_B0 pin functionality Fast Detect B/GPIO B0 pin functionality. 0x7 R/W 000 Fast Detect B output. 001 JESD204B LMFC output.

110 Pin functionality determined by 0x0041[7:4]

111 Disabled. Configured as inpu t with weak pull-down (default). [2:0] Chip FD_A/GPIO_A0 pin functionality Fast Detect A/GPIO A0 pin functionality. 0x7 R/W 000 Fast Detect A output. 001 JESD204B LMFC output.

110 Pin functionality determined by Register 0x0041, Bits[3:0]

111 Disabled. Configured as an input with weak pull-down (default). 0x0041 Chip Pin Control 2 [7:4] Chip FD_B/GPIO_B0 pin secondary functionality Fast Detect B/GPIO B0 pin secondary functionality (only used when Register 0x0040, Bits[5:3] = 110). 0x0 R/W 0000 Chip GPIO B0 input (NCO channel selection). 0001 Chip transfer input. 1000 Master next trigger output (MNTO). 1001 Slave next trigger input (SNTI). [3:0] Chip FD_A/GPIO_A0 pin secondary functionality Fast Detect A/GPIO B0 pin secondary functionality (only used when Register 0x0040, Bits[2:0] = 110). 0x0 R/W 0000 Chip GPIO A0 input (NCO channel selection). 0001 Chip transfer input. 1000 Master next trigger output (MNTO). 1001 Slave next trigger input (SNTI).

Rev. 0 | Page 95 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0042 Chip Pin Control 3 [7:4] Chip GPIO_B1 pin functionality GPIO B1 pin functionality. 0xF R/W 0000 Chip GPIO B1 input (NCO channel selection). 1000 Master next trigger output (MNTO). 1001 Slave next trigger input (SNTI). 1111 Disabled (configured as input with weak pull-down). [3:0] Chip GPIO_B1 pin functionality GPIO A1 pin functionality. 0xF R/W 0000 Chip GPIO A1 input (NCO channel selection). 1000 Master next trigger output (MNTO). 1001 Slave next trigger input (SNTI). 1111 Disabled (configured as input with weak pull-down). 0x0108 Clock divider control [7:3] Reserved Reserved. 0x0 R [2:0] Input clock divider (CLK± pins) 0x0 R/W 00 Divide by 1. 01 Divide by 2. 11 Divide by 4. 0x0109 Clock divider phase (local) [7:4] Reserved Reserved. 0x0 R [3:0] Clock divider phase offset 0x0 R/W 0000 0 input clock cycles delayed. 0001 ½ input clock cycles delayed (invert clock). 0010 1 input clock cycles delayed. … … 1110 7 input clock cycles delayed. 1111 7½ input clock cycles delayed. 0x010A Clock divider and SYSREF control

7 Clock divider auto phase

Clock divider autophase adjust enable. When enabled, Register 0x0129, Bits[3:0] contain the phase of the divider when SYSREF occurred. The actual divider phase offset = Register 0x0129, Bits[3:0] + Register 0x0109, Bits[3:0]. 0x0 R/W 0 Clock divider phase is not changed by SYSREF (disabled). 1 Clock divider phase is automatical ly adjusted by SYSREF (enabled). [6:4] Reserved Reserved. 0x0 R [3:2] Clock divider negative skew window Clock divider negative skew window (measured in ½ input device clocks). Number of ½ clock cycles before the input device clock by which captured SYSREF transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. This allows some uncertainty in the sampling of SYSREF without disturbing the input clock divider. Also, SYSREF must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. 0x0 R/W 0 No negative skew; SYSREF must be captured accurately. 1 ½ device clock of negative skew. 10 1 device clocks of negative skew. 11 1½ device clocks of negative skew. [1:0] Clock divider positive skew window Clock divider positive skew window (measured in ½ input device clocks). Number of clock cycles after the input device clock by which captured SYSREF transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. This allows some uncertainty in the sampling of SYSREF without disturbing the input clock divider. Also, SYSREF must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. 0x0 R/W 0 No positive skew; SYSREF must be captured accurately. 1 ½ device clock of positive skew. 10 1 device clocks of positive skew. 11 1½ device clocks of positive skew.

Rev. 0 | Page 96 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x010B Clock divider SYSREF status [7:4] Reserved Reserved. 0x0 R [3:0] Clock divider SYSREF offset Clock divider phase status (measured in ½ clock cycles). Internal clock divider phase of the captured SYSREF signal applied to the phase offset. Only used when 0x010A[7] = 1. When Register 0x010A, Bit 7 = 1, Register 0x010A, Bits[3:2] = 0, and Register 0x010A, Bits[1:0] = 0, the clock divider SYSREF offset = Register 0x0129, Bits[3:0]. 0x0 R 0x0110 Clock delay control [7:3] Reserved Reserved. 0x0 R [2:0] Clock delay mode select Clock de lay mode select. Used in conjunction with Register 0x0111 and Register 0x0112. 0x0 R/W 000 No clock delay. 010 Fine delay: only 0 to 16 delay steps are valid. 011 Fine delay (lowest jitter): only 0 to 16 delay steps are valid. 100 Fine delay: all 192 delay steps are valid.

110 Fine delay enabled (all 192 delay steps are valid); superfine

delay enabled (all 128 delay steps are valid). 0x0111 Clock superfine delay (local) [7:0] Clock superfine delay adjust Clock superfine delay adjust. This is an unsigned control to adjust the superfine sample clock delay in 0.25 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 010 or 110. 0x0 R/W 0x00 0 delay steps. … … 0x08 8 delay steps. … … 0x80 128 delay steps. 0x0112 Clock fine delay (local) [7:0] Set clock fine delay Clock fine delay adju st. This is an unsigned control to adjust the fine sample clock skew in 1.725 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6. Minimum = 0. Maximum = 192. Increment = 1. Unit = delay steps. 0xC0 R/W 0x00 0 delay steps. … … 0x08 8 delay steps. … … 0xC0 192 delay steps. 0x011B Clock status [7:1] Reserved Reserved. 0x0 R 0 Input clock detect Clock detection status. 0x0 R 0 Input clock not detected. 1 Input clock detected/locked. 0x011C Clock Duty Cycle Stabilizer 1 control (local) [7:2] Reserved Reserved 0x0 R/W 1 DCS1 enable Clock DCS1 enable. 0x1 R/W 0 DCS1 bypassed. 1 DCS1 enabled. 0 DCS1 power up Clock DCS1 power-up. 0x1 R/W 0 DCS1 powered down. 1 DCS1 powered up. 0x011E Clock Duty Cycle Stabilizer 2 control [7:2] Reserved Reserved. 0x0 R/W 1 DCS2 enable Clock DCS2 enable. 0x1 R/W 0 DCS2 bypassed. 1 DCS2 enabled. 0 DCS2 power up Clock DCS2 power-up. 0x1 R/W 0 DCS2 powered down. 1 DCS2 powered up.

Rev. 0 | Page 97 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0120 SYSREF Control 1 7 Reserved Reserved. 0x0 R

6 SYSREF± flag reset 0x0 R/W

0 Normal flag operation. 1 SYSREF flags held in reset (setup and hold error flags cleared). 5 Reserved Reserved. 0x0 R

4 SYSREF± transition select 0x0 R/W

0 SYSREF is valid on low to high transitions using the selected

CLK± edge. When changing this setting, SYSREF± mode select must be set to disabled.

1 SYSREF is valid on high to low transitions using the selected

CLK± edge. When changing this setting, SYSREF± mode select must be set to disabled.

3 CLK± edge select 0x0 R/W

0 Captured on the rising edge of CLK± input. 1 Captured on the falling edge of CLK± input. [2:1] SYSREF± mode select 0x0 R/W 0 Disabled. 1 Continuous. 10 N-shot. 0 Reserved Reserved. 0x0 R 0x0121 SYSREF Control 2 [7:4] Reserved Reserved. 0x0 R [3:0] SYSREF N-shot ignore counter select 0x0 R/W 0000 Next SYSREF only (do not ignore). 0001 Ignore the first SYSREF± transition. 0010 Ignore the first two SYSREF± transitions. 0011 Ignore the first three SYSREF± transitions. … … 1110 Ignore the first 14 SYSREF± transitions. 1111 Ignore the first 15 SYSREF± transitions. 0x0122 SYSREF Control 3 [7:4] Reserved Reserved. 0x0 R [3:2] SYSREF window negative Negative skew window (measured in sample clocks). Number of clock cycles before the sample clock by which captured SYSREF transitions are ignored. 0x0 R/W 00 No negative skew; SYSREF must be captured accurately. 01 One sample clock of negative skew. 10 Two sample clocks of negative skew. 11 Three sample clocks of negative skew. [1:0] SYSREF window positive Positive skew window (measured in sample clocks). Number of clock cycles before the sample clock by which captured SYSREF transitions are ignored. 0x0 R/W 00 No positive skew; SYSREF must be captured accurately. 01 One sample clock of positive skew. 10 Two sample clocks of positive skew. 11 Three sample clocks of positive skew. 0x0123 SYSREF Control 4 7 Reserved Reserved. 0x0 R [6:0] SYSREF± timestamp delay, Bits[6:0] SYSREF timestamp delay (in converte r sample clock cycles). 0x00 R/W 0 0 sample clock cycle delay. 1 1 sample clock cycle delay. … … 111 1111 127 sample clock cycle delay. 0x0128 SYSREF Status 1 [7:4] SYSREF± ho ld status SYSREF hold status. 0x0 R [3:0] SYSREF± setup status SYSREF setup status. 0x0 R

Rev. 0 | Page 98 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0129 SYSREF Status 2 [7:4] Reserved Reserved. 0x0 R [3:0] Clock divider phase when SYSREF± was captured SYSREF divider phase. Represents the phase of the divider when SYSREF was captured. 0x0 R 0000 In phase. 0001 SYSREF± is ½ cycl e delayed from clock. 0010 SYSREF± is 1 cycl e delayed from clock. 0011 SYSREF± is 1½ input clock cycles delayed. 0100 SYSREF± is 2 input clock cycles delayed. … … 1111 SYSREF± is 7½ input clock cycles delayed. 0x012A SYSREF Status 3 [7:0] SYSREF counter, Bits[7:0] increments when a SYSREF± is captured SYSREF count. Running counter that increments whenever a SYSREF event is captured. Reset by Register 0x120, Bit 6. Wraps around at 255. Read these bits only when Register 0x120, Bits[2:1] are set to disabled. 0x0 R 0x01FF Chip sync mode [7:1] Reserved Reserved. 0x0 R

0 Synchronization mode 0x0 R/W

0 JESD204B synchronization m ode. The SYSREF signal resets all internal clock dividers. Use this mode when synchronizing multiple chips as specified in the JESD204B standard. If the phase of any of the dividers must change, the JESD204B link goes down. 1 Timestamp mode. The SYSREF signal does not reset internal clock dividers. In this mode, the JESD204B link and the signal monitor are not affected by the SYSREF signal. The SYSREF signal timestamps a sample as it passes through the ADC and is used as a control bit in the JESD204B output word. Chip Operating Mode Control Registers 0x0200 Chip mode [7:6] Reserved Reserved. 0x0 R/W 5 Chip Q ignore Chip real (I) only selection. 0x0 R/W 0 Both real (I) and complex (Q) selected. 1 Only real (I) selected; complex (Q) is ignored. 4 Reserved Reserved. 0x0 R [3:0] Chip application mode 0x0 R/W 0000 Full bandwidth mode (default).

0001 One DDC mode (DDC0 only)

0010 Two DDC mode (DDC0 and DDC1 only)

0011 Four DDC mode (DDC0, DDC1, DDC2, and DDC3)

[7:4] Reserved Reserved. 0x0 R [3:0] Chip decimation ratio Chip decimation ratio. 0x0 R/W 0000 Full sample rate (decimate by 1, DDCs are bypassed). 0001 Decimate by 2. 1000 Decimate by 3. 0010 Decimate by 4. 0101 Decimate by 5. 1001 Decimate by 6. 0011 Decimate by 8. 0110 Decimate by 10. 1010 Decimate by 12. 0111 Decimate by 15. 0100 Decimate by 16. 1101 Decimate by 20. 1011 Decimate by 24. 1110 Decimate by 30. 1111 Decimate by 40. 1100 Decimate by 48.

Rev. 0 | Page 99 of 136 Addr. Name Bits Bit Name Settings Description Reset Access Fast Detect and Signal Monitor Control Registers 0x0245 Fast detect control (local) [7:4] Reserved Reserved. 0x0 R

3 Force FD_A/FD_B pins 0x0 R/W

0 Normal operation of the fast detect pin. 1 Force a value on the fast detect pin (see Bit 2).

2 Force value of

FD_A/FD_B pins The fast detect output pin for th is channel is set to this value when the output is forced. 0x0 R/W 1 Reserved Reserved. 0x0 R

0 Enable fast detect output 0x0 R/W

0 Fast detect disabled. 1 Fast detect enabled. 0x0247 Fast detect up LSB (local) [7:0] Fast detect upper threshold LSBs of the fast detect upper th reshold. This register contains the 8 LSBs of the programmable 13-bit upper threshold that is compared to the fine ADC magnitude. 0x0 R/W 0x0248 Fast detect up MSB (local) [7:5] Reserved Reserved. 0x0 R [4:0] Fast detect upper threshold MSBs of the fast detect upper th reshold. This register contains the 8 LSBS of the programmable 13-bit upper threshold that is compared to the fine ADC magnitude. 0x0 R/W 0x0249 Fast detect low LSB (local) [7:0] Fast detect lower threshold LSBs of the fast detect lower th reshold. This register contains the 8 LSBS of the programmable 13-bit lower threshold that is compared to the fine ADC magnitude. 0x0 R/W 0x024A Fast detect low MSB (local) [7:5] Reserved Reserved. 0x0 R [4:0] Fast detect lower threshold MSBs of the fast detect lower th reshold. This register contains the 8 LSBs of the programmable 13-bit lower threshold that is compared to the fine ADC magnitude 0x0 R/W 0x024B Fast detect dwell LSB (local) [7:0] Fast detect dwell time LSBs of the fast detect dwell time counter target. This is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FD_x pins are reset to 0. 0x0 R/W 0x024C Fast detect dwell MSB (local) [7:0] Fast detect dwell time MSBs of the fast detect dwell time counter target. This is a load value for a 16-bit counter that determines how long the ADC data must remain below the lower threshold before the FD_x pins are reset to 0. 0x0 R/W 0x026F Signal monitor sync control [7:2] Reserved Reserved. 0x0 R

1 Signal monitor next

Signal monitor next synchronization mode. 0x0 R/W 0 Continuous mode. 1 Next synchronization mode. Only the next valid edge of the SYSREF± pin is used to synchronize the signal monitor block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF is found, Register 0x026F, Bit 0 clears. The SYSREF± pin must be an integer multiple of the signal monitor period for this function to operate correctly in continuous mode.

0 Signal monitor

Signal monitor synchronization enable 0x0 R/W 0 Synchronization disabled.

1 If Register 0x026F, Bit 1 = 1, only the next valid edge of the

SYSREF± pin is used to synchronize the signal monitor block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF signal is received, this bit is cleared. The SYSREF± input pin must be enabled to synchronize the signal monitor blocks. 0x0270 Signal monitor control (local) [7:2] Reserved Reserved. 0x0 R

1 Peak detector 0x0 R/W

0 Peak detector disabled. 1 Peak detector enabled. 0 Reserved Reserved. 0x0 R 0x0271 Signal Monitor Period 0 (local) [7:0] Signal monitor period [7:0] Bits[7:0] of the 24-bit value that sets the number of output clock cycles over which the signal monitor performs its operation. Only even values are supported. 0x80 R/W

Rev. 0 | Page 100 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0272 Signal Monitor Period 1 (local) [7:0] Signal monitor period [15:8] Bits[15:8] of the 24-bit value that sets the number of output clock cycles over which the signal monitor performs its operation. Only even values are supported. 0x0 R/W 0x0273 Signal Monitor Period 2 (local) [7:0] Signal monitor period [23:16] Bits[23:16] of the 24-bit value th at sets the number of output clock cycles over which the signal monitor performs its operation. Only even values are supported. 0x0 R/W 0x0274 Signal monitor status control (local) [7:5] Reserved Reserved. 0x0 R

4 Result update 0x0 R/WC

1 Update signal monitor stat us registers, Register 0x0275 to

Register 0x0278. Self clearing. 3 Reserved Reserved. 0x0 R [2:0] Result selection 0x1 R/W 001 Peak detector placed on status readback signals. 0x0275 Signal Monitor Status 0 (local) [7:0] Signal monitor result [7:0] Signal monitor status result. This 20-bit value contains the status result calculated by the signal monitor block. 0x0 R 0x0276 Signal Monitor Status 1 (local) [7:0] Signal monitor result [15:8] Signal monitor status result. 0x0 R 0x0277 Signal Monitor Status 2 (local) [7:4] Reserved Reserved. 0x0 R [3:0] Signal monitor result [19:16] Signal monitor status result. 0x0 R 0x0278 Signal monitor status frame counter (local) [7:0] Period count result, Bits[7:0] Signal monitor frame counter status bits. Frame counter increments whenever the period counter expires. 0x0 R 0x0279 Signal monitor serial framer control (local) [7:2] Reserved Reserved. 0x0 R [1:0] Signal monitor SPORT over JESD204B enable 0x0 R/W 00 Disabled. 11 Enabled. 0x027A SPORT over JESD204B input selection (local) [7:6] Reserved Reserved. 0x0 R

1 SPORT over JESD204B

Signal monitor serial framer input selection. When each individual bit is a 1, the corresponding signal statistics information is sent within the frame. 0x1 R/W 0 Disabled. 1 Peak detector data inse rted in the serial frame. 0 Reserved Reserved. 0x0 R DDC Function Registers (See the Digital Downconverter (DDC) Section) 0x0300 DDC SYNC control 7 DDC FTW/POW/MAW/ MBW update mode Select DDC FTW/POW/MAW/MBW update mode. 0x0 R/W 0 Instantaneous/continuous update. FTW/POW/MAW/MBW values are updated immediately.

1 FTW/POW/MAW/MBW values are updated synchronously when

the chip transfer bit (Register 0x000F, Bit 0) is set. [6:5] Reserved Reserved. 0x0 R

4 DDC NCO soft reset This bit can be used to synchronize all the NCOs inside the DDC

blocks. 0x0 R/W 0 Normal operation. 1 DDC held in reset. [3:2] Reserved Reserved. 0x0 R

Rev. 0 | Page 101 of 136 Addr. Name Bits Bit Name Settings Description Reset Access

1 DDC next

0 Continuous mode. The SYSR EF frequency must be an integer multiple of the NCO frequency for this function to operate correctly in continuous mode.

1 Only the next valid edge of the SYSREF± pin is used to

synchronize the NCO in the DDC block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF signal is found, the DDC synchronization enable bit (Register 0x0300, Bit 0) is cleared.

0 DDC synchronization

The SYSREF input pin must be enabled to synchronize the DDCs. 0x0 R/W 0 Synchronization disabled.

1 If DDC next synchronizatio n (Register 0x0300, Bit 1 = 1), only

the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. Subsequent edges of the SYSREF± pin are ignored. When the next SYSREF signal is received, this bit is cleared. 0x0310 DDC0 control 7 DDC0 mixer select 0x0 R/W 0 Real mixer (I and Q inputs mu st be from the same real channel).

1 Complex mixer (I and Q must be from separate, real and imaginary

quadrature ADC receive channels; analog demodulator).

6 DDC0 gain select Gain can be used to compensate for the 6 dB loss associated

with mixing an input signal down to baseband and filtering out its negative component. 0x0 R/W 0 0 dB gain. 1 6 dB gain (multiply by 2). [5:4] DDC0 intermediate frequency (IF) mode 0x0 R/W 00 Variable IF mode. 01 0 Hz IF mode. 10 f S Hz IF mode. 11 Test mode.

3 DDC0 complex to real

0 Complex (I and Q) outputs contain valid data. 1 Real (I) output only. comp lex to real enabled. Uses extra fS mixing to convert to real. [2:0] DDC0 decimation rate select Decimation filter selection. 0x0 R/W

000 HB1 + HB2 filter selection: decimate by 2 (complex to real

enabled), or decimate by 4 (complex to real disabled).

001 HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to

real enabled), or decimate by 8 (complex to real disabled).

010 HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8

(complex to real enabled), or decimate by 16 (complex to real disabled).

011 HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

100 HB1 + TB2 filter selection: decimate by 3 (complex to real

enabled), or decimate by 6 (complex to real disabled).

101 HB1 + HB2 + TB2 filter select ion: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

110 HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to

real enabled), or decimate by 24 (complex to real disabled). 111 Decimation determined by Register 0x0311, Bits[7:4].

Rev. 0 | Page 102 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0311 DDC0 input select [7:4] DDC0 decimation rate select Only valid when Register 0x0310, Bits[2:0] = 3'b111. 0x0 R/W

0 TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real enabled).

10 FB2 + HB1 filter selection: decimate by 10 (complex to real

disabled), or decimate by 5 (complex to real enabled).

11 FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to

real disabled), or decimate by 10 (complex to real enabled).

100 FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to

real disabled), or decimate by 20 (complex to real enabled). 111 TB1 filter selection: decimate by 3 (decimate by 1.5 not supported). 1000 FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not supported).

1001 HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by

15 not supported). 3 Reserved Reserved. 0x0 R

2 DDC0 Q input select 0x0 R/W

0 Channel A. 1 Channel B. 1 Reserved Reserved. 0x0 R

0 DDC0 I input select 0x0 R/W

0 Channel A. 1 Channel B. 0x0314 DDC0 NCO control [7:4] DDC0 NCO channel select mode For edge control, the internal counter wraps after the Register 0x0314, Bits[3:0] value is reached. 0x0 R/W 0 Use Register 0x0314, Bits[3:0]. 1 2'b0, GPIO_B0, GPIO_A0. 10 2'b0, GPIO_B1, GPIO_A1. 11 2'b00, GPIO_A1, GPIO_A0. 100 2'b00, GPIO_B1, GPIO_B0. 101 GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0. 110 GPIO_B1, GPIO_B 0, GPIO_A1, GPIO_A0. 1000 Increment internal counter on rising edge of the GPIO_A0 pin. 1001 Increment internal counter on rising edge of the GPIO_A1 pin. 1010 Increment internal counter on rising edge of the GPIO_B0 pin. 1011 Increment internal counter on rising edge of the GPIO_B1 pin. [3:0] DDC0 NCO register map channel select NCO channel select register map control. 0x0 R/W 0 Select NCO Channel 0. 1 Select NCO Channel 1. 10 Select NCO Channel 2. 11 Select NCO Channel 3. 100 Select NCO Channel 4. 101 Select NCO Channel 5. 110 Select NCO Channel 6. 111 Select NCO Channel 7. 1000 Select NCO Channel 8. 1001 Select NCO Channel 9. 1010 Select NCO Channel 10. 1011 Select NCO Channel 11. 1100 Select NCO Channel 12. 1101 Select NCO Channel 13. 1110 Select NCO Channel 14. 1111 Select NCO Channel 15.

Rev. 0 | Page 103 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0315 DDC0 phase control [7:4] Reserved Reserved. 0x0 R [3:0] DDC0 phase update index Indexes the NCO channel whose phase and offset is updated. The update method is based on the DDC phase update mode, which can be continuous or require chip transfer. 0x0 R/W 0000 Update NCO Channel 0. 0001 Update NCO Channel 1. 0010 Update NCO Channel 2. 0011 Update NCO Channel 3. 0x0316 DDC0 Phase Increment 0 [7:0] DDC0 phase increment [7:0] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0317 DDC0 Phase Increment 1 [7:0] DDC0 phase increment [15:8] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0318 DDC0 Phase Increment 2 [7:0] DDC0 phase increment [23:16] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0319 DDC0 Phase Increment 3 [7:0] DDC0 phase increment [31:24] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x031A DDC0 Phase Increment 4 [7:0] DDC0 phase increment [39:32] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x031B DDC0 Phase Increment 5 [7:0] DDC0 phase increment [47:40] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x031D DDC0 Phase Offset 0 [7:0] DDC0 phase offset [7:0] Tw os complement phase offset value for the NCO. 0x0 R/W 0x031E DDC0 Phase Offset 1 [7:0] DDC0 phase offset [15:8] Twos complement phase offset value for the NCO. 0x0 R/W 0x031F DDC0 Phase Offset 2 [7:0] DDC0 phase offset [23:16] Twos complement phase offset value for the NCO. 0x0 R/W 0x0320 DDC0 Phase Offset 3 [7:0] DDC0 phase offset [31:24] Tw os complement phase offset value for the NCO. 0x0 R/W 0x0321 DDC0 Phase Offset 4 [7:0] DDC0 phase offset [39:32] Tw os complement phase offset value for the NCO. 0x0 R/W 0x0322 DDC0 Phase Offset 5 [7:0] DDC0 phase offset [47:40] Tw os complement phase offset value for the NCO. 0x0 R/W 0x0327 DDC0 test enable [7:3] Reserved Reserved. 0x0 R

2 DDC0 Q output test

Q samples always use the Test Mode B block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. 0x0 R/W 0 Test mode disabled. 1 Test mode enabled. 1 Reserved Reserved. 0x0 R

0 DDC0 I output test mode

I samples always use the Test Mode A block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. 0x0 R/W 0 Test mode disabled. 1 Test mode enabled. 0x0330 DDC1 control 7 DDC1 mixer select 0x0 R/W 0 Real mixer (I and Q inputs mu st be from the same real channel). quadrature ADC receive channels; analog demodulator).

6 DDC1 gain select Gain can be used to compensates for the 6 dB loss associated

with mixing an input signal down to baseband and filtering out its negative component. 0x0 R/W 0 0 dB gain. 1 6 dB gain (multiply by 2). [5:4] DDC1 intermediate frequency (IF) mode 0x0 R/W 00 Variable IF mode. 01 0 Hz IF mode. 10 f S Hz IF mode. 11 Test mode.

3 DDC1 complex to real

0 Complex (I and Q) outputs contain valid data. 1 Real (I) output only. Comp lex to real enabled. Uses extra fS mixing to convert to real.

Rev. 0 | Page 104 of 136 Addr. Name Bits Bit Name Settings Description Reset Access [2:0] DDC1 decimation rate select Decimation filter selection. 0x0 R/W enabled), or decimate by 4 (complex to real disabled). real enabled), or decimate by 8 (complex to real disabled). (complex to real enabled), or decimate by 16 (complex to real disabled). decimate by 2 (complex to real disabled). enabled), or decimate by 6 (complex to real disabled). enabled), or decimate by 12 (complex to real disabled).

110 HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex

to real enabled), or decimate by 24 (complex to real disabled). 111 Decimation determined by Register 0x0331, Bits[7:4]. 0x0331 DDC1 input select [7:4] DDC1 decimation rate select Only valid when Register 0x0310, Bits[2:0] = 3'b111. 0x0 R/W (complex to real disabled), or decimate by 24 (complex to real enabled). disabled), or decimate by 5 (complex to real enabled). real disabled), or decimate by 10 (complex to real enabled).

100 FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex

to real disabled), or decimate by 20 (complex to real enabled). 111 TB1 filter selection: decimate by 3 (decimate by 1.5 not supported). 1000 FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not supported). 15 not supported). 3 Reserved Reserved. 0x0 R

2 DDC1 Q input select 0x1 R/W

0 Channel A. 1 Channel B. 1 Reserved Reserved. 0x0 R

0 DDC1 I input select 0x1 R/W

0 Channel A. 1 Channel B. 0x0334 DDC1 NCO control [7:4] DDC1 NCO channel select mode For edge control, the internal counter wraps when the Register 0x0334, Bits[3:0] value is reached. 0x0 R/W

0 Use Register 0x0314, Bits[3:0]

1 2'b0, GPIO_B0, GPIO_A0. 10 2'b0, GPIO_B1, GPIO_A1. 11 2'b00, GPIO_A1, GPIO_A0. 100 2'b00, GPIO_B1, GPIO_B0. 101 GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0. 110 GPIO_B1, GPIO_B 0, GPIO_A1, GPIO_A0. 1000 Increment internal counter when rising edge of the GPIO_A0 pin. 1001 Increment internal counter when rising edge of the GPIO_A1 pin. 1010 Increment internal counter when rising edge of the GPIO_B0 pin. 1011 Increment internal counter when rising edge of the GPIO_B1 pin.

Rev. 0 | Page 105 of 136 Addr. Name Bits Bit Name Settings Description Reset Access [3:0] DDC1 NCO register map channel select NCO channel select register map control 0x0 R/W 0 Select NCO Channel 0. 1 Select NCO Channel 1. 10 Select NCO Channel 2. 11 Select NCO Channel 3. 100 Select NCO Channel 4. 101 Select NCO Channel 5. 110 Select NCO Channel 6. 111 Select NCO Channel 7. 1000 Select NCO Channel 8. 1001 Select NCO Channel 9. 1010 Select NCO Channel 10. 1011 Select NCO Channel 11. 1100 Select NCO Channel 12. 1101 Select NCO Channel 13. 1110 Select NCO Channel 14. 1111 Select NCO Channel 15. 0x0335 DDC1 phase control [7:4] Reserved Reserved. 0x0 R [3:0] DDC1 phase update index Indexes the NCO channel for which the phase and offset is to be updated. The update method is based on the DDC phase update mode, which can be continuous or require chip transfer. 0x0 R/W 0000 Update NCO Channel 0. 0001 Update NCO Channel 1. 0010 Update NCO Channel 2. 0011 Update NCO Channel 3. 0x0336 DDC1 Phase Increment 0 [7:0] DDC1 phase increment [7:0] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0337 DDC1 Phase Increment 1 [7:0] DDC1 phase increment [15:8] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0338 DDC1 Phase Increment 2 [7:0] DDC1 phase increment [23:16] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0339 DDC1 Phase Increment 3 [7:0] DDC1 phase increment [31:24] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x033A DDC1 Phase Increment 4 [7:0] DDC1 phase increment [39:32] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x033B DDC1 Phase Increment 5 [7:0] DDC1 phase increment [47:40] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x033D DDC1 Phase Offset 0 [7:0] DDC1 phase offset [7:0] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x033E DDC1 Phase Offset 1 [7:0] DDC1 phase offset [15:8] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x033F DDC1 Phase Offset 2 [7:0] DDC1 phase offset [23:16] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0340 DDC1 Phase Offset 3 [7:0] DDC1 phase offset [31:24] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0341 DDC1 Phase Offset 4 [7:0] DDC1 phase offset [39:32] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0342 DDC1 Phase Offset 5 [7:0] DDC1 phase offset [47:40] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0347 DDC1 test enable [7:3] Reserved Reserved. 0x0 R

2 DDC1 Q output test

Q samples always use the Test Mode B block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. 0x0 R/W 0 Test mode disabled. 1 Test mode enabled. 1 Reserved Reserved. 0x0 R

0 DDC1 I output test mode

I samples always use the Test Mode A block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. 0x0 R/W 0 Test mode disabled. 1 Test mode enabled.

Rev. 0 | Page 106 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0350 DDC2 control 7 DDC2 mixer select 0x0 R/W

0 Real mixer (I and Q inputs must be from the same real channel)

quadrature ADC receive channels; analog demodulator)

6 DDC2 gain select Gain can be used to compensates for the 6 dB loss associated

with mixing an input signal down to baseband and filtering out its negative component. 0x0 R/W 0 0 dB gain. 1 6 dB gain (multiply by 2). [5:4] DDC2 intermediate frequency (IF) mode 0x0 R/W 00 Variable IF mode. 01 0 Hz IF mode. 10 f S Hz IF mode. 11 Test mode.

3 DDC2 complex to real

0 Complex (I and Q) outputs contain valid data. 1 Real (I) output only. Comp lex to real enabled. Uses extra fS mixing to convert to real. [2:0] DDC2 decimation rate select Decimation filter selection. 0x0 R/W enabled), or decimate by 4 (complex to real disabled). real enabled), or decimate by 8 (complex to real disabled). (complex to real enabled), or decimate by 16 (complex to real disabled). decimate by 2 (complex to real disabled). enabled), or decimate by 6 (complex to real disabled). enabled), or decimate by 12 (complex to real disabled). real enabled), or decimate by 24 (complex to real disabled). 111 Decimation determined by Register 0x0351, Bits[7:4]. 0x0351 DDC2 input select [7:4] DDC2 decimation rate select Only valid when Register 0x0310, Bits[2:0] = 3'b111. 0x0 R/W (complex to real disabled), or decimate by 24 (complex to real enabled). disabled), or decimate by 5 (complex to real enabled). real disabled), or decimate by 10 (complex to real enabled). real disabled), or decimate by 20 (complex to real enabled). 3 Reserved Reserved. 0x0 R

2 DDC2 Q input select 0x0 R/W

0 Channel A. 1 Channel B. 1 Reserved Reserved. 0x0 R

0 DDC2 I input select 0x0 R/W

0 Channel A. 1 Channel B.

Rev. 0 | Page 107 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0354 DDC2 NCO control [7:4] DDC2 NCO channel select mode For edge control, the internal counter wraps when the Register 0x0354, Bits[3:0] value is reached. 0x0 R/W

0 Use 0x0314[3:0]

1 2'b0, GPIO B0, GPIO A0. 10 2'b0, GPIO B1, GPIO A1. 11 2'b00, GPIO A1, GPIO A0. 100 2'b00, GPIO B1, GPIO B0. 101 GPIO B1, GPIO A1, GPIO B0, GPIO A0. 110 GPIO B1, GPIO B0, GPIO A1, GPIO A0. 1000 Increment internal counter when rising edge of the GPIO_A0 pin. 1001 Increment internal counter when rising edge of the GPIO_A1 pin. 1010 Increment internal counter when rising edge of the GPIO_B0 pin. 1011 Increment internal counter when rising edge of the GPIO_B1 pin. [3:0] DDC2 NCO register map channel select NCO channel select register map control. 0x0 R/W 0 Select NCO Channel 0. 1 Select NCO Channel 1. 10 Select NCO Channel 2. 11 Select NCO Channel 3. 100 Select NCO Channel 4. 101 Select NCO Channel 5. 110 Select NCO Channel 6. 111 Select NCO Channel 7. 1000 Select NCO Channel 8. 1001 Select NCO Channel 9. 1010 Select NCO Channel 10. 1011 Select NCO Channel 11. 1100 Select NCO Channel 12. 1101 Select NCO Channel 13. 1110 Select NCO Channel 14. 1111 Select NCO Channel 15. 0x0355 DDC2 phase control [7:4] Reserved Reserved. 0x0 R [3:0] DDC2 phase update index Indexes the NCO channel whose phase and offset gets updated. The update method is based on the DDC phase update mode, which can be continuous or require chip transfer. 0x0 R/W 0000 Update NCO Channel 0. 0001 Update NCO Channel 1. 0010 Update NCO Channel 2. 0011 Update NCO Channel 3. 0x0356 DDC2 Phase Increment 0 [7:0] DDC2 phase increment [7:0] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0357 DDC2 Phase Increment 1 [7:0] DDC2 phase increment [15:8] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0358 DDC2 Phase Increment 2 [7:0] DDC2 phase increment [23:16] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0359 DDC2 Phase Increment 3 [7:0] DDC2 phase increment [31:24] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x035A DDC2 Phase Increment 4 [7:0] DDC2 phase increment [39:32] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x035B DDC2 Phase Increment 5 [7:0] DDC2 phase increment [47:40] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x035D DDC2 Phase Offset 0 [7:0] DDC2 phase offset [7:0] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x035E DDC2 Phase Offset 1 [7:0] DDC2 phase offset [15:8] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x035F DDC2 Phase Offset 2 [7:0] DDC2 phase offset [23:16] Twos complement phase offset value for the NCO. 0x0 R/W 0x0360 DDC2 Phase Offset 3 [7:0] DDC2 phase offset [31:24] Twos complement phase offset value for the NCO. 0x0 R/W

Rev. 0 | Page 108 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0361 DDC2 Phase Offset 4 [7:0] DDC2 phase offset [39:32] Twos complement phase offset value for the NCO. 0x0 R/W 0x0362 DDC2 Phase Offset 5 [7:0] DDC2 phase offset [47:40] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0367 DDC2 test enable [7:3] Reserved Reserved. 0x0 R

2 DDC2 Q output test

Q samples always use the Test Mode B block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. 0x0 R/W 0 Test mode disabled. 1 Test mode enabled. 1 Reserved Reserved. 0x0 R

0 DDC2 I output test mode

I samples always use the Test Mode A block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. 0x0 R/W 0 Test mode disabled. 1 Test mode enabled. 0x0370 DDC3 control 7 DDC3 mixer select 0x0 R/W 0 Real mixer (I and Q inputs mu st be from the same real channel). quadrature ADC receive channels; analog demodulator).

6 DDC3 gain select Gain can be used to compensate for the 6 dB loss associated

with mixing an input signal down to baseband and filtering out its negative component. 0x0 R/W 0 0 dB gain. 1 6 dB gain (multiply by 2) [5:4] DDC3 intermediate frequency (IF) mode 0x0 R/W 00 Variable IF mode. 01 0 Hz IF mode. 10 f S Hz IF mode. 11 Test mode.

3 DDC3 complex to real

0 Complex (I and Q) outputs contain valid data. 1 Real (I) output only. comp lex to real enabled. Uses extra fS mixing to convert to real. [2:0] DDC3 decimation rate select Decimation filter selection. 0x0 R/W enabled), or decimate by 4 (complex to real disabled). real enabled), or decimate by 8 (complex to real disabled). (complex to real enabled), or decimate by 16 (complex to real disabled). decimate by 2 (complex to real disabled). enabled), or decimate by 6 (complex to real disabled). enabled), or decimate by 12 (complex to real disabled). real enabled), or decimate by 24 (complex to real disabled). 111 Decimation determined by Register 0x0371, Bits[7:4].

Rev. 0 | Page 109 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0371 DDC3 input select [7:4] DDC3 decimation rate select Only valid when Register 0x0310, Bits[2:0] = 3'b111. 0x0 R/W (complex to real disabled), or decimate by 24 (complex to real enabled). disabled), or decimate by 5 (complex to real enabled)

11 FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled) to real disabled), or decimate by 20 (complex to real enabled) 3 Reserved Reserved. 0x0 R

2 DDC3 Q input select 0x1 R/W

0 Channel A. 1 Channel B. 1 Reserved Reserved. 0x0 R

0 DDC3 I input select 0x1 R/W

0 Channel A. 1 Channel B. 0x0374 DDC3 NCO control [7:4] DDC3 NCO channel select mode For edge control, the internal counter wraps when the Register 0x0374, Bits[3:0] value is reached. 0x0 R/W 0 Use Register 0x0314, Bits[3:0]. 1 2'b0, GPIO B0, GPIO A0. 10 2'b0, GPIO B1, GPIO A1. 11 2'b00, GPIO A1, GPIO A0. 100 2'b00, GPIO B1, GPIO B0. 101 GPIO B1, GPIO A1, GPIO B0, GPIO A0. 110 GPIO B1, GPIO B0, GPIO A1, GPIO A0. 1000 Increment internal counter when rising edge of GPIO_A0 pin. 1001 Increment internal counter when rising edge of GPIO_A1 pin. 1010 Increment internal counter when rising edge of GPIO_B0 pin. 1011 Increment internal counter when rising edge of GPIO_B1 pin. [3:0] DDC3 NCO register map channel select NCO channel select register map control. 0x0 R/W 0 Select NCO Channel 0. 1 Select NCO Channel 1. 10 Select NCO Channel 2. 11 Select NCO Channel 3. 100 Select NCO Channel 4. 101 Select NCO Channel 5. 110 Select NCO Channel 6. 111 Select NCO Channel 7. 1000 Select NCO Channel 8. 1001 Select NCO Channel 9. 1010 Select NCO Channel 10. 1011 Select NCO Channel 11. 1100 Select NCO Channel 12. 1101 Select NCO Channel 13. 1110 Select NCO Channel 14. 1111 Select NCO Channel 15. 0x0375 DDC3 phase control [7:4] Reserved Reserved. 0x0 R [3:0] DDC3 phase update index Indexes the NCO channel whose phase and offset gets updated. The update method is based on the DDC phase update mode, which can be continuous or require chip transfer. 0x0 R/W 0000 Update NCO Channel 0. 0001 Update NCO Channel 1. 0010 Update NCO Channel 2. 0011 Update NCO Channel 3.

Rev. 0 | Page 110 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0376 DDC3 Phase Increment 0 [7:0] DDC3 phase increment [7:0] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0377 DDC3 Phase Increment 1 [7:0] DDC3 phase increment [15:8] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248 0x0 R/W 0x0378 DDC3 Phase Increment 2 [7:0] DDC3 phase increment [23:16] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x0379 DDC3 Phase Increment 3 [7:0] DDC3 phase increment [31:24] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x037A DDC3 Phase Increment 4 [7:0] DDC3 phase increment [39:32] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x037B DDC3 Phase Increment 5 [7:0] DDC3 phase increment [47:40] FTW. Twos complement phase increment value for the NCO. Complex mixing frequency = (DDC phase increment × fS)/248. 0x0 R/W 0x037D DDC3 Phase Offset 0 [7:0] DDC3 phase offset [7:0] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x037E DDC3 Phase Offset 1 [7:0] DDC3 phase offset [15:8] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x037F DDC3 Phase Offset 2 [7:0] DDC3 phase offset [23:16] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0380 DDC3 Phase Offset 3 [7:0] DDC3 phase offset [31:24] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0381 DDC3 Phase Offset 4 [7:0] DDC3 phase offset [39:32] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0382 DDC3 Phase Offset 5 [7:0] DDC3 phase offset [47:40] Twos compleme nt phase offset value for the NCO. 0x0 R/W 0x0387 DDC3 test enable [7:3] Reserved Reserved. 0x0 R

2 DDC3 Q output test

Q samples always use the Test Mode B block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. 0x0 R/W 0 Test mode disabled. 1 Test mode enabled. 1 Reserved Reserved. 0x0 R

0 DDC3 I output test mode

I samples always use the Test Mode A block. The test mode is selected using the channel dependent Register 0x0550, Bits[3:0]. 0x0 R/W 0 Test mode disabled. 1 Test mode enabled. 0x0390 DDC0 Phase Increment Fractional A0 [7:0] DDC0 Phase Increment Fractional A [7:0] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x0391 DDC0 Phase Increment Fractional A1 [7:0] DDC0 Phase Increment Fractional A [15:8] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x0392 DDC0 Phase Increment Fractional A2 [7:0] DDC0 Phase Increment Fractional A [23:16] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x0393 DDC0 Phase Increment Fractional A3 [7:0] DDC0 Phase Increment Fractional A [31:24] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x0394 DDC0 Phase Increment Fractional A4 [7:0] DDC0 Phase Increment Fractional A [39:32] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x0395 DDC0 Phase Increment Fractional A5 [7:0] DDC0 Phase Increment Fractional A [47:40] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x0398 DDC0 Phase Increment Fractional B0 [7:0] DDC0 Phase Increment Fractional B [7:0] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x0399 DDC0 Phase Increment Fractional B1 [7:0] DDC0 Phase Increment Fractional B [15:8] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x039A DDC0 Phase Increment Fractional B2 [7:0] DDC0 Phase Increment Fractional B [23:16] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x039B DDC0 Phase Increment Fractional B3 [7:0] DDC0 Phase Increment Fractional B [31:24] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W

Rev. 0 | Page 111 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x039C DDC0 Phase Increment Fractional B4 [7:0] DDC0 Phase Increment Fractional B [39:32] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x039D DDC0 Phase Increment Fractional B5 [7:0] DDC0 Phase Increment Fractional B [47:40] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03A0 DDC1 Phase Increment Fractional A0 [7:0] DDC1 Phase Increment Fractional A [7:0] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03A1 DDC1 Phase Increment Fractional A1 [7:0] DDC1 Phase Increment Fractional A [15:8] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03A2 DDC1 Phase Increment Fractional A2 [7:0] DDC1 Phase Increment Fractional A [23:16] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03A3 DDC1 Phase Increment Fractional A3 [7:0] DDC1 Phase Increment Fractional A [31:24] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03A4 DDC1 Phase Increment Fractional A4 [7:0] DDC1 Phase Increment Fractional A [39:32] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03A5 DDC1 Phase Increment Fractional A5 [7:0] DDC1 Phase Increment Fractional A [47:40] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03A8 DDC1 Phase Increment Fractional B0 [7:0] DDC1 Phase Increment Fractional B [7:0] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03A9 DDC1 Phase Increment Fractional B1 [7:0] DDC1 Phase Increment Fractional B [15:8] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03AA DDC1 Phase Increment Fractional B2 [7:0] DDC1 Phase Increment Fractional B [23:16] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03AB DDC1 Phase Increment Fractional B3 [7:0] DDC1 Phase Increment Fractional B [31:24] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03AC DDC1 Phase Increment Fractional B4 [7:0] DDC1 Phase Increment Fractional B [39:32] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03AD DDC1 Phase Increment Fractional B5 [7:0] DDC1 Phase Increment Fractional B [47:40] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03B0 DDC2 Phase Increment Fractional A0 [7:0] DDC2 Phase Increment Fractional A [7:0] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03B1 DDC2 Phase Increment Fractional A1 [7:0] DDC2 Phase Increment Fractional A [15:8] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03B2 DDC2 Phase Increment Fractional A2 [7:0] DDC2 Phase Increment Fractional A [23:16] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03B3 DDC2 Phase Increment Fractional A3 [7:0] DDC2 Phase Increment Fractional A [31:24] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03B4 DDC2 Phase Increment Fractional A4 [7:0] DDC2 Phase Increment Fractional A [39:32] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03B5 DDC2 Phase Increment Fractional A5 [7:0] DDC2 Phase Increment Fractional A [47:40] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03B8 DDC2 Phase Increment Fractional B0 [7:0] DDC2 Phase Increment Fractional B [7:0] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03B9 DDC2 Phase Increment Fractional B1 [7:0] DDC2 Phase Increment Fractional B [15:8] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W

Rev. 0 | Page 112 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x03BA DDC2 Phase Increment Fractional B2 [7:0] DDC2 Phase Increment Fractional B [23:16] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03BB DDC2 Phase Increment Fractional B3 [7:0] DDC2 Phase Increment Fractional B [31:24] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03BC DDC2 Phase Increment Fractional B4 [7:0] DDC2 Phase Increment Fractional B [39:32] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03BD DDC2 Phase Increment Fractional B5 [7:0] DDC2 Phase Increment Fractional B [47:40] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03C0 DDC3 Phase Increment Fractional A0 [7:0] DDC3 Phase Increment Fractional A [7:0] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03C1 DDC3 Phase Increment Fractional A1 [7:0] DDC3 Phase Increment Fractional A [15:8] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03C2 DDC3 Phase Increment Fractional A2 [7:0] DDC3 Phase Increment Fractional A [23:16] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03C3 DDC3 Phase Increment Fractional A3 [7:0] DDC3 Phase Increment Fractional A [31:24] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03C4 DDC3 Phase Increment Fractional A4 [7:0] DDC3 Phase Increment Fractional A [39:32] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03C5 DDC3 Phase Increment Fractional A5 [7:0] DDC3 Phase Increment Fractional A [47:40] Numerator correction term for Mo dulus Phase Accumulator A. 0x0 R/W 0x03C8 DDC3 Phase Increment Fractional B0 [7:0] DDC3 Phase Increment Fractional B [7:0] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03C9 DDC3 Phase Increment Fractional B1 [7:0] DDC3 Phase Increment Fractional B [15:8] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03CA DDC3 Phase Increment Fractional B2 [7:0] DDC3 Phase Increment Fractional B [23:16] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03CB DDC3 Phase Increment Fractional B3 [7:0] DDC3 Phase Increment Fractional B [31:24] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03CC DDC3 Phase Increment Fractional B4 [7:0] DDC3 Phase Increment Fractional B [39:32] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W 0x03CD DDC3 Phase Increment Fractional B5 [7:0] DDC3 Phase Increment Fractional B [47:40] Denominator correction term for Mo dulus Phase Accumulator B. 0x0 R/W Digital Outputs and Test Modes Registers 0x0550 ADC test mode control (local) 7 User pattern selection Test mode user patte rn selection. This bit is only used when Register 0x0550, Bits[3:0] = 4’b1000 (user input mode). Otherwise, it is ignored. User Pattern 1 is found in the User Pattern 1 MSB register (Register 0x0552) and the User Pattern 1 LSB (Register 0x0551) registers. User Pattern 2 is found in the User Pattern 2 MSB register (Register 0x0554) and the User Patter 2 LSB (Register 0x0553) register, and so on. 0x0 R/W 0 Continuous/repeat pattern. Plac e each user pattern (1, 2, 3, and 4) on the output for 1 clock cycle and then repeat. (Output User Pattern 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, and so on.) 1 Single pattern. Place each user pattern (1, 2, 3, and 4) on the output for 1 clock cycle and then output all zeros. (Output User Pattern 1, 2, 3, 4, and then output all zeros) 6 Reserved Reserved. 0x0 R 5 Reset PN long generator Test mode long pseudorandom number test generator reset. 0x0 R/W 0 Long PN enabled. 1 Long PN held in reset.

Rev. 0 | Page 113 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 4 Reset PN short generator Test mode short pseudorandom number test generator reset. 0x0 R/W 0 Short PN enabled. 1 Short PN held in reset. [3:0] Test mode selection Test mode generation selection. 0x0 R/W 0000 Off (normal operation). 0001 Midscale short. 0010 Positive full scale. 0011 Negative full scale. 0100 Alternating checker board. 0101 PN sequence (long). 0110 PN sequence (short). 0111 1/0 word toggle.

1000 User pattern test mode (used with Register 0x0550, Bit 7 and

the User Pattern 1, User Pattern 2, User Pattern 3, and User Pattern 4 registers). 1111 Ramp output. 0x0551 User Pattern 1 LSB [7:0] User Pattern 1 [7:0] User Test Pattern 1 least significant byte. 0x0 R/W 0x0552 User Pattern 1 MSB [7:0] User Pattern 1 [15:8] User Test Pattern 1 leas t significant byte. 0x0 R/W 0x0553 User Pattern 2 LSB [7:0] User Pattern 2 [7:0] User Test Pattern 2 least significant byte. 0x0 R/W 0x0554 User Pattern 2 MSB [7:0] User Pattern 2 [15:8] User Test Pattern 2 leas t significant byte. 0x0 R/W 0x0555 User Pattern 3 LSB [7:0] User Pattern 3 [7:0] User Test Pattern 3 least significant bits. 0x0 R/W 0x0556 User Pattern 3 MSB [7:0] User Pattern 3 [15:8] User Test Pattern 3 leas t significant bits. 0x0 R/W 0x0557 User Pattern 4 LSB [7:0] User Pattern 4 [7:0] User Test Pattern 4 least significant bits. 0x0 R/W 0x0558 User Pattern 4 MSB [7:0] User Pattern 4 [15:8] User Test Pattern 4 leas t significant bits. 0x0 R/W 0x0559 Output Mode Control 1 [7:4] Converter control Bit 1 selection 0x0 R/W 0000 Tie low (1'b0). 0001 Overrange bit. 0010 Signal monitor bit . 0011 Fast detect (FD) bit. 0101 SYSREF. [3:0] Converter control Bit 0 selection 0x0 R/W 0000 Tie low (1'b0). 0001 Overrange bit. 0010 Signal monitor bit. 0011 Fast detect (FD) bit. 0101 SYSREF. 0x055A Output Mode Control 2 [7:4] Reserved Reserved. 0x0 R [3:0] Converter control Bit 2 selection 0x1 R/W 0000 Tie low (1'b0). 0001 Overrange bit. 0010 Signal monitor bit. 0011 Fast detect (FD) bit. 0101 SYSREF. 0x0561 Out sample mode [7:3] Reserved Reserved. 0x0 R/W

2 Sample invert 0x0 R/W

0 ADC sample data is not inverted. 1 ADC sample data is inverted. [1:0] Data format select 0x1 R/W 00 Offset binary.

01 Twos complement (default)

[7:0] Data format overrange clear Overrange clear bits (one bit for each virtual converter). Writing a 1 to the overrange clear bit clears the corresponding overrange sticky bit. 0x0 R/W 0 Overrange bit enabled. 1 Overrange bit cleared.

Rev. 0 | Page 114 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0563 Out overrange status [7:0] Data format overrange Overrange sticky bit status (one bit for each virtual converter). Writing a 1 to the overrange clear bit clears the corresponding overrange sticky bit. 0x0 R 0 No overrange occurred. 1 Overrange occurred. 0x0564 Out channel select [7:1 ] Reserved Reserved. 0x0 R

0 Converter channel swap

0 Normal channel ordering. 1 Channel swap enabled. 0x056E PLL control [7:4] JESD204B lane rate control 0x3 R/W 0000 Lane rate = 6.75 Gbps to 13.5 Gbps. 0001 Lane rate = 3.375 Gbps to 6.75 Gbps. 0011 Lane rate = 13.5 Gbps to 15.5 Gbps. 0101 Lane rate = 1.6875 Gbps to 3.375 Gbps. [3:0] Reserved Reserved. 0x0 R 0x056F PLL status 7 PLL lock status 0x0 R 0 Not locked. 1 Locked. [6:4] Reserved Reserved. 0x0 R 3 PLL loss of lock Loss of lock sticky bit. 1 Indicate a loss of lock has occurred at some time. Cleared by setting Register 0x0571, Bit 0. [2:0] Reserved Reserved 0x0570 f S × 4 configuration [7:0] See the fS × 4 Mode section. 0xFF R/W fS × 4 mode enabled. 0xFF f S × 4 mode disabled. L, M, and F set by Register 0x058B, Bits[4:0], Register 0x58E, Bits[7:0], and Register 0x058C, Bits[7:0], respectively. 0x0571 JESD204B Link Control 1

7 Standby mode 0x0 R/W

0 Standby mode forces zeros for all converter samples. 1 Standby mode forces code group synchronization (K28.5 characters).

6 Tail bit(t) PN 0x0 R/W

0 Disable. 1 Enable.

5 Long transport layer test 0x0 R/W

0 JESD204B test samples disabled.

1 JESD204B test samples enabled; long transport layer test

sample sequence (as specified in JESD204B Section 5.1.6.3) sent on all link lanes.

4 Lane synchronization 0x1 R/W

0 Disable FACI uses /K28.7/. 1 Enable FACI uses /K28.3/ and /K28.7/. [3:2] ILAS sequence mode 0x1 R/W

00 Initial lane alignmen t sequence disabled (JESD204B

Section 5.3.3.5). 01 Initial lane alignment sequen ce enabled (JESD204B Section 5.3.3.5). 11 Initial lane alignment sequence always on test mode. JESD204B data link layer test mode where repeated lane alignment sequence

1 FACI 0x0 R/W

0 Frame alignment character insertion enabled (JESD204B

Section 5.3.3.4). 1 Frame alignment character insertion disabled. For debug only (JESD204B Section 5.3.3.4).

Rev. 0 | Page 115 of 136 Addr. Name Bits Bit Name Settings Description Reset Access

0 Link control 0x0 R/W

0 JESD204B serial transmit link enabled. Transmission of the /K28.5/ characters for code group synchronization is controlled by the SYNC~ signal.

1 JESD204B serial transmit link powered down (held in reset and

clock gated). 0x0572 JESD204B Link Control 2 [7:6] SYNCINB± pin control 0x0 R/W 00 Normal mode. 10 Ignore SYNCINB± (force CGS). 11 Ignore SYNCINB± (force ILAS/user data).

5 SYNCINB± pin invert 0x0 R/W

0 SYNCINB± pin not inverted. 1 SYNCINB± pin inverted.

4 SYNCINB± pin type 0x0 R/W

0 LVDS differential pair SYNC~ input. 1 CMOS single-ended SYNC~ input. SYNCINB+ used. 3 Reserved Reserved. 0x0 R 2 8-bit/10-bit bypass 0x0 R/W 0 8-bit/10-bit enabled. 1 8-bit/10-bit bypassed (most significant 2 bits are 0). 1 8-bit/10-bit bit invert 0x0 R/W 0 Normal. 1 Invert a, b, c, d, e, f, g, h, I, and j symbols. 0 Reserved Reserved. 0x0 R/W 0x0573 JESD204B Link Control 3 [7:6] Checksum mode 0x0 R/W

00 Checksum is the sum of all 8-bit registers in the link

configuration table.

01 Checksum is the sum of all individual link configuration fields

(LSB aligned). 10 Checksum is disabled (set to zero). For test purposes only. 11 Unused. [5:4] Test injection point 0x0 R/W 0 N' sample input. 1 10-bit data at 8-bit/10-bit output (for PHY testing). 10 8-bit data at scrambler input. [3:0] JESD204B test mode patterns 0x0 R/W 0 Normal operation (test mode disabled). 1 Alternating checkerboard. 10 1/0 word toggle. 11 31-bit pseudorandom number (PN) sequence: x 31 + x28 + 1. 100 23-bit PN sequence: x 23 + x18 + 1. 101 15-bit PN sequence: x 15 + x14 + 1. 110 9-bit PN sequence: x 9 + x5 + 1. 111 7-bit PN sequence: x 7 + x6 + 1. 1000 Ramp output. 1110 Continuous/repeat user test. 1111 Single user test.

Rev. 0 | Page 116 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0574 JESD204B Link Control 4 [7:4] ILAS delay 0x0 R/W 0 Transmit ILAS on first LMFC after SYNCINB± deasserted. 1 Transmit ILAS on second LMFC after SYNCINB± deasserted. 10 Transmit ILAS on third LMFC after SYNCINB± deasserted. 11 Transmit ILAS on fourth LMFC after SYNCINB± deasserted. 100 Transmit ILAS on fifth LMFC after SYNCINB± deasserted. 101 Transmit ILAS on sixth LMFC after SYNCINB± deasserted. 110 Transmit ILAS on seventh LMFC after SYNCINB± deasserted. 111 Transmit ILAS on eighth LMFC after SYNCINB± deasserted. 1000 Transmit ILAS on ninth LMFC after SYNCINB± deasserted. 1001 Transmit ILAS on tenth LMFC after SYNCINB± deasserted. 1010 Transmit ILAS on eleventh LMFC after SYNCINB± deasserted. 1011 Transmit ILAS on twelfth LMFC after SYNCINB± deasserted. 1100 Transmit ILAS on thirteenth LMFC after SYNCINB± deasserted. 1101 Transmit ILAS on fourteenth LMFC after SYNCINB± deasserted. 1110 Transmit ILAS on fifteenth LMFC after SYNCINB± deasserted. 1111 Transmit ILAS on sixteenth LMFC after SYNCINB± deasserted. 3 Reserved Reserved. 0x0 R [2:0] Link layer test mode 0x0 R/W 000 Normal operation (link layer test mode disabled). 001 Continuous sequence of /D21.5/ characters. 010 Reserved. 011 Reserved. 100 Modified RPAT test sequence. 101 JSPAT test sequence. 110 JTSPAT test sequence. 111 Reserved. 0x0578 JESD204B LMFC offset [7:5] Reserved Reserved. 0x0 R [4:0] LMFC phase offset value Local multif rame clock (LMFC) phase offset value (in frame clocks). Refer to the Deterministic Latency section. 0x0 R/W 0x0580 JESD204B DID configuration [7:0] JESD204B Tx DID value JESD204B serial device identification (DID) number. 0x0 R/W 0x0581 JESD204B BID configuration [7:4] Reserved Reserved. 0x0 R [3:0] JESD204B Tx BID value JESD204B serial bank identification (BID) number (extension to DID). 0x0 R/W 0x0583 JESD204B LID0 configuration [7:5] Reserved Reserved. 0x0 R [4:0] Lane 0 LID value JESD204B serial lane identification (LID) number for Lane 0. 0x0 R/W 0x0584 JESD204B LID1 configuration [7:5] Reserved Reserved. 0x0 R [4:0] Lane 1 LID value JESD204B serial lane identification (LID) number for Lane 1. 0x1 R/W 0x0585 JESD204B LID2 configuration [7:5] Reserved Reserved. 0x0 R [4:0] Lane 2 LID value JESD204B serial lane identification (LID) number for Lane 2. 0x2 R/W 0x0586 JESD204B LID3 configuration [7:5] Reserved Reserved. 0x0 R [4:0] Lane 3 LID value JESD204B serial lane identification (LID) number for Lane 3. 0x3 R/W 0x0587 JESD204B LID4 configuration [7:5] Reserved Reserved. 0x0 R [4:0] Lane 4 LID value JESD204B serial lane identification (LID) number for Lane 4. 0x4 R/W 0x0588 JESD204B LID5 configuration [7:5] Reserved Reserved. 0x0 R [4:0] Lane 5 LID value JESD204B serial lane identification (LID) number for Lane 5. 0x5 R/W 0x0589 JESD204B LID6 configuration [7:5] Reserved Reserved. 0x0 R [4:0] Lane 6 LID value JESD204B serial lane identification (LID) number for Lane 6. 0x6 R/W 0x058A JESD204B LID7 configuration [7:5] Reserved Reserved. 0x0 R [4:0] Lane 7 LID value JESD204B serial lane identification (LID) number for Lane 7. 0x7 R/W

Rev. 0 | Page 117 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x058B JESD204B scrambling and number lanes (L) configuration

7 JESD204B scrambling

(SCR) 0x1 R/W 0 JESD204B scrambler disabled (SCR = 0). 1 JESD204B scrambler enabled (SCR = 1). [6:5] Reserved Reserved. 0x0 R [4:0] JESD204B lanes (L) 0x7 R/W 0x0 One lane per link (L = 1). 0x1 Two lanes per link (L = 2). 0x3 Four lanes per link (L = 4). 0x7 Eight lanes per Link (L = 8). 0x058C JESD204B link number of octets per frames (F) [7:0] JESD204B F configuratio n JESD204B number of octe ts per frame (F = JESD204B F configuration + 1) 0x0 R/W 0 F = 1. 1 F = 2. 10 F = 3. 11 F = 4. 101 F = 6. 111 F = 8. 1111 F = 16. 0x058D JESD204B link number of frames per multiframe (K) [7:5] Reserved Reserved. 0x0 R [4:0] JESD204B K configuration JESD204B number of frames per multiframe (K = JESD204B K configuration + 1). Only values where F × K is divisible by 4 can be used. 0x1F R/W 0x058E JESD204B link number of converters (M) [7:0] JESD204B M configuration JESD204B number of converters per link/device (M = JESD204B M configuration). 0x1 R/W 0 Link connected to one virtual converter (M = 1). 1 Link connected to two virtual converters (M = 2). 11 Link connected to four virtual converters (M = 4). 111 Link connected to eight virtual converters (M = 8). 0x058F JESD204B number of control bits (CS) and ADC resolution (N) [7:6] Number of control bits (CS) per sample 0x0 R/W 0 No control bits (CS = 0). 1 1 control bit (CS = 1), Control Bit 2 only. 10 2 control bits (CS = 2), Control Bit 2 and Control Bit 1 only. 11 3 control bits (CS = 3), all control bits (Control Bit 2, Control Bit 1, and Control Bit 0). 5 Reserved Reserved. 0x0 R [4:0] ADC converter resolution (N) 0xF R/W 00110 N = 7-bit resolution. 00111 N = 8-bit resolution. 01000 N = 9-bit resolution. 01001 N = 10-bit resolution. 01010 N = 11-bit resolution. 01011 N = 12-bit resolution. 01100 N = 13-bit resolution. 01101 N = 14-bit resolution. 01110 N = 15-bit resolution. 01111 N = 16-bit resolution.

Rev. 0 | Page 118 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0590 JESD204B SCV NP configuration [7:5] Subclass support 0x1 R/W 000 Subclass 0. 001 Subclass 1. [4:0] ADC number of bits per sample(N') 0xF R/W 0 0111 N' = 8. 0 1011 N' = 12. 0 1111 N' = 16. 0x0591 JESD204B JV S configuration [7:5] Reserved Reserved. 0x1 R [4:0] Samples per converter frame cycle (S) Samples per converter frame cycle (S = Register 0x0591, Bits[4:0] + 1). 0x0 R 0x0592 JESD204B HD CF configuration

7 HD value 0x0 R

0 High density format disabled. 1 High density format enabled. [6:5] Reserved Reserved. 0x0 R [4:0] Control words per frame clock cycle per link (CF) Number of control words per frame clock cycle per link (CF = Register 0x0592, Bits[4:0]). 0x0 R 0x05A0 JESD204B Checksum 0 configuration [7:0] Checksum 0 checksum value for SERDOUT0± Serial checksum value for Lane 0. Automatically calculated for each lane. Sum (all link configuration parameters for Lane 0) mod 256. 0xC3 R 0x05A1 JESD204B Checksum 1 configuration [7:0] Checksum 1 checksum value for SERDOUT1± Serial checksum value for Lane 1. Automatically calculated for each lane. Sum (all link configuration parameters for Lane 1) mod 256. 0xC4 R 0x05A2 JESD204B Checksum 2 configuration [7:0] Checksum 2 checksum value for SERDOUT2± Serial checksum value for Lane 2. Automatically calculated for each lane. Sum (all link configuration parameters for each lane) mod 256. 0xC5 R 0x05A3 JESD204B Checksum 3 configuration [7:0] Checksum 3 checksum value for SERDOUT3± Serial checksum value for Lane 3. Automatically calculated for each lane. Sum (all link configuration parameters for Lane 3) mod 256. 0xC6 R 0x05B0 JESD204B lane power-down

7 JESD204B Lane 7 power-

Physical Lane 7 force power-down. 0x0 R/W 0 SERDOUT7± normal operation. 1 SERDOUT7± power-down.

6 JESD204B Lane 6 power-

Physical Lane 6 force power-down. 0x0 R/W 0 SERDOUT6± normal operation. 1 SERDOUT6± power-down.

5 JESD204B Lane 5 power-

Physical Lane 5 force power-down. 0x0 R/W 0 SERDOUT5± normal operation. 1 SERDOUT5± power-down.

4 JESD204B Lane 4 power-

Physical Lane 4 force power-down. 0x0 R/W 0 SERDOUT4± normal operation. 1 SERDOUT4± power-down.

3 JESD204B Lane 3 power-

Physical Lane 3 force power-down. 0x0 R/W 0 SERDOUT3± normal operation. 1 SERDOUT3± power-down.

2 JESD204B Lane 2 power-

Physical Lane 2 force power-down. 0x0 R/W 0 SERDOUT2± normal operation. 1 SERDOUT2± power-down.

1 JESD204B Lane 1 power-

Physical Lane 1 force power-down. 0x0 R/W 0 SERDOUT1± normal operation. 1 SERDOUT1± power-down.

0 JESD204B Lane 0 power-

Physical Lane 0 force power-down. 0x0 R/W 0 SERDOUT0± normal operation. 1 SERDOUT0± power-down.

Rev. 0 | Page 119 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x05B2 JESD204B Lane Assign 1 7 Reserved Reserved. 0x0 R [6:4] SERDOUT1± lane assignment Physical Lane 1 assignment. 0x1 R/W 0 Logical Lane 0. 1 Logical Lane 1 (default). 10 Logical Lane 2. 11 Logical Lane 3. 100 Logical Lane 4. 101 Logical Lane 5. 110 Logical Lane 6. 111 Logical Lane 7. 3 Reserved Reserved. 0x0 R [2:0] SERDOUT0± lane assignment Physical Lane 0 assignment. 0x0 R/W 0 Logical Lane 0 (default). 1 Logical Lane 1. 10 Logical Lane 2. 11 Logical Lane 3. 100 Logical Lane 4. 101 Logical Lane 5. 110 Logical Lane 6. 111 Logical Lane 7. 0x05B3 JESD204B Lane Assign 2 7 Reserved Reserved. 0x0 R [6:4] SERDOUT3± lane assignment Physical Lane 3 assignment. 0x3 R/W 0 Logical Lane 0. 1 Logical Lane 1. 10 Logical Lane 2. 11 Logical Lane 3 (default). 100 Logical Lane 4. 101 Logical Lane 5. 110 Logical Lane 6. 111 Logical Lane 7. 3 Reserved Reserved. 0x0 R [2:0] SERDOUT2± lane assignment Physical Lane 2 assignment. 0x2 R/W 0 Logical Lane 0.

1 Logical Lane 1

10 Logical Lane 2 (default). 11 Logical Lane 3. 100 Logical Lane 4. 101 Logical Lane 5. 110 Logical Lane 6. 111 Logical Lane 7. 0x05B5 JESD204B Lane Assign 3 7 Reserved Reserved. 0x0 R [6:4] SERDOUT5± lane assignment Physical Lane 5 assignment. 0x5 R/W 0 Logical Lane 0. 1 Logical Lane 1. 10 Logical Lane 2. 11 Logical Lane 3. 100 Logical Lane 4. 101 Logical Lane 5 (default). 110 Logical Lane 6. 111 Logical Lane 7. 3 Reserved Reserved. 0x0 R

Rev. 0 | Page 120 of 136 Addr. Name Bits Bit Name Settings Description Reset Access [2:0] SERDOUT4± lane assignment Physical Lane 4 assignment. 0x4 R/W 0 Logical Lane 0. 1 Logical Lane 1. 10 Logical Lane 2. 11 Logical Lane 3. 100 Logical Lane 4 (default). 101 Logical Lane 5. 110 Logical Lane 6. 111 Logical Lane 7. 0x05B6 JESD204B Lane Assign 4 7 Reserved Reserved. 0x0 R [6:4] SERDOUT7± lane assignment Physical Lane 7 assignment. 0x7 R/W 0 Logical Lane 0. 1 Logical Lane 1. 10 Logical Lane 2. 11 Logical Lane 3. 100 Logical Lane 4. 101 Logical Lane 5. 110 Logical Lane 6. 111 Logical Lane 7 (default). 3 Reserved Reserved. 0x0 R [2:0] SERDOUT6± lane assignment Physical Lane 6 assignment. 0x6 R/W 0 Logical Lane 0. 1 Logical Lane 1. 10 Logical Lane 2. 11 Logical Lane 3. 100 Logical Lane 4. 101 Logical Lane 5. 110 Logical Lane 6 (default). 111 Logical Lane 7. 0x05BF SERDOUTx± data invert 7 Invert SERDOUT7± data In vert SERDOUT7± data. 0x0 R/W 0 Normal. 1 Invert. 6 Invert SERDOUT6± data Invert SERDOUT6± data. 0x0 R/W 0 Normal. 1 Invert. 5 Invert SERDOUT5± data Invert SERDOUT5± data. 0x0 R/W 0 Normal. 1 Invert. 4 Invert SERDOUT4± data Invert SERDOUT4± data. 0x0 R/W 0 Normal. 1 Invert. 3 Invert SERDOUT3± data Invert SERDOUT3± data. 0x0 R/W 0 Normal. 1 Invert. 2 Invert SERDOUT2± data Invert SERDOUT2± data. 0x0 R/W 0 Normal. 1 Invert. 1 Invert SERDOUT1± data Invert SERDOUT1± data. 0x0 R/W 0 Normal. 1 Invert. 0 Invert SERDOUT0± data Invert SERDOUT0± data. 0x0 R/W 0 Normal. 1 Invert.

Rev. 0 | Page 121 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x05C0 JESD204B Swing Adjust 1 7 Reserved Reserved. 0x0 R [6:4] SERDOUT1± voltage swing adjust Output swing level for SERDOUT1±. 0x1 R/W 000 1.0 × DRVDD1. 001 0.850 × DRVDD1. 010 0.750 × DRVDD1. 3 Reserved Reserved. 0x0 R [2:0] SERDOUT0± voltage swing adjust Output swing level for SERDOUT0±. 0x1 R/W 000 1.0 × DRVDD1. 001 0.850 × DRVDD1. 010 0.750 × DRVDD1. 0x05C1 JESD204B Swing Adjust 2 7 Reserved Reserved. 0x0 R [6:4] SERDOUT3± voltage swing adjust Output swing level for SERDOUT3±. 0x1 R/W 000 1.0 × DRVDD1. 001 0.850 × DRVDD1. 010 0.750 × DRVDD1. 3 Reserved Reserved. 0x0 R [2:0] SERDOUT2± voltage swing adjust Output swing level for SERDOUT2±. 0x1 R/W 000 1.0 × DRVDD1. 001 0.850 × DRVDD1. 010 0.750 × DRVDD1. 0x05C2 JESD204B Swing Adjust 3 7 Reserved Reserved. 0x0 R [6:4] SERDOUT5± voltage swing adjust Output swing level for SERDOUT5±. 0x1 R/W 000 1.0 × DRVDD1. 001 0.850 × DRVDD1. 010 0.750 × DRVDD1. 3 Reserved Reserved. 0x0 R [2:0] SERDOUT4± voltage swing adjust Output swing level for SERDOUT4±. 0x1 R/W 000 1.0 × DRVDD1. 001 0.850 × DRVDD1. 010 0.750 × DRVDD1. 0x05C3 JESD204B Swing Adjust 4 7 Reserved Reserved. 0x0 R [6:4] SERDOUT7± voltage swing adjust Output swing level for SERDOUT7±. 0x1 R/W 000 1.0 × DRVDD1. 001 0.850 × DRVDD1. 010 0.750 × DRVDD1. 3 Reserved Reserved. 0x0 R [2:0] SERDOUT6± voltage swing adjust Output swing level for SERDOUT6±. 0x1 R/W 000 1.0 × DRVDD1. 001 0.850 × DRVDD1. 010 0.750 × DRVDD1.

Rev. 0 | Page 122 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x05C4 SERDOUT0 pre- emphasis select 7 Post tap enable Post tap enable. 0x0 R/W 0 Disable. 1 Enable. [6:4] Set post tap level for SERDOUT0± Set post tap level. 0x0 R/W 000 0 dB. 001 3 dB. 010 6 dB. 011 9 dB. 100 12 dB. [3:0] Reserved Reserved. 0x0 R/W 0x05C5 SERDOUT1 pre- emphasis select 7 Post tap enable Post tap enable. 0x0 R/W 0 Disable. 1 Enable. [6:4] Set post tap level for SERDOUT1± Set post tap level. 0x0 R/W 000 0 dB. 001 3 dB. 010 6 dB. 011 9 dB. 100 12 dB. [3:0] Reserved Reserved. 0x0 R/W 0x05C6 SERDOUT2 pre- emphasis select 7 Post tap enable Post tap enable. 0x0 R/W 0 Disable. 1 Enable. [6:4] Set post tap level for SERDOUT2± Set post tap level. 0x0 R/W 000 0 dB. 001 3 dB. 010 6 dB. 011 9 dB. 100 12 dB. [3:0] Reserved Reserved. 0x0 R/W 0x05C7 SERDOUT3 pre- emphasis select 7 Post tap enable Post tap enable. 0x0 R/W 0 Disable. 1 Enable. [6:4] Set post tap level for SERDOUT3± Set post tap level. 0x0 R/W 000 0 dB. 001 3 dB. 010 6 dB. 011 9 dB. 100 12 dB. [3:0] Reserved Reserved. 0x0 R/W 0x05C8 SERDOUT4 pre- emphasis select 7 Post tap enable Post tap enable. 0x0 R/W 0 Disable. 1 Enable. [6:4] Set post tap level for SERDOUT4± Set post tap level. 0x0 R/W 000 0 dB. 001 3 dB. 010 6 dB. 011 9 dB. 100 12 dB. [3:0] Reserved Reserved. 0x0 R/W

Rev. 0 | Page 123 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x05C9 SERDOUT5 pre- emphasis select 7 Post tap enable Post tap enable. 0x0 R/W 0 Disable. 1 Enable. [6:4] Set post tap level for SERDOUT5± Set post tap level. 0x0 R/W 000 0 dB. 001 3 dB. 010 6 dB. 011 9 dB. 100 12 dB. [3:0] Reserved Reserved. 0x0 R/W 0x05CA SERDOUT6 pre- emphasis select 7 Post tap enable Post tap enable. 0x0 R/W 0 Disable. 1 Enable. [6:4] Set post tap level for SERDOUT6± Set post tap level. 0x0 R/W 000 0 dB. 001 3 dB. 010 6 dB. 011 9 dB. 100 12 dB. [3:0] Reserved Reserved. 0x0 R/W 0x05CB SERDOUT7 pre- emphasis select 7 Post tap enable Post tap enable. 0x0 R/W

0 Disable

1 Enable

[6:4] Set post tap level for SERDOUT7± Set post tap level. 0x0 R/W 000 0 dB. 001 3 dB. 010 6 dB. 011 9 dB. 100 12 dB. [3:0] Reserved Reserved. 0x0 R/W 0x1222 JESD204B PLL calibration [7:0] See Table 32. 0x00 R/W 0x00 JESD204B PLL Normal Operation 0x04 Reset JESD204B PLL calibration 0x1228 JESD204B PLL start-up control [7:0] See Table 32. 0x0F R/W 0x0F JESD204B start-up circuit in normal operation. 0x4F Reset JESD204B start-up circuit. 0x1262 JESD204B PLL LOL bit control [7:0] See Table 32. 0x00 R/W 0x00 Loss of lock bit normal operation. 0x80 Clear loss of lock bit.

Rev. 0 | Page 124 of 136 Addr. Name Bits Bit Name Settings Description Reset Access Programmable Filter Control and Coefficients Registers 0x0DF8 PFILT control [7:3] Reserved Reserved. 0x0 R [2:0] PFILT mode Programmable filter (PFILT) mode. 0x0 R/W 000 = disabled (filters bypassed). 001 = single filter (X only). DOUT_I[n] = DIN_I[n] * X_I[n]. DOUT_Q[n] = DIN_Q[n] * X_Q[n]. 010 = single filter (X and Y together). DOUT_I[n] = DIN_I[n] * XY_I[n]. DOUT_Q[n] = DIN_Q[n] * XY_Q[n]. 100 = cascaded filters (X to Y). DOUT_I[n] = DIN_I[n] * X_I[n] * Y_I[n]. DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n]. DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n]. 101 = complex filters. DOUT_I[n] = DIN_I[n] * X_I[n] + DIN_Q[n] * Y_Q[n]. DOUT_Q[n] = DIN_Q[n] * X_Q[n] + DIN_I[n] * Y_I[n]. 110 = half complex filter. DOUT_I[n] = DIN_I[n]. DOUT_Q[n] = DIN_Q[n] * XY_Q[n] + DIN_I[n] * XY_I[n]. 111 = real 96-tap filter. DOUT_I[n] = DIN_I[n] * XY_I[n]. DOUT_Q[n] = DIN_Q[n] * XY_Q[n]. 0x0DF9 PFILT gain 7 Reserved Reserved. 0x0 R [6:4] PFILT Y gain PFILT Y gain. 0x0 R/W 110 −12 dB loss. 111 −6 dB loss. 000 0 dB gain. 001 +6 dB gain. 010 +12 dB gain. 3 Reserved Reserved. 0x0 R [2:0] PFILT X gain PFILT X gain. 0x0 R/W 110 −12 dB loss. 111 −6 dB loss. 000 0 dB gain. 001 +6 dB gain. 010 +12 dB gain. 0x0E00 PFILT X Coefficient 0 [7:0] PFILT X Coefficient 0 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E01 PFILT X Coefficient 1 [7:0] PFILT X Coefficient 1 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E02 PFILT X Coefficient 2 [7:0] PFILT X Coefficient 2 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E03 PFILT X Coefficient 3 [7:0] PFILT X Coefficient 3 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E04 PFILT X Coefficient 4 [7:0] PFILT X Coefficient 4 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E05 PFILT X Coefficient 5 [7:0] PFILT X Coefficient 5 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E06 PFILT X Coefficient 6 [7:0] PFILT X Coefficient 6 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E07 PFILT X Coefficient 7 [7:0] PFILT X Coefficient 7 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E08 PFILT X Coefficient 8 [7:0] PFILT X Coefficient 8 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E09 PFILT X Coefficient 9 [7:0] PFILT X Coefficient 9 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E0A PFILT X Coefficient 10 [7:0] PFILT X Coefficient 10 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E0B PFILT X Coefficient 11 [7:0] PFILT X Coefficient 11 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W

Rev. 0 | Page 125 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0E0C PFILT X Coefficient 12 [7:0] PFILT X Coefficient 12 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E0D PFILT X Coefficient 13 [7:0] PFILT X Coefficient 13 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E0E PFILT X Coefficient 14 [7:0] PFILT X Coefficient 14 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E0F PFILT X Coefficient 15 [7:0] PFILT X Coefficient 15 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E10 PFILT X Coefficient 16 [7:0] PFILT X Coefficient 16 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E11 PFILT X Coefficient 17 [7:0] PFILT X Coefficient 17 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E12 PFILT X Coefficient 18 [7:0] PFILT X Coefficient 18 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E13 PFILT X Coefficient 19 [7:0] PFILT X Coefficient 19 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E14 PFILT X Coefficient 20 [7:0] PFILT X Coefficient 20 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E15 PFILT X Coefficient 21 [7:0] PFILT X Coefficient 21 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E16 PFILT X Coefficient 22 [7:0] PFILT X Coefficient 22 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E17 PFILT X Coefficient 23 [7:0] PFILT X Coefficient 23 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E18 PFILT X Coefficient 24 [7:0] PFILT X Coefficient 24 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E19 PFILT X Coefficient 25 [7:0] PFILT X Coefficient 25 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E1A PFILT X Coefficient 26 [7:0] PFILT X Coefficient 26 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E1B PFILT X Coefficient 27 [7:0] PFILT X Coefficient 27 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E1C PFILT X Coefficient 28 [7:0] PFILT X Coefficient 28 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E1D PFILT X Coefficient 29 [7:0] PFILT X Coefficient 29 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E1E PFILT X Coefficient 30 [7:0] PFILT X Coefficient 30 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E1F PFILT X Coefficient 31 [7:0] PFILT X Coefficient 31 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E20 PFILT X Coefficient 32 [7:0] PFILT X Coefficient 32 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E21 PFILT X Coefficient 33 [7:0] PFILT X Coefficient 33 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E22 PFILT X Coefficient 34 [7:0] PFILT X Coefficient 34 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E23 PFILT X Coefficient 35 [7:0] PFILT X Coefficient 35 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E24 PFILT X Coefficient 36 [7:0] PFILT X Coefficient 36 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E25 PFILT X Coefficient 37 [7:0] PFILT X Coefficient 37 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E26 PFILT X Coefficient 38 [7:0] PFILT X Coefficient 38 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E27 PFILT X Coefficient 39 [7:0] PFILT X Coefficient 39 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E28 PFILT X Coefficient 40 [7:0] PFILT X Coefficient 40 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E29 PFILT X Coefficient 41 [7:0] PFILT X Coefficient 41 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E2A PFILT X Coefficient 42 [7:0] PFILT X Coefficient 42 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E2B PFILT X Coefficient 43 [7:0] PFILT X Coefficient 43 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W

Rev. 0 | Page 126 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0E2C PFILT X Coefficient 44 [7:0] PFILT X Coefficient 44 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E2D PFILT X Coefficient 45 [7:0] PFILT X Coefficient 45 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E2E PFILT X Coefficient 46 [7:0] PFILT X Coefficient 46 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E2F PFILT X Coefficient 47 [7:0] PFILT X Coefficient 47 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E30 PFILT X Coefficient 48 [7:0] PFILT X Coefficient 48 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E31 PFILT X Coefficient 49 [7:0] PFILT X Coefficient 49 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E32 PFILT X Coefficient 50 [7:0] PFILT X Coefficient 50 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E33 PFILT X Coefficient 51 [7:0] PFILT X Coefficient 51 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E34 PFILT X Coefficient 52 [7:0] PFILT X Coefficient 52 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E35 PFILT X Coefficient 53 [7:0] PFILT X Coefficient 53 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E36 PFILT X Coefficient 54 [7:0] PFILT X Coefficient 54 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E37 PFILT X Coefficient 55 [7:0] PFILT X Coefficient 55 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E38 PFILT X Coefficient 56 [7:0] PFILT X Coefficient 56 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E39 PFILT X Coefficient 57 [7:0] PFILT X Coefficient 57 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E3A PFILT X Coefficient 58 [7:0] PFILT X Coefficient 58 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E3B PFILT X Coefficient 59 [7:0] PFILT X Coefficient 59 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E3C PFILT X Coefficient 60 [7:0] PFILT X Coefficient 60 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E3D PFILT X Coefficient 61 [7:0] PFILT X Coefficient 61 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E3E PFILT X Coefficient 62 [7:0] PFILT X Coefficient 62 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E3F PFILT X Coefficient 63 [7:0] PFILT X Coefficient 63 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E40 PFILT X Coefficient 64 [7:0] PFILT X Coefficient 64 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E41 PFILT X Coefficient 65 [7:0] PFILT X Coefficient 65 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E42 PFILT X Coefficient 66 [7:0] PFILT X Coefficient 66 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E43 PFILT X Coefficient 67 [7:0] PFILT X Coefficient 67 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E44 PFILT X Coefficient 68 [7:0] PFILT X Coefficient 68 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E45 PFILT X Coefficient 69 [7:0] PFILT X Coefficient 69 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E46 PFILT X Coefficient 70 [7:0] PFILT X Coefficient 70 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E47 PFILT X Coefficient 71 [7:0] PFILT X Coefficient 71 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E48 PFILT X Coefficient 72 [7:0] PFILT X Coefficient 72 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E49 PFILT X Coefficient 73 [7:0] PFILT X Coefficient 73 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E4A PFILT X Coefficient 74 [7:0] PFILT X Coefficient 74 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E4B PFILT X Coefficient 75 [7:0] PFILT X Coefficient 75 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W

Rev. 0 | Page 127 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0E4C PFILT X Coefficient 76 [7:0] PFILT X Coefficient 76 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E4D PFILT X Coefficient 77 [7:0] PFILT X Coefficient 77 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E4E PFILT X Coefficient 78 [7:0] PFILT X Coefficient 78 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E4F PFILT X Coefficient 79 [7:0] PFILT X Coefficient 79 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E50 PFILT X Coefficient 80 [7:0] PFILT X Coefficient 80 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E51 PFILT X Coefficient 81 [7:0] PFILT X Coefficient 81 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E52 PFILT X Coefficient 82 [7:0] PFILT X Coefficient 82 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E53 PFILT X Coefficient 83 [7:0] PFILT X Coefficient 83 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E54 PFILT X Coefficient 84 [7:0] PFILT X Coefficient 84 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E55 PFILT X Coefficient 85 [7:0] PFILT X Coefficient 85 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E56 PFILT X Coefficient 86 [7:0] PFILT X Coefficient 86 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E57 PFILT X Coefficient 87 [7:0] PFILT X Coefficient 87 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E58 PFILT X Coefficient 88 [7:0] PFILT X Coefficient 88 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E59 PFILT X Coefficient 89 [7:0] PFILT X Coefficient 89 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E5A PFILT X Coefficient 90 [7:0] PFILT X Coefficient 90 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E5B PFILT X Coefficient 91 [7:0] PFILT X Coefficient 91 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E5C PFILT X Coefficient 92 [7:0] PFILT X Coefficient 92 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E5D PFILT X Coefficient 93 [7:0] PFILT X Coefficient 93 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E5E PFILT X Coefficient 94 [7:0] PFILT X Coefficient 94 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E5F PFILT X Coefficient 95 [7:0] PFILT X Coefficient 95 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E60 PFILT X Coefficient 96 [7:0] PFILT X Coefficient 96 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E61 PFILT X Coefficient 97 [7:0] PFILT X Coefficient 97 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E62 PFILT X Coefficient 98 [7:0] PFILT X Coefficient 98 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E63 PFILT X Coefficient 99 [7:0] PFILT X Coefficient 99 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E64 PFILT X Coefficient 100 [7:0] PFILT X Coefficient 100 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E65 PFILT X Coefficient 101 [7:0] PFILT X Coefficient 101 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E66 PFILT X Coefficient 102 [7:0] PFILT X Coefficient 102 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E67 PFILT X Coefficient 103 [7:0] PFILT X Coefficient 103 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E68 PFILT X Coefficient 104 [7:0] PFILT X Coefficient 104 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E69 PFILT X Coefficient 105 [7:0] PFILT X Coefficient 105 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E6A PFILT X Coefficient 106 [7:0] PFILT X Coefficient 106 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E6B PFILT X Coefficient 107 [7:0] PFILT X Coefficient 107 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W

Rev. 0 | Page 128 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0E6C PFILT X Coefficient 108 [7:0] PFILT X Coefficient 108 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E6D PFILT X Coefficient 109 [7:0] PFILT X Coefficient 109 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E6E PFILT X Coefficient 110 [7:0] PFILT X Coefficient 110 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E6F PFILT X Coefficient 111 [7:0] PFILT X Coefficient 111 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E70 PFILT X Coefficient 112 [7:0] PFILT X Coefficient 112 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E71 PFILT X Coefficient 113 [7:0] PFILT X Coefficient 113 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E72 PFILT X Coefficient 114 [7:0] PFILT X Coefficient 114 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E73 PFILT X Coefficient 115 [7:0] PFILT X Coefficient 115 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E74 PFILT X Coefficient 116 [7:0] PFILT X Coefficient 116 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E75 PFILT X Coefficient 117 [7:0] PFILT X Coefficient 117 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E76 PFILT X Coefficient 118 [7:0] PFILT X Coefficient 118 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E77 PFILT X Coefficient 119 [7:0] PFILT X Coefficient 119 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E78 PFILT X Coefficient 120 [7:0] PFILT X Coefficient 120 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E79 PFILT X Coefficient 121 [7:0] PFILT X Coefficient 121 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E7A PFILT X Coefficient 122 [7:0] PFILT X Coefficient 122 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E7B PFILT X Coefficient 123 [7:0] PFILT X Coefficient 123 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E7C PFILT X Coefficient 124 [7:0] PFILT X Coefficient 124 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E7D PFILT X Coefficient 125 [7:0] PFILT X Coefficient 125 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E7E PFILT X Coefficient 126 [7:0] PFILT X Coefficient 126 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0E7F PFILT X Coefficient 127 [7:0] PFILT X Coefficient 127 Programmable Fi lter X coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F00 PFILT Y Coefficient 0 [7:0] PFILT Y Coefficient 0 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F01 PFILT Y Coefficient 1 [7:0] PFILT Y Coefficient 1 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F02 PFILT Y Coefficient 2 [7:0] PFILT Y Coefficient 2 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F03 PFILT Y Coefficient 3 [7:0] PFILT Y Coefficient 3 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F04 PFILT Y Coefficient 4 [7:0] PFILT Y Coefficient 4 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F05 PFILT Y Coefficient 5 [7:0] PFILT Y Coefficient 5 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F06 PFILT Y Coefficient 6 [7:0] PFILT Y Coefficient 6 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F07 PFILT Y Coefficient 7 [7:0] PFILT Y Coefficient 7 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F08 PFILT Y Coefficient 8 [7:0] PFILT Y Coefficient 8 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F09 PFILT Y Coefficient 9 [7:0] PFILT Y Coefficient 9 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F0A PFILT Y Coefficient 10 [7:0] PFILT Y Coefficient 10 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F0B PFILT Y Coefficient 11 [7:0] PFILT Y Coefficient 11 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W

Rev. 0 | Page 129 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0F0C PFILT Y Coefficient 12 [7:0] PFILT Y Coefficient 12 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F0D PFILT Y Coefficient 13 [7:0] PFILT Y Coefficient 13 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F0E PFILT Y Coefficient 14 [7:0] PFILT Y Coefficient 14 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F0F PFILT Y Coefficient 15 [7:0] PFILT Y Coefficient 15 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F10 PFILT Y Coefficient 16 [7:0] PFILT Y Coefficient 16 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F11 PFILT Y Coefficient 17 [7:0] PFILT Y Coefficient 17 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F12 PFILT Y Coefficient 18 [7:0] PFILT Y Coefficient 18 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F13 PFILT Y Coefficient 19 [7:0] PFILT Y Coefficient 19 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F14 PFILT Y Coefficient 20 [7:0] PFILT Y Coefficient 20 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F15 PFILT Y Coefficient 21 [7:0] PFILT Y Coefficient 21 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F16 PFILT Y Coefficient 22 [7:0] PFILT Y Coefficient 22 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F17 PFILT Y Coefficient 23 [7:0] PFILT Y Coefficient 23 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F18 PFILT Y Coefficient 24 [7:0] PFILT Y Coefficient 24 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F19 PFILT Y Coefficient 25 [7:0] PFILT Y Coefficient 25 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F1A PFILT Y Coefficient 26 [7:0] PFILT Y Coefficient 26 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F1B PFILT Y Coefficient 27 [7:0] PFILT Y Coefficient 27 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F1C PFILT Y Coefficient 28 [7:0] PFILT Y Coefficient 28 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F1D PFILT Y Coefficient 29 [7:0] PFILT Y Coefficient 29 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F1E PFILT Y Coefficient 30 [7:0] PFILT Y Coefficient 30 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F1F PFILT Y Coefficient 31 [7:0] PFILT Y Coefficient 31 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F20 PFILT Y Coefficient 32 [7:0] PFILT Y Coefficient 32 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F21 PFILT Y Coefficient 33 [7:0] PFILT Y Coefficient 33 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F22 PFILT Y Coefficient 34 [7:0] PFILT Y Coefficient 34 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F23 PFILT Y Coefficient 35 [7:0] PFILT Y Coefficient 35 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F24 PFILT Y Coefficient 36 [7:0] PFILT Y Coefficient 36 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F25 PFILT Y Coefficient 37 [7:0] PFILT Y Coefficient 37 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F26 PFILT Y Coefficient 38 [7:0] PFILT Y Coefficient 38 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F27 PFILT Y Coefficient 39 [7:0] PFILT Y Coefficient 39 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F28 PFILT Y Coefficient 40 [7:0] PFILT Y Coefficient 40 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F29 PFILT Y Coefficient 41 [7:0] PFILT Y Coefficient 41 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F2A PFILT Y Coefficient 42 [7:0] PFILT Y Coefficient 42 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F2B PFILT Y Coefficient 43 [7:0] PFILT Y Coefficient 43 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W

Rev. 0 | Page 130 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0F2C PFILT Y Coefficient 44 [7:0] PFILT Y Coefficient 44 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F2D PFILT Y Coefficient 45 [7:0] PFILT Y Coefficient 45 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F2E PFILT Y Coefficient 46 [7:0] PFILT Y Coefficient 46 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F2F PFILT Y Coefficient 47 [7:0] PFILT Y Coefficient 47 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F30 PFILT Y Coefficient 48 [7:0] PFILT Y Coefficient 48 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F31 PFILT Y Coefficient 49 [7:0] PFILT Y Coefficient 49 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F32 PFILT Y Coefficient 50 [7:0] PFILT Y Coefficient 50 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F33 PFILT Y Coefficient 51 [7:0] PFILT Y Coefficient 51 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F34 PFILT Y Coefficient 52 [7:0] PFILT Y Coefficient 52 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F35 PFILT Y Coefficient 53 [7:0] PFILT Y Coefficient 53 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F36 PFILT Y Coefficient 54 [7:0] PFILT Y Coefficient 54 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F37 PFILT Y Coefficient 55 [7:0] PFILT Y Coefficient 55 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F38 PFILT Y Coefficient 56 [7:0] PFILT Y Coefficient 56 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F39 PFILT Y Coefficient 57 [7:0] PFILT Y Coefficient 57 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F3A PFILT Y Coefficient 58 [7:0] PFILT Y Coefficient 58 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F3B PFILT Y Coefficient 59 [7:0] PFILT Y Coefficient 59 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F3C PFILT Y Coefficient 60 [7:0] PFILT Y Coefficient 60 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F3D PFILT Y Coefficient 61 [7:0] PFILT Y Coefficient 61 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F3E PFILT Y Coefficient 62 [7:0] PFILT Y Coefficient 62 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F3F PFILT Y Coefficient 63 [7:0] PFILT Y Coefficient 63 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F40 PFILT Y Coefficient 64 [7:0] PFILT Y Coefficient 64 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F41 PFILT Y Coefficient 65 [7:0] PFILT Y Coefficient 65 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F42 PFILT Y Coefficient 66 [7:0] PFILT Y Coefficient 66 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F43 PFILT Y Coefficient 67 [7:0] PFILT Y Coefficient 67 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F44 PFILT Y Coefficient 68 [7:0] PFILT Y Coefficient 68 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F45 PFILT Y Coefficient 69 [7:0] PFILT Y Coefficient 69 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F46 PFILT Y Coefficient 70 [7:0] PFILT Y Coefficient 70 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F47 PFILT Y Coefficient 71 [7:0] PFILT Y Coefficient 71 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F48 PFILT Y Coefficient 72 [7:0] PFILT Y Coefficient 72 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F49 PFILT Y Coefficient 73 [7:0] PFILT Y Coefficient 73 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F4A PFILT Y Coefficient 74 [7:0] PFILT Y Coefficient 74 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F4B PFILT Y Coefficient 75 [7:0] PFILT Y Coefficient 75 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W

Rev. 0 | Page 131 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0F4C PFILT Y Coefficient 76 [7:0] PFILT Y Coefficient 76 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F4D PFILT Y Coefficient 77 [7:0] PFILT Y Coefficient 77 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F4E PFILT Y Coefficient 78 [7:0] PFILT Y Coefficient 78 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F4F PFILT Y Coefficient 79 [7:0] PFILT Y Coefficient 79 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F50 PFILT Y Coefficient 80 [7:0] PFILT Y Coefficient 80 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F51 PFILT Y Coefficient 81 [7:0] PFILT Y Coefficient 81 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F52 PFILT Y Coefficient 82 [7:0] PFILT Y Coefficient 82 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F53 PFILT Y Coefficient 83 [7:0] PFILT Y Coefficient 83 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F54 PFILT Y Coefficient 84 [7:0] PFILT Y Coefficient 84 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F55 PFILT Y Coefficient 85 [7:0] PFILT Y Coefficient 85 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F56 PFILT Y Coefficient 86 [7:0] PFILT Y Coefficient 86 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F57 PFILT Y Coefficient 87 [7:0] PFILT Y Coefficient 87 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F58 PFILT Y Coefficient 88 [7:0] PFILT Y Coefficient 88 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F59 PFILT Y Coefficient 89 [7:0] PFILT Y Coefficient 89 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F5A PFILT Y Coefficient 90 [7:0] PFILT Y Coefficient 90 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F5B PFILT Y Coefficient 91 [7:0] PFILT Y Coefficient 91 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F5C PFILT Y Coefficient 92 [7:0] PFILT Y Coefficient 92 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F5D PFILT Y Coefficient 93 [7:0] PFILT Y Coefficient 93 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F5E PFILT Y Coefficient 94 [7:0] PFILT Y Coefficient 94 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F5F PFILT Y Coefficient 95 [7:0] PFILT Y Coefficient 95 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F60 PFILT Y Coefficient 96 [7:0] PFILT Y Coefficient 96 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F61 PFILT Y Coefficient 97 [7:0] PFILT Y Coefficient 97 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F62 PFILT Y Coefficient 98 [7:0] PFILT Y Coefficient 98 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F63 PFILT Y Coefficient 99 [7:0] PFILT Y Coefficient 99 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F64 PFILT Y Coefficient 100 [7:0] PFILT Y Coefficient 100 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F65 PFILT Y Coefficient 101 [7:0] PFILT Y Coefficient 101 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F66 PFILT Y Coefficient 102 [7:0] PFILT Y Coefficient 102 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F67 PFILT Y Coefficient 103 [7:0] PFILT Y Coefficient 103 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F68 PFILT Y Coefficient 104 [7:0] PFILT Y Coefficient 104 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F69 PFILT Y Coefficient 105 [7:0] PFILT Y Coefficient 105 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F6A PFILT Y Coefficient 106 [7:0] PFILT Y Coefficient 106 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F6B PFILT Y Coefficient 107 [7:0] PFILT Y Coefficient 107 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W

Rev. 0 | Page 132 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x0F6C PFILT Y Coefficient 108 [7:0] PFILT Y Coefficient 108 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F6D PFILT Y Coefficient 109 [7:0] PFILT Y Coefficient 109 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F6E PFILT Y Coefficient 110 [7:0] PFILT Y Coefficient 110 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F6F PFILT Y Coefficient 111 [7:0] PFILT Y Coefficient 111 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F70 PFILT Y Coefficient 112 [7:0] PFILT Y Coefficient 112 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F71 PFILT Y Coefficient 113 [7:0] PFILT Y Coefficient 113 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F72 PFILT Y Coefficient 114 [7:0] PFILT Y Coefficient 114 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F73 PFILT Y Coefficient 115 [7:0] PFILT Y Coefficient 115 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F74 PFILT Y Coefficient 116 [7:0] PFILT Y Coefficient 116 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F75 PFILT Y Coefficient 117 [7:0] PFILT Y Coefficient 117 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F76 PFILT Y Coefficient 118 [7:0] PFILT Y Coefficient 118 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F77 PFILT Y Coefficient 119 [7:0] PFILT Y Coefficient 119 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F78 PFILT Y Coefficient 120 [7:0] PFILT Y Coefficient 120 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F79 PFILT Y Coefficient 121 [7:0] PFILT Y Coefficient 121 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F7A PFILT Y Coefficient 122 [7:0] PFILT Y Coefficient 122 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F7B PFILT Y Coefficient 123 [7:0] PFILT Y Coefficient 123 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F7C PFILT Y Coefficient 124 [7:0] PFILT Y Coefficient 124 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F7D PFILT Y Coefficient 125 [7:0] PFILT Y Coefficient 125 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F7E PFILT Y Coefficient 126 [7:0] PFILT Y Coefficient 126 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W 0x0F7F PFILT Y Coefficient 127 [7:0] PFILT Y Coefficient 127 Programmable Fi lter Y coefficients. Coefficients are only applied after the chip transfer bit is written. 0x0 R/W VREF/Analog Input Control Registers 0x0701 DC offset calibration control (local) [7:0] DC offset calibration control 0x06 R/W 0x06 Disable. 0x86 Enable. 0x18A6 VREF control [7:1] Reserved Reserved. 0x0 R

0 VREF control 0x0 R/W

0 Internal reference. 1 External reference. 0x18E3 External VCM buffer control 7 Reserved Reserved. 0x0 R

6 External VCM buffer 0x0 R/W

0 Disable. 1 Enable. [5:0] External VCM buffer [5:0] S ee the Input Common Mode section. 0x0 R/W

Rev. 0 | Page 133 of 136 Addr. Name Bits Bit Name Settings Description Reset Access 0x18E6 Temperature diode export [7:0] Temperature diode location select See the Temperature Diode section. 0x0 R/W 0x00 Central diode. VREF pin = high-Z. 0x01 Central diode. VREF pin = 1× diode voltage output. 0x02 Central diode. VREF pin = 20× diode voltage output. 0x03 Central diode. VREF pin = GND. 0x40 Channel A diode . VREF pin = high-Z. 0x41 Channel A diode. VREF pin = 1× diode voltage output. 0x42 Channel A diode. VREF pin = 20× diode voltage output. 0x43 Channel A di ode. VREF pin = GND. 0x50 Channel B diode. VREF pin = high-Z. 0x51 Channel B diode. VREF pin = 1× diode voltage output. 0x52 Channel B diode. VREF pin = 20× diode voltage output. 0x53 Channel B diode. VREF pin = GND. 0x1908 Analog input control (local) [7:3] Reserved Reserved. 0x0 R

2 Enable dc coupling 0x0 R/W

0 Analog input is optimized for ac coupling. 1 Analog input is optimized for dc coupling. [1:0] Reserved Reserved. 0x0 R 0x1910 Input full-scale control (local) [7:4] Reserved Reserved. 0x0 R [3:0] Input full-scale voltage Full-scale voltage setting. 0xD R/W 1000 1.13 V p-p differential. 1001 1.25 V p-p differential. 1101 1.7 V p-p differential. 1110 1.81 V p-p differential. 1111 1.93 V p-p differential. 0000 2.04 V p-p differential. 0x1A4C Buffer Control 1 (local) [7:6] Reserved Reserved. 0x0 R [5:0] Buffer Control 1 Input Buffer Main Current 1. See the Analog Input Buffer Controls and SFDR Optimization section. 0x19 R/W 00 0100 Buffer current set to 400 μA. 00 1001 Buffer current set to 500 μA. 01 1110 Buffer current set to 600 μA. 10 0011 Buffer current set to 700 μA. 10 1000 Buffer current set to 800 μA. 11 0010 Buffer current set to 1000 μA. 0x1A4D Buffer Control 2 (local) [7:6] Reserved Reserved. 0x0 R [5:0] Buffer Control 2 Input Buffer Main Current 2. See the Analog Input Buffer Controls and SFDR Optimization section. 0x19 R/W 00 0100 Buffer current set to 400 μA. 00 1001 Buffer current set to 500 μA. 01 1110 Buffer current set to 600 μA. 10 0011 Buffer current set to 700 μA. 10 1000 Buffer current set to 800 μA. 11 0010 Buffer current set to 1000 μA.

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

0.80 REF

0.34 REF

10.40 REF

Figure 134. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] registered trademarks are the property of their respective owners.