AD9204BCPZ-65

AD9204_17 AD | Alldatasheet

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10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

1.8 V Dual Analog-to-Digital Converter

Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

1.8 V analog supply operation

1.8 V to 3.3 V output supply SNR 61.3 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input Low power 30 mW per channel at 20 MSPS 63 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit DNL = ±0.11 LSB Serial port control options Scalable analog input: 1 V p-p to 2 V p-p differential Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment

APPLICATIONS

Multimode digital receivers GSM, EDGE, W-C D M A, LT E , CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Handheld scope meters Ultrasound Radar/LIDAR PET/SPECT imaging FUNCTIONAL BLOCK DIAGRAM VIN+A VIN–A VREF SENSE VCM RBIAS VIN–B VIN+B ORA D0A D9A DCOA DRVDD ORB D9B D0B DCOB SDIOGNDAVDD SCLK SPI PROGRAMMING DATA PDWN DFSCLK+ CLK– MODE CONTROLS DCS DUTY CYCLE STABILIZER SYNC DIVIDE

1 TO 8

Figure 1. PRODUCT HIGHLIGHTS 1. The AD9204 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. 2. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. 3. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/DATA timing and offset adjustments, and voltage reference modes. 4. The AD9204 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9251 and AD9258 14-bit ADCs, and the AD9231 12-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.

AD9204* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS

AD9204 Evaluation Board DOCUMENTATION Application Notes
AN-1142: Techniques for High Speed ADC PCB Layout
AN-742: Frequency Domain Response of Switched- Capacitor ADCs
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs
AN-877: Interfacing to High Speed ADCs via SPI
AN-878: High Speed ADC SPI Control Software
AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

AN-935: Designing an ADC Transformer-Coupled Front End Data Sheet
AD9204: 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet User Guides
UG-003: Evaluating the AD9650/AD9268/AD9258/ AD9251/AD9231/AD9204 Analog-to-Digital Converters TOOLS AND SIMULATIONS
Visual Analog
AD9204 IBIS Models
AD9204/AD9231/AD9251 S-Parameter Data REFERENCE MATERIALS Product Selection Guide
RF Source Booklet Technical Articles
Improve The Design Of Your Passive Wideband ADC Front-End Network
MS-2210: Designing Power Supplies for High Speed ADC DESIGN RESOURCES
AD9204 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints DISCUSSIONS View all AD9204 EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

Rev. A | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

9/2016—Rev. 0 to Rev. A 7/2009—Revision 0: Initial Version

Rev. A | Page 3 of 36 GENERAL DESCRIPTION The AD9204 is a monolithic, dual-channel, 1.8 V supply, 10-bit,

20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter

(ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at

80 MSPS data rates and to guarantee no missing codes over the

full operating temperature range. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported and output data can be multiplexed onto a single output bus. The AD9204 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).

Rev. A | Page 4 of 36 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V , maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter Temp AD9204-20/AD9204-40 AD9204-65 AD9204-80 Unit Min Typ Max Min Typ Max Min Typ Max RESOLUTION Full 10 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Guaranteed Gain Error1 Full +1.8 +1.8 +1.8 % FSR Differential Nonlinearity (DNL)2 Full ±0.30 ±0.30 ±0.30 LSB Integral Nonlinearity (INL)2 Full ±0.60 ±0.60 ±0.60 LSB MATCHING CHARACTERISTICS Gain Error1 25°C ±0.3 ±0.3 ±0.3 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Load Regulation Error at 1.0 mA Full 2 2 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.06 0.08 0.08 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 2 2 V p-p Input Capacitance3 Full 6 6 6 pF Input Common-Mode Voltage Full 0.9 0.9 0.9 V REFERENCE INPUT RESISTANCE Full 7.5 7.5 7.5 kΩ POWER SUPPLIES Supply Voltage Supply Current POWER CONSUMPTION DC Input Full 59.5/82.1 108 125 mW Sine Wave Input2 (DRVDD = 3.3 V) Full 76.7/111 150.8 177 mW Standby Power4 Full 37/37 37 37 mW Power-Down Power Full 2.2 2.2 2.2 mW 1 Measured with a 1.0 V external reference. 2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input, the CLK active.

Rev. A | Page 5 of 36 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V , maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. Parameter1 Temp AD9204-20/AD9204-40 AD9204-65 AD9204-80 Unit Min Typ Max Min Typ Max Min Typ Max SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 61.7 61.5 61.3 dBFS fIN = 30.5 MHz 25°C 61.6 61.4 61.3 dBFS Full 61.0 60.5 dBFS fIN = 70 MHz 25°C 61.6 61.4 61.3 dBFS Full 60.4 dBFS fIN = 200 MHz 25°C 61.0 61.0 dBFS SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 9.7 MHz 25°C 61.5 61.2 61.1 dBFS fIN = 30.5 MHz 25°C 61.5 61.2 61.1 dBFS Full 60.1 59.7 dBFS fIN = 70 MHz 25°C 61.5 61.2 61.1 dBFS Full 59.5 dBFS fIN = 200 MHz 25°C 60 60 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 9.9 9.8 9.8 Bits fIN = 30.5 MHz 25°C 9.9 9.8 9.8 Bits fIN = 70 MHz 25°C 9.9 9.8 9.8 Bits fIN = 200 MHz 25°C 9.6 9.6 Bits WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −81 −78 −78 dBc fIN = 30.5 MHz 25°C −81 −78 −78 dBc Full −65 −64 dBc fIN = 70 MHz 25°C −82 −78 −78 dBc Full −64 dBc fIN = 200 MHz 25°C −73 −73 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 78 75 75 dBc fIN = 30.5 MHz 25°C 78 75 75 dBc Full 65 64 dBc fIN = 70 MHz 25°C 78 75 75 dBc Full 64 dBc fIN = 200 MHz 25°C 73 73 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −82 −80 −80 dBc fIN = 30.5 MHz 25°C −82 −80 −80 dBc Full −71 −70 dBc fIN = 70 MHz 25°C −82 −80 −80 dBc Full −70 dBc fIN = 200 MHz 25°C −80 −80 dBc TWO-TONE SFDR fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 78 78 dBc CROSSTALK2 Full −100 −100 −100 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

Rev. A | Page 6 of 36 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 1.8 V , maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. Parameter Temp AD9204-20/AD9204-40/AD9204-65/AD9204-80 Unit Min Typ Max DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.2 3.6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 0.2 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 8 10 12 kΩ Input Capacitance Full 4 pF LOGIC INPUTS (SCLK/DFS, SYNC, PDWN)1 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −50 −75 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 30 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (CSB)2 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full +40 +135 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF LOGIC INPUTS (SDIO/DCS)2 High Level Input Voltage Full 1.2 DRVDD + 0.3 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full +40 +130 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, IOH = 50 μA Full 3.29 V High Level Output Voltage, IOH = 0.5 mA Full 3.25 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V DRVDD = 1.8 V High Level Output Voltage, IOH = 50 μA Full 1.79 V High Level Output Voltage, IOH = 0.5 mA Full 1.75 V Low Level Output Voltage, IOL = 1.6 mA Full 0.2 V Low Level Output Voltage, IOL = 50 μA Full 0.05 V 1 Internal 30 kΩ pull-down. 2 Internal 30 kΩ pull-up.

Figure 4. SYNC Input Timing Requirements

The exposed paddle is the only ground connection for the chip. maximizes the thermal capability of the package. Table 7. Thermal Resistance 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). power planes reduces the θJA.

THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND

Figure 5. Pin Configuration Table 8. Pin Function Description 0 GND Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND. 1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. 3 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. 10, 19, 28, 37 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 11 to 18, 20, 21 D0B to D9B Channel B Digital Outputs. D9B = MSB. 22 ORB Channel B Out-of-Range Digital Output. 23 DCOB Channel B Data Clock Digital Output. 24 DCOA Channel A Data Clock Digital Output. 32 to 36, 38 to 42 D0A to D9A Channel A Digital Outputs. D9A = MSB. 43 ORA Channel A Out-of-Range Digital Output. Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal pull-up in non-SPI (DCS) mode. 45 SCLK/DFS SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down. DFS high = twos complement output. DFS low = offset binary output. 46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up. high. 30 kΩ internal pull-down. 48 PDWN Digital Input. 30 kΩ internal pull-down. PDWN high = power-down device. PDWN low = run device, normal operation.

Rev. A | Page 11 of 36 Pin No. Mnemonic Description 49, 50, 53, 54, 59, 60, 63, 64 AVDD 1.8 V Analog Supply Pins. 51, 52 VIN+A, VIN−A Channel A Analog Inputs. 55 VREF Voltage Reference Input/Output. 56 SENSE Reference Mode Selection. 57 VCM Analog output voltage at midsupply to set common mode of the analog inputs. 58 RBIAS Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. 61, 62 VIN−B, VIN+B Channel B Analog Inputs.

disabled, unless otherwise noted. Figure 12. AD9204-80 SNR/SFDR vs. Input Frequency (AIN) with

2 V p-p Full Scale

Figure 13. AD9204-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz Figure 14. AD9204-80 DNL with fIN = 9.7 MHz Figure 15. AD9204-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7MHz Figure 16. AD9204-80 Grounded Input Histogram Figure 17. AD9204-80 INL with fIN = 9.7 MHz

disabled, unless otherwise noted. Figure 18. AD9204-65 Single-Tone FFT with fIN = 9.7 MHz Figure 19. AD9204-65 Single-Tone FFT with fIN = 70.3 MHz Figure 20. AD9204-65 Single-Tone FFT with fIN = 30.5 MHz Figure 21. AD9204-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz Figure 22. AD9204-65 SNR/SFDR vs. Input Frequency (AIN) with

300 MHz analog input is permitted but occurs at the

expense of increased ADC noise and distortion. used for I input data and the other is used for Q input data. timing among multiple channels or multiple devices. using a 3-bit SPI-compatible serial interface. The AD9204 architecture consists of a multistage, pipelined ADC. combined into a final 10-bit result in the digital correction logic. of flash errors. The last stage simply consists of a flash ADC. output buffers go into a high impedance state. signal-dependent errors and achieve optimum performance. Figure 38. Switched-Capacitor Input Circuit

and should not exceed that supply voltage. proportionally shorter wake-up times. may affect converter performance. or large fanouts may require external buffers or latches. in the external pin mode (see Table 12). binary, twos complement, or gray code when using the SPI control. Table 12. SCLK/DFS Mode Selection (External Pin Mode) output disable (OEB) bit (Bit 4) in Register 0x14. delay (tPD) after the rising edge of the clock signal. transients can degrade converter dynamic performance. clock rates below 3 MSPS, dynamic performance can degrade. Figure 3 for a graphical timing description. Table 13. Output Data Format

Rev. A | Page 27 of 36 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9204 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9204 is included. Various output test options are also provided to place predictable values on the outputs of the AD9204. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9204 signal path. Perform the BIST test after a reset to ensure that the device is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. Once completed, the BIST compares the signature results with a predetermined value. If the signatures match, the BIST sets Bit 0 of Register 0x24, signifying that the test passed. If the BIST test failed, Bit 0 of Register 0x24 is cleared. The outputs are connected during this test so that the PN sequence can be observed as it runs. Writing 0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN sequence can be continued from the last value by writing a 0 in Bit 2 of Register 0x0E. However, if the PN sequence is not reset, the signature calculation will not equal the predetermined value at the end of the test. At that point, the user must rely on verifying the output data. OUTPUT TEST MODES The output test options are described in Table 17 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

Rev. A | Page 28 of 36 CHANNEL/CHIP SYNCHRONIZATION The AD9204 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple devices, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. Drive the SYNC input using a single-ended CMOS-type signal.

Note, Interfacing to High Speed ADCs via SPI. low control that enables or disables the read and write cycles. Table 14. Serial Port Interface Pins serial interface reads and writes. on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. by the W0 and W1 bits, as shown in Figure 58. to an output at the appropriate point in the serial frame. at the appropriate point in the serial frame. Figure 58. Serial Port Interface Timing Diagram

tioning at the converter inputs during critical sampling periods. the strappable functions supported on the AD9204. select to AVDD, which disables the serial port interface. Table 15. Mode Selection Table 16. Features Accessible Using the SPI

Rev. A | Page 31 of 36 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 17) has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x05 and Address 0xFF); the program registers (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 and Address 0x101). Table 17 documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the VREF register, has a hexadecimal default value of 0xE0. This means that Bits[7:5] = 1, and the remaining Bits[4:0] = 0. This setting is the default reference selection setting. The default value uses a 2.0 V p-p reference. For more information on this function and others, see the AN-812 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to register 0xFF. The remaining registers, Register 0x100 and Register 0x101, are documented in the Memory Map Register Descriptions section following Table 17. OPEN LOCATIONS All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. DEFAULT VALUES After the AD9204 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). Logic Levels An explanation of logic level terminology follows:  “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ”  “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Transfer Register Map Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect device operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simulta- neously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. Channel-Specific Registers Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in the memory map register table as local. These local registers and bits can be accessed by setting the appropriate Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the device returns the value for Channel A. Registers and bits designated as global in the memory map register table affect the entire device or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits.

Rev. A | Page 32 of 36 Memory Map Register Table All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Comments Chip Configuration Registers 0x00 SPI port configuration (global)

0 LSB

LSB first 0 0x18 The nibbles are mirrored so that LSB- or MSB-first mode registers correctly, regard- less of shift mode 0x01 Chip ID (global) 8-bit chip ID bits [7:0] AD9204 = 0x25 Unique chip ID differentiates devices; read only 0x02 Chip grade (global) Open Speed grade ID 6:4

20 MSPS = 000

40 MSPS = 001

65 MSPS = 010

80 MSPS = 011

devices; read only Device Index and Transfer Registers 0x05 Channel index Open Open Open Open Open Open ADC B default ADC A default 0xFF Bits are set to determine which device on-chip receives the next write command; the default is all devices on-chip 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave Program Registers (May or May Not Be Indexed by Device Index) 0x08 Modes External power- down enable (local) External pin function 0x00 full power-down 0x01 standby (local) Open Open 00 = chip run 01 = full power- down 10 = standby 11 = chip wide digital reset (local) 0x80 Determines various generic modes of chip operation 0x09 Clock (global) Open Open Open Open Open Duty cycle stabilize 0x00 0x0B Clock divide (global) Open Clock divider [2:0] Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 The divide ratio is the value plus 1

Rev. A | Page 33 of 36 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Comments 0x0D Test mode (local) User test mode (local) 00 = single 01 = alternate 10 = single once 11 = alternate once Reset PN long gen Reset PN short gen Output test mode [3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 0x00 When set, the test data is placed on the output pins in place of normal data 0x0E BIST enable Open Open BIST INIT Open BIST enable 0x00 When Bit 0 is set, the BIST function is initiated 0x10 Offset adjust (local) 8-bit device offset adjustment [7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) 0x00 Device offset trim 0x14 Output mode 00 = 3.3 V CMOS 10 = 1.8 V CMOS Output mux enable (interleaved) Output disable (local) Open Output invert (local) 00 = offset binary 01 = twos complement 10 = gray code 11 = offset binary (local) 0x00 Configures the outputs and the format of the data 0x15 OUTPUT_ADJUST 3.3 V DCO drive strength 00 = 1 stripe (default) 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes

1.8 V DCO

00 = 1 stripe 01 = 2 stripes 10 = 3 stripes (default) 11 = 4 stripes

3.3 V data

00 = 1 stripe (default) 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes

1.8 V data

00 = 1 stripe 01 = 2 stripes 10 = 3 stripes (default) 11 = 4 stripes 0x22 Determines CMOS output drive strength properties 0x16 OUTPUT_PHASE DCO output polarity 0 = normal 1 = inverted (local) Input clock phase adjust [2:0] (Value is number of input clock cycles of phase delay) 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x00 On devices that utilize global clock divide, determines which phase of the divider output supplies the output clock; internal latching is unaffected 0x17 OUTPUT_DELAY Enable DCO delay Enable data delay DCO/Data delay[2:0] 000 = 0.56 ns 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x00 This sets the fine output delay of the output clock but does not change internal timing 0x18 VREF Reserved =11 Internal VREF adjustment [2:0] 000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.60 V p-p 100 = 2.0 V p-p 0xE0 Selects and/or adjusts the VREF 0x19 USER_PATT1_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB 0x1A USER_PATT1_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB 0x1B USER_PATT2_LSB B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB

Rev. A | Page 34 of 36 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Comments 0x1C USER_PATT2_MSB B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB 0x24 MISR_LSB Open Open Open Open Open Open Open B0 0x00 Least significant byte of MISR; read only 0x2A Features Open Open Open Open Open Open Open OR output enable (local) 0x01 Disables the OR pin for the indexed channel 0x2E Output assign Open Open Open Open Open Open Open 0 = ADC A 1 = ADC B (local) Ch A = 0x00 Ch B = 0x01 Assign an ADC to an output channel Digital Feature Control 0x10 Sync control (global) Open Open Open Open Open Clock divider next sync only Clock divider sync enable Master sync enable 0x01 0x10 USR2 Enable OEB Pin 47 (local) Open Open Open Enable GCLK detect Run GCLK Open Disable SDIO pull- down 0x88 Enables internal oscillator for clock rates < 5 MHz MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-812 Application Note, Interfacing to High Speed ADCs via SPI. Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only If the master sync enable bit (Address 0x100, Bit 0) and the clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 and Bit 0 are high and the device is operating in continuous sync mode as long as Bit 2 of the sync control is low. Bit 0—Master Sync Enable Bit 0 must be high to enable any of the sync functions. USR2 (Register 0x101) Bit 7—Enable OEB Pin 47 Normally set high, this bit allows Pin 47 to function as the output enable. If it is set low, it disables Pin 47. Bit 3—Enable GCLK Detect Normally set high, this bit enables a circuit that detects encode rates below about 5 MSPS. When a low encode rate is detected, an internal oscillator, GCLK, is enabled, ensuring the proper operation of several circuits. If set low, the detector is disabled. Bit 2—Run GCLK This bit enables the GCLK oscillator. For some applications with encode rates below 10 MSPS, it may be preferable to set this bit high to supersede the GCLK detector. Bit 0—Disable SDIO Pull-Down This bit can be set high to disable the internal 30 kΩ pull-down on the SDIO pin, which can limit the loading when many devices are connected to the SPI bus.

Rev. A | Page 35 of 36 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9204 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9204, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the digital output supply (DRVDD). If a common 1.8 V AVDD and DRVDD supply must be used, the AVDD and DRVDD domains must be isolated with a ferrite bead or filter choke and separate decoupling capacitors. Several different decoupling capacitors can cover both high and low frequencies. Locate these capacitors close to the point of entry at the PCB level and close to the pins of the device, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9204. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. Exposed Paddle Thermal Heat Sink Recommendations The exposed paddle (Pin 0) is the only ground connection for the AD9204 and, therefore, it must be connected to analog ground (AGND) on the customer PCB. To achieve the best electrical and thermal performance, mate an exposed (no solder mask) continuous copper plane on the PCB to the AD9204 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. Fill or plug these vias with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 42. RBIAS The AD9204 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. Reference Decoupling Externally decouple the VREF pin to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9204 to keep these signals from transitioning at the converter inputs during critical sampling periods.

0.25 MIN

0.20 REF

7.50 REF

0.05 MAX

0.02 NOM

Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 2 The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND. registered trademarks are the property of their respective owners.

Summary

1.8 V Dual Analog-to-Digital Converter Rev. A

Description