AD9203ARUZRL71

AD9203ARUZRL7 AD | Alldatasheet

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Technical content

10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter AD9203 Rev. B Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

CMOS 10-Bit, 40 MSPS sampling A/D converter Power dissipation: 74 mW (3 V supply, 40 MSPS) 17 mW (3 V supply, 5 MSPS) Operation between 2.7 V and 3.6 V supply Differential nonlinearity: −0.25 LSB Power-down (standby) mode, 0.65 mW ENOB: 9.55 @ fIN = 20 MHz Out-of-range indicator Adjustable on-chip voltage reference IF undersampling up to fIN = 130 MHz Input range: 1 V to 2 V p-p differential or single-ended Adjustable power consumption Internal clamp circuit

APPLICATIONS

IF and baseband communications Cable modems Medical ultrasound FUNCTIONAL BLOCK DIAGRAM 00573-001 SHA GAIN A/D D/A SHA GAIN A/D D/A A/D CORRECTION LOGIC AD9203 OUTPUT BUFFERS 0.5V BANDGAP REFERENCE CLK AVDD DRVDD STBY 3-STATE OTR D9 (MSB) D0 (LSB) DRVSSDFSPWRCONAVSS CLAMP CLAMPIN AINP AINN REFTF REFBF VREF REFSENSE Figure 1. GENERAL DESCRIPTION The AD9203 is a monolithic low power, single supply, 10-bit,

40 MSPS analog-to-digital converter, with an on-chip voltage

reference. The AD9203 uses a multistage differential pipeline architecture and guarantees no missing codes over the full operating temperature range. Its input range may be adjusted between 1 V and 2 V p-p. The AD9203 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of an application. An external resistor can be used to reduce power consumption when operating at lower sampling rates. This yields power savings for users who do not require the maximum sample rate. This feature is especially useful at sample rates far below 40 MSPS. Excellent performance is still achieved at reduced power. For example, 9.7 ENOB performance may be realized with only 17 mW of power, using a 5 MHz clock. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary or twos complementary output format by using the DFS pin. An out-of-range signal (OTR) indicates an overflow condition that can be used with the most significant bit to determine over- or underrange. The AD9203 can operate with a supply range from 2.7 V to 3.6 V, an attractive option for low power operation in high-speed portable applications. The AD9203 is specified over industrial (−40°C to +85°C) temperature ranges and is available in a 28-lead TSSOP package. PRODUCT HIGHLIGHTS Low Power—The AD9203 consumes 74 mW on a 3 V supply operating at 40 MSPS. In standby mode, power is reduced to 0.65 mW. High Performance—Maintains better than 9.55 ENOB at 40 MSPS input signal from dc to Nyquist. Very Small Package—The AD9203 is available in a 28-lead TSSOP. Programmable Power—The AD9203 power can be further reduced by using an external resistor at lower sample rates. Built-In Clamp Function—Allows dc restoration of video signals.

Rev. B | Page 2 of 28 TABLE OF CONTENTS

REVISION HISTORY

8/04—Data sheet changed from Rev. A to Rev. B 4/01—Data sheet changed from Rev. 0 to Rev. A 7/99—Revision 0: Initial Version

Rev. B | Page 3 of 28 SPECIFICATIONS AVDD = 3 V , DRVDD = 3 V , FS = 40 MSPS, input span from 0.5 V to 2.5 V , internal 1 V reference, PWRCON = AVDD, 50% clock duty cycle, TMIN to TMAX unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Conditions RESOLUTION 10 Bits MAX CONVERSION RATE FS 40 MSPS PIPELINE DELAY 5.5 Clock Cycles DC ACCURACY Differential Nonlinearity DNL ± 0.25 ± 0.7 LSB Integral Nonlinearity INL ± 0.65 ± 1.4 LSB Offset Error EZS ± 0.6 ± 2.8 % FSR Gain Error EFS ± 0.7 ± 4.0 % FSR ANALOG INPUT Input Voltage Range AIN 1 2 V p-p Input Capacitance CIN 1.4 pF Aperture Delay TAP 2.0 ns Aperture Uncertainty (Jitter) TAJ 1.2 ps rms Input Bandwidth (–3 dB) BW 390 MHz Input Referred Noise 0.3 mV Switched, Single-Ended INTERNAL REFERENCE Output Voltage (0.5 V Mode) VREF 0.5 V REFSENSE = VREF Output Voltage (1 V Mode) VREF 1 V REFSENSE = GND Output Voltage Tolerance (1 V Mode) ± 5 ± 30 mV Load Regulation 0.65 1.2 mV 1.0 mA Load POWER SUPPLY Operating Voltage AVDD 2.7 3.0 3.6 V DRVDD 2.7 3.0 3.6 V Analog Supply Current IAVDD 20.1 22.0 mA Digital Supply Current IDRVDD 4.4 6.0 mA fIN= 4.8 MHz, Output Bus Load = 10pF 9.5 14.0 mA fIN= 20 MHz, Output Bus Load = 20 pF Power Consumption 74 84.0 mW fIN= 4.8 MHz, Output Bus Load = 10pF 88.8 108.0 mW fIN= 20 MHz, Output Bus Load = 20 pF Power-Down PD 0.65 1.2 mW Power Supply Rejection Ratio PSRR 0.04 ± 0.25 % FS DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion1 SINAD f = 4.8 MHz 59.7 dB f = 20 MHz 57.2 59.3 dB Effective Bits ENOB f = 4.8 MHz1 9.6 Bits f = 20 MHz 9.2 9.55 Bits Signal-to-Noise Ratio SNR f = 4.8 MHz1 60.0 dB f = 20 MHz 57.5 59.5 dB Total Harmonic Distortion THD f = 4.8MHz −76.0 dB f = 20 MHz −74.0 −65.0 dB Spurious-Free Dynamic Range SFDR f = 4.8 MHz1 80 dB f = 20 MHz 67.8 78 dB

1 Differential Input (2 V p-p). 2 The AD9203 will convert at clock rates as low as 20 kHz. Figure 2. Timing Diagram

Rev. B | Page 5 of 28 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter With Respect to Min Max Unit AVDD AVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V AVSS DRVSS –0.3 +0.3 V AVDD DRVDD –3.9 +3.9 V REFCOM AVSS –0.3 +0.3 V CLK AVSS –0.3 AVDD + 0.3 V Digital Outputs DRVSS –0.3 DRVDD + 0.3 V AINP AINN AVSS –0.3 AVDD + 0.3 V VREF AVSS –0.3 AVDD + 0.3 V REFSENSE AVSS –0.3 AVDD + 0.3 V REFTF, REFBF AVSS –0.3 AVDD + 0.3 V STBY AVSS –0.3 AVDD + 0.3 V CLAMP AVSS –0.3 AVDD + 0.3 V CLAMPIN AVSS –0.3 AVDD + 0.3 V PWRCON AVSS –0.3 AVDD + 0.3 V DFS AVSS –0.3 AVDD + 0.3 V 3-STATE AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Storage Temperature –65 +150 °C Lead Temperature (10 s) 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS 28-Lead TSSOP JA = 97.9°C/W JC = 14.0°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 3. Pin Configuration Table 3. Pin Function Descriptions 3 D0 Bit 0, Least Significant Bit. 12 D9 Bit 9, Most Significant Bit. 13 OTR Out-of-Range Indicator. 14 DFS Data Format Select HI: Twos Complement; LO: Straight Binary. 16 3-STATE HI: High Impedance State Output; LO: Active Digital Output Drives. 17 STBY HI: Power-Down Mode; LO: Normal Operation. 18 REFSENSE Reference Select. 19 CLAMP HI: Enable Clamp; LO: Open Clamp. 20 CLAMPIN Clamp Signal Input. 21 PWRCON Power Control Input. 22 REFTF Top Reference Decoupling. 24 REFBF Bottom Reference Decoupling. 25 AINP Noninverting Analog Input. 26 AINN Inverting Analog Input.

Rev. B | Page 7 of 28 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity Error (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes respectively, must be present over all operating ranges. Signal-To-Noise and Distortion (S/N+D, SINAD) Ratio S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD – 1.76)/6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Signal-To-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference in dB between the rms amplitude of the input signal and the peak spurious signal. Offset Error First transition should occur for an analog value 1/2 LSB above negative full scale. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur for an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Aperture Jitter Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. Aperture Delay Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. Pipeline Delay (Latency) The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided on every rising edge.

Figure 10. Grounded Input Histogram Figure 11. SNR and THD vs. Sample Rate (fIN = 20 MHz) Figure 12. Typical INL Performance Figure 13. Typical DNL Performance Figure 14. Single Tone Frequency Domain Performance (Input Frequency =

10 MHz, Sample Rate = 40 MSPS 2 V Differential Input, 8192 Point FFT)

Figure 15. SNR and THD vs. Power Supply

the remaining stages operate on preceding samples. separate amplifiers by eliminating one amplifier in the pipeline. performance. Sampling occurs on the falling edge of the clock. keeps the signal peaks within the power supply rails. accomplished by connecting the CLAMP pin to AINN or AINP . Power Control section for more information. Table 4. Modes

1 V Differential Figure 28 with VREF Connected to

2 V Differential Figure 28 with REFSENSE Connected to

1 V Single-Ended Figure 20 Video and Applications Requiring Clamping Require Single-Ended Inputs

2 V Single-Ended Figure 19 Video and Applications Requiring Clamping Require Single-Ended Inputs

Figure 31. THD and SNR vs. Clock Duty Cycle Table 5. Power Programming Resistance conversion rate, but do need even lower power consumption. programmed power and performance. with extremely low power consumption. 5 V analog power line through an AD3307-3 linear regulator. maximum rated values listed on the Specifications page. both tCH and tCL are satisfied. See Figure 31 for dynamics vs. input, analog input signal, and A/D aperture jitter specification. Undersampling applications are particularly sensitive to jitter. aperture jitter may affect the dynamic range of the AD9203. should be retimed by the original clock at the last step. the data to a twos complement format.

2 V spans. Refer to Figure 39. Figure 38. Evaluation Board Connection

56 U6 1 AS W6

Figure 39. Evaluation Board (Rev. C)

12 P1 38P137

Figure 40. Evaluation Board (Rev. C)

1.20 MAX

6.40 BSC

Figure 47. 28-Lead Thin Shrink Small Outline Package

Rev. B | Page 26 of 28 NOTES

Rev. B | Page 27 of 28 NOTES

Rev. B | Page 28 of 28 NOTES © 2004 A nalog De vices, Inc. All rig hts reserv ed. Trademarks an d registered tra demarks are the prop erty of their respective owners . C00573–0–8/04(B)