AD9200SSOP-EVAL

AD9200 AD | Alldatasheet

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Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter FUNCTIONAL BLOCK DIAGRAM A/D A/DAIN REFTF REFBF REFSENSE OTR (MSB) (LSB) VREF DRVDDAVDDCLK DRVSS AD9200 SHA SHA SHA GAIN SHA GAIN GAIN D/A A/D D/AA/D D/A CORRECTION LOGIC OUTPUT BUFFERS REFTS AVSS REFBS THREE- STATE MODE STBY CLAMP CLAMP IN SHA GAIN A/D D/A

FEATURES

CMOS 10-Bit, 20 MSPS Sampling A/D Converter Pin-Compatible with AD876 Power Dissipation: 80 mW (3 V Supply) Operation Between 2.7 V and 5.5 V Supply Differential Nonlinearity: 0.5 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp Function (DC Restore) Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz PRODUCT DESCRIPTION The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9200 uses a multistage differential pipeline architecture at 20 MSPS data rates and guarantees no missing codes over the full operating temperature range. The input of the AD9200 has been designed to ease the devel- opment of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. The sample-and-hold (SHA) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in suc- cessive channels and sampling single-channel inputs at frequen- cies up to and beyond the Nyquist rate. AC coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit (AD9200ARS, AD9200KST). The dynamic per- formance is excellent. The AD9200 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an over- flow condition which can be used with the most significant bit to determine low or high overflow. The AD9200 can operate with supply range from 2.7 V to

5.5 V, ideally suiting it for low power operation in high speed

portable applications. The AD9200 is specified over the industrial (–40 °C to +85°C) and commercial (0°C to +70°C) temperature ranges. PRODUCT HIGHLIGHTS Low Power The AD9200 consumes 80 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW. Very Small Package The AD9200 is available in both a 28-lead SSOP and 48-lead LQFP packages. Pin Compatible with AD876 The AD9200 is pin compatible with the AD876, allowing older designs to migrate to lower supply voltages.

300 MHz On-Board Sample-and-Hold

The versatile SHA input can be configured for either single- ended or differential inputs. Out-of-Range Indicator The OTR output bit indicates when the input signal is beyond the AD9200’s input range. Built-In Clamp Function Allows dc restoration of video signals with AD9200ARS and AD9200KST.

–2– REV. E AD9200–SPECIFICATIONS (AVDD = +3 V, DRVDD = +3 V, F S = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V, External Reference, T MIN to TMAX unless otherwise noted) Parameter Symbol Min Typ Max Units Condition RESOLUTION 10 Bits CONVERSION RATE F S 20 MHz DC ACCURACY Differential Nonlinearity DNL – 0.5 – 1 LSB REFTS = 2.5 V, REFBS = 0.5 V Integral Nonlinearity INL – 0.75 – 2 LSB Offset Error E ZS 0.4 1.2 % FSR Gain Error E FS 1.4 3.5 % FSR REFERENCE VOLTAGES Top Reference Voltage REFTS 1 AVDD V Bottom Reference Voltage REFBS GND AVDD – 1 V Differential Reference Voltage 2 V p-p Reference Input Resistance 1 10 k W REFTS, REFBS: MODE = AVDD 4.2 k W Between REFTF and REFBF: MODE = AVSS ANALOG INPUT Input Voltage Range AIN REFBS REFTS V REFBS Min = GND: REFTS Max = AVDD Input Capacitance C IN 1 pF Switched Aperture Delay t AP 4n s Aperture Uncertainty (Jitter) t AJ 2p s Input Bandwidth (–3 dB) BW Full Power (0 dB) 300 MHz DC Leakage Current 23 mA Input = – FS INTERNAL REFERENCE Output Voltage (1 V Mode) VREF 1 V REFSENSE = VREF Output Voltage Tolerance (1 V Mode) – 10 – 25 mV Output Voltage (2 V Mode) VREF 2 V REFSENSE = GND Load Regulation (1 V Mode) 0.5 2 mV 1 mA Load Current POWER SUPPLY Operating Voltage AVDD 2.7 3 5.5 V DRVDD 2.7 3 5.5 V Supply Current IAVDD 26.6 33.3 mA AVDD = 3 V, MODE = AVSS Power Consumption P D 80 100 mW AVDD = DRVDD = 3 V, MODE = AVSS Power-Down 4 mW STBY = AVDD, MODE and CLOCK = AVSS Gain Error Power Supply Rejection PSRR 1 % FS DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz 54.5 57 dB f = 10 MHz 54 dB Effective Bits f = 3.58 MHz 9.1 Bits f = 10 MHz 8.6 Bits Signal-to-Noise SNR f = 3.58 MHz 55 57 dB f = 10 MHz 56 dB Total Harmonic Distortion THD f = 3.58 MHz –59 –66 dB f = 10 MHz –58 dB Spurious Free Dynamic Range SFDR f = 3.58 MHz –61 –69 dB f = 10 MHz –61 dB Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.1 Degree NTSC 40 IRE Mod Ramp Differential Gain DG 0.05 %

Parameter Symbol Min Typ Max Units Condition DIGITAL INPUTS High Input Voltage V IH 2.4 V Low Input Voltage V IL 0.3 V DIGITAL OUTPUTS High-Z Leakage I OZ –10 +10 mA Output = GND to VDD Data Valid Delay t OD 25 ns C L = 20 pF Data Enable Delay t DEN 25 ns Data High-Z Delay t DHZ 13 ns LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 mA) V OH +2.95 V High Level Output Voltage (IOH = 0.5 mA) V OH +2.80 V Low Level Output Voltage (IOL = 1.6 mA) V OL +0.4 V Low Level Output Voltage (IOL = 50 mA) V OL +0.05 V LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 mA) V OH +4.5 V High Level Output Voltage (IOH = 0.5 mA) V OH +2.4 V Low Level Output Voltage (IOL = 1.6 mA) V OL +0.4 V Low Level Output Voltage (IOL = 50 mA) V OL +0.1 V CLOCKING Clock Pulsewidth High t CH 22.5 ns Clock Pulsewidth Low t CL 22.5 ns Pipeline Latency 3 Cycles CLAMP2 Clamp Error Voltage E OC – 20 – 40 mV CLAMPIN = 0.5 V–2.7 V, R IN = 10 W Clamp Pulsewidth t CPW 2 msC IN = 1 mF (Period = 63.5 ms) NOTES 1See Figures 1a and 1b. 2Available only in AD9200ARS and AD9200KST. Specifications subject to change without notice. AD9200REFTS REFBS MODE AV DD 10kV 10kV 0.4 3 VDD AD9200 REFTS REFBF MODE REFTF REFBS 4.2kV Figure 1a. Figure 1b. AD9200 –3–REV. E

ratings for extended periods may effect device reliability. *RS = Shrink Small Outline; ST = Thin Quad Flatpack. Figure 2. Equivalent Circuits accumulate on the human body and test equipment and can discharge without detection. precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. E PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS SSOP LQFP Pin No. Pin No. Name Description 1 44 AVSS Analog Ground 2 45 DRVDD Digital Driver Supply 3 1 D0 Bit 0, Least Significant Bit 4 2 D1 Bit 1 5 3 D2 Bit 2 6 4 D3 Bit 3 7 5 D4 Bit 4 8 8 D5 Bit 5 9 9 D6 Bit 6 10 10 D7 Bit 7 11 11 D8 Bit 8 12 12 D9 Bit 9, Most Significant Bit 13 16 OTR Out-of-Range Indicator 14 17 DRVSS Digital Ground 15 22 CLK Clock Input 16 23 THREE-STATE HI: High Impedance State. LO: Normal Operation 17 24 STBY HI: Power-Down Mode. LO: Normal Operation 18 26 REFSENSE Reference Select 19 27 CLAMP HI: Enable Clamp Mode. LO: No Clamp 20 28 CLAMPIN Clamp Reference Input 21 29 REFTS Top Reference 22 30 REFTF Top Reference Decoupling 23 32 MODE Mode Select 24 34 REFBF Bottom Reference Decoupling 25 35 REFBS Bottom Reference 26 38 VREF Internal Reference Output 27 39 AIN Analog Input 28 42 AVDD Analog Supply 28-Lead Shrink Small Outline (SSOP) TOP VIEW (Not to Scale) AD9200 AVSS REFBS VREF AIN AVDD DRVDD REFTF MODE REFBFD2 D7 CLAMP CLAMPIN REFTS OTR DRVSS REFSENSE CLK THREE-STATE STBY 48-Lead Plastic Thin Quad Flatpack (LQFP) AVDD VREF NC NC NC AVSS NC NC AIN NC 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 39 38 3743 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) NC REFBS REFBF NC MODE NC REFTF NC NC NC NC OTR DRVSS NC NC NC NC = NO CONNECT REFTS CLAMPIN CLAMP REFSENSE NC NC CLK THREE-STATE NC AD9200 STBY D9 NC DRVDD

1 V Mode the internal reference may be set to 1 V by connect-

ing REFSENSE and VREF together.

2 V Mode the internal reference my be set to 2 V by connecting

is attained by tying REFSENSE to VDD. Top/Bottom Mode sets the input range between two points. Mode is enabled by tying the MODE pin to AVDD. to the CLAMP pin. MODE pin is tied to AVDD. and REFBS together to be used as the second input. Figure 15. AD9200 Equivalent Functional Input Circuit ground to generate a potential anywhere between 1 V and 2 V. the user can select an input configuration to match drive circuit. amplitude of a full-scale signal. Table I outlines pin configurations to match user requirements.

–10– REV. E SHA 10kV 10kV 10kV A/D CORE 4.2kV TOTAL REFTS REFBS 10mF 0.1mFREFTF REFBF 0.1mF AIN +F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF –F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF 0.1mF MODE (AVDD) +FS –FS AD9200 10kV a. Top/Bottom Mode V MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO MODE INTERNAL REF AVDD/2SHA 10kV 10kV 10kV A/D CORE 4.2kV TOTAL 10mF 0.1mFREFTF REFBF 0.1mF AIN 0.1mF AD9200 10kV REFTS REFBS AVDD/2 c. Differential Mode AVSS REFSENSE VREF (1V) AD9200 0.1mF 1.0 mF d. 1 V Reference 0.01mF 1.0 mFA1 10kV 10kV AVSS REFSENSE VREF (2V) AD9200 e. 2 V Reference AVSS REFSENSE VREF (= 1 + RA /RB ) R A R B INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF R A AND RB . AD9200 0.1mF 1.0 mF f. Variable Reference (Between 1 V and 2 V) Figure 16. REFSENSE AVDD VREF AD9200 g. Internal Reference Disable (Power Reduction) MODE INTERNAL REF MIDSCALE OFFSET VOLTAGE IS DERIVED FROM INTERNAL OR EXTERNAL REF MIDSCALE AVDD/2 * MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE 10kV 10kV 10kV A/D CORE 4.2kV TOTAL REFTS REFBS 10mF 0.1mFREFTF REFBF 0.1mF AIN 0.1mF AD9200 10kV SHA b. Center Span Mode

–13–REV. E The input capacitor should be sized to allow sufficient acquisi- tion time of the clamp voltage at AIN within the CLAMP inter- val, but also be sized to minimize droop between clamping intervals. Specifically, the acquisition time when the switch is closed will equal: T ACQ = RINCIN ln VC VE æ Łç ö where VC is the voltage change required across CIN, and VE is the error voltage. VC is calculated by taking the difference be- tween the initial input dc level at the start of the clamp interval and the clamp voltage supplied at CLAMPIN. V E is a system- dependent parameter, and equals the maximum tolerable devia- tion from VC. For example, if a 2-volt input level needs to be clamped to 1 volt at the AD9200’s input within 10 millivolts, then VC equals 2 – 1 or 1 volt, and V E equals 10 mV. Note that once the proper clamp level is attained at the input, only a very small voltage change will be required to correct for droop. The voltage droop is calculated with the following equation: dV = IBIAS CIN t() where t = time between clamping intervals. The bias current of the AD9200 will depend on the sampling rate, FS. The switched capacitor input AIN appears resistive over time, with an input resistance equal to 1/C SFS. Given a sampling rate of 20 MSPS and an input capacitance of 1 pF, the input resistance is 50 k W . This input resistance is equivalently terminated at the midscale voltage of the input range. The worst case bias current will thus result when the input signal is at the extremes of the input range, that is, the furthest distance from the midscale voltage level. For a 1-volt input range, the maxi- mum bias current will be – 0.5 volts divided by 50 kW , which is – 10 mA. If droop is a critical parameter, then the minimum value of C IN should be calculated first based on the droop requirement. Acquisition time—the width of the CLAMP pulse—can be adjusted accordingly once the minimum capacitor value is cho- sen. A tradeoff will often need to be made between droop and acquisition time, or error voltage V Clamp Circuit Example A single supply video amplifier outputs a level-shifted video signal between 2 and 3 volts with the following parameters: horizontal period = 63.56 ms, horizontal sync interval = 10.9 ms, horizontal sync pulse = 4.7 ms, sync amplitude = 0.3 volts, video amplitude of 0.7 volts, reference black level = 2.3 volts The video signal must be dc restored from a 2- to 3-volt range down to a 1- to 2-volt range. C onfiguring the AD9200 for a one volt input span with an input range from 1 to 2 v olts (see Figure 24), the CLAMPIN voltage can be set to 1 volt with an external voltage or by direct connection to REFBS. The CLAMP pulse may be applied during the SYNC pulse, or during the back porch to truncate the SYNC below the AD9200’s mini- mum input voltage. With a C IN = 1 mF, and RIN = 20 W , the acquisition time needed to set the input dc level to one volt with 1 mV accuracy is about 140 ms, assuming a full 1 volt V C. With a 1 mF input coupling capacitor, the droop across one horizontal can be calculated: IBIAS = 10 mA, and t = 63.5 ms, so dV = 0.635 mV, which is less than one LSB. After the input capacitor is initially charged, the clamp pulse- width only needs to be wide enough to correct small voltage errors such as the droop. The fine scale settling characteristics of the clamp circuitry are shown in Table II. Depend ing on the required accuracy, a CLAMP pulsewidth of 1 ms–3 ms should work in most applications. The OFFSET val- ues ignore the contribution of offset from the clamp amplifier; they simply compare the output code with a “final value” mea- sured with a much longer CLAMP pulse duration. Table II. CLAMP OFFSET 10 ms <1 LSB 5 ms 5 LSBs 4 ms 7 LSBs 3 ms 11 LSBs 2 ms 19 LSBs 1 ms 42 LSBs CLAMP IN AD9200 CLAMP AINCIN RIN TO SHA SW1 Figure 24a. Clamp Operation 0.1 F 10 F AIN REFTF REFBS MODE AD9200 REFTS

0.1 F REFBF

0.1 F Figure 24b. Video Clamp Circuit

–18– REV. E AD822 AD822 AD822 JP5 JP17 JP18 GND R53 49.9V R37 1kV R38 1kV R39 1kV DRVDD B S3 21 A 2S4 A TP11 CLAMP THREE-STATE STBY R14 10kV CW C9 10/10V +3–5A C10 0.1mF 1 6 R18 316kV R16 1kV C29 0.1mF 2N3904 C14 0.1mF C15 10/10V TP17 EXTB R20 178V R19 178V C12 0.1mF C13 10/10V CM TP16 EXTT 2N3906 0.626V TO 4.8V R17 316VR15 1kV C11 0.1mF +3–5A R13 11kV R12 10kV 10/10V 0.1mF8 +3–5A R10 5kV R11 15kV CW XXXX ADJ. TP14 10kV 1.5kV AD1580 +3–5A 5.49kV XXXX ADJ. DUTCLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN 1 14 C33 10/10V AD9200 CLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN AVSS DRVSS AVDD C17 10/10V AVDD C16 0.1mF C18 10/10V C19 0.1mF DRVDD OTR TP19 27 21 RN1 22V RN1 22V RN1 22V RN1 22V RN2 22V RN2 22V RN2 22V RN1 22V RN1 22V RN2 22V RN2 22V RN2 22V NC NC NC CLK CLK_OUT +3–5D GND +3–5D +3–5D GND GND C20 0.1mF JP21 B A C21 0.1mF C43 0.1mF GND 32 1 JP20 GND GNDGND GND C41 0.1mF 74LVXC4245WM 74LVXC4245WM C40 0.1mF GND DRVDD CLK DRVDD B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A B U5 A B U5 A B U5 A B U5 A B U5 A B U5 A B U5 A B U5 A VCCB VCCA NC1 T/R OE OE GD2 GD1 U4 GD3 VCCB VCCA NC1 T/R GD2 GD1 U5 GD3 OTR 71 0 61 1 5 12 DRVDD 41 3 2 15 11 6 61 1 51 2 4 13 3 14 21 5 1 16 WHITE WHITE AD822 C42 0.1mF Figure 39a. Evaluation Board Schematic

–19–REV. E C32 0.1 F TP29 +3–5D C31 10/10V C22 0.1 F TP20 DRVDD C23 10/10V C24 0.1 F TP21 AVDD C25 33/16V C26 0.1 F TP22 +3–5A C27 10/10V GND J6 TP23 TP24 TP25 TP26 TP27 TP28 GND J10

9 U6 8

11 U6 10

13 U6 12

0.1 F U6 DECOUPLING AVDDCLK 74AHC14 PWR GND TP1 AVDD VREF TP5 TP6 JP1 JP2 JP3 JP4 JP6 JP9 B A TP7 C35 10/10V C36 0.1 F C37 0.1 F C38 0.1 F GND GND JP12 JP11 GND JP13JP7 0.1 F 0.1 F TP3 TP4 JP10 0.1 F+ 10/10V REFSENSE EXTB REFBF REFTF EXTT CLAMPIN EXTT REFTS REFBS EXTBTP8 JP8 JP26 TP10 DCIN TP9R2 100 100 A B 0.1 F 47/10V P S AIN REFBS CM T1–1T A 1 B 49.9 TP12 R51 49.9 CLK TP13 DUTCLK R52 49.9U63 4 12 U6 5 6 A A 49.9 ADC_CLK C30 0.1 F JP22 AVDD AVDDCLK R35 4.99k R36 4.99k R34 AVDD MODER5 10k 10k JP14 JP15 JP16 GND CW Figure 39b. Evaluation Board Schematic

–23–REV. E GROUNDING AND LAYOUT RULES As is the case for any high performance device, proper ground- ing and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD9200 have been separated to optimize the management of return currents in a system. Grounds should be connected near the ADC. It is recommended that a printed circuit board (PCB) of at least four layers, employing a ground plane and power planes, be used with the AD9200. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. These characteristics result in both a reduction of electro- magnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from cou- pling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD9200 in a solid ground plane. The power and ground return currents must be carefully managed. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. DIGITAL OUTPUTS Each of the on-chip buffers for the AD9200 output bits (D0–D9) is powered from the DRVDD supply pins, separate from AVDD. The output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated. In all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level. For DRVDD = 5 V, the AD9200 output signal swing is compat- ible with both high speed CMOS and TTL logic families. For TTL, the AD9200 on-chip, output drivers were designed to support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 20 MSPS, other TTL families may be appropriate. For interfacing with lower voltage CMOS logic, the AD9200 sustains 20 MSPS operation with DRVDD = 3 V. In all cases, check your logic family data sheets for compatibility with the AD9200 Digital Specification table. THREE-STATE OUTPUTS The digital outputs of the AD9200 can be placed in a high impedance state by setting the THREE-STATE pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation.

C3033e–0–8/99PRINTED IN U.S.A. –24– AD9200 REV. E OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Plastic Thin Quad Flatpack (LQFP) (ST-48) 0.354 (9.00) BSC 0.276 (7.0) BSC 3748 TOP VIEW (PINS DOWN) 0.276 (7.0) BSC 0.354 (9.00) BSC 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) BSC SEATING PLANE 0.063 (1.60) MAX 0° MIN 0° – 7° 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09)28-Lead Shrink Small Outline Package (SSOP) (RS-28) 28 15 141 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) PIN 1 SEATING PLANE 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) BSC 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558)