AD9148-M5375-EBZ

AD9148 AD | Alldatasheet

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Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter Preliminary Technical Data AD9148 Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

Single-carrier W-CDMA ACLR = 80 dBc @ 150 MHz IF Channel-to-channel isolation > 90 dB Analog output Adjustable 8.7 mA to 31.7 mA R L = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator eases data interface On-chip fine complex NCO allows carrier placement anywhere in DAC bandwidth High performance, low noise PLL clock multiplier Multiple chip synchronization interface Programmable digital inverse sinc filter Auxiliary DACs allow for offset control Gain DACs allow for I and Q gain matching Programmable I and Q phase compensation Digital gain control Flexible LVDS digital I/F supports 32- or 16-bit bus widths 196-ball CSP_BGA, 12 mm × 12 mm

APPLICATIONS

L TE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM MIMO/transmit diversity Digital high or low IF synthesis GENERAL DESCRIPTION The AD9148 is a quad, 16-bit, high dynamic range, digital-to- analog converter (DAC) that provides a sample rate of 1000 MSPS. These devices include features optimized for direct conversion transmit applications, including gain, phase, and offset compen- sation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the ADL5371/ ADL5372/ ADL5373/ADL5374/ADL5375. A serial peripheral interface (SPI) is provided for programming of the internal device parameters. Full-scale output current can be programmed over a range of 10 mA to 30 mA. The devices operate from 1.8 V and 3.3 V supplies for a total power consumption of 3 W at the maximum sample rate. They are enclosed in 196-ball chip scale package ball grid array with the option of an attached heat spreader. PRODUCT HIGHLIGHTS 1. Low noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. 2. A proprietary DAC output switching technique enhances dynamic performance. 3. The current outputs are easily configured for various single-ended or differential circuit topologies. 4. LVDS data input interface includes FIFO to ease input timing. TYPICAL SIGNAL CHAIN FPGA/ASIC/DSP NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. DC COMPLEX BASEBAND COMPLEX IF RF fIF LO ± fIF DAC1 DAC2 DIGITAL INTERPOLATION FILTERS POST DAC ANALOG FILTER DAC3 DAC4 POST DAC AQM LO AQM ↑2 ↑2 ↑2 ↑2 ↑2 ↑2 ↑2 ↑2 ↑2 ↑2 ↑2 ↑2 PA PA LO 08910-001 Figure 1.

AD9148 Preliminary Technical Data Rev. PrA | Page 2 of 73 TABLE OF CONTENTS

REVISION HISTORY

4/10—Revision PrA: Preliminary Version

Preliminary Technical Data AD9148 Rev. PrA | Page 3 of 73 FUNCTIONAL BLOCK DIAGRAM FIFO DATA RECEIVER 310MHz 310MHz 310MHz/620MHz 500MHz/1GHz 500MHz/1GHz I OFFSET Q OFFSET fS/2 MOD 1.2GHz 1GHz 2× 2× I GAIN Q GAIN 2× 2× 2× FIFO I OFFSET COS PHASE CORRECTION SIN Q OFFSET GAIN/ OFFSET_CTRL SINC–1 SINC–1 SINC–1 SINC–1 2× 2× I GAIN Q GAIN 2× 2× INTERNAL CLOCK TIMING AND CONTROL LOGIC HB3_EN HB3_CLK HB2_EN HB2_CLK HB1_EN HB1_CLK INVSINE_EN PREMOD_EN PREMOD_CLK MODE SDO SDIO SCLK CSB IRQ RESET FILTER COEFFICIENT 16-BIT DAC1 16-BIT DAC2 32-BIT NCO 16-BIT DAC3 16-BIT DAC4 GAIN GAIN AUX1 AUX2 GAIN GAIN AUX3 AUX4 DAC_CLK SYNC REFERENCE BIAS PLL_CTRL CLOCK MULTIPLIER (2× – 16×) MULTI-CHIP SYNC POWER-ON RESET SERIAL IN/OUT PORT PROGRAMMING REGISTERS FRAMEA_P/ FRAMEA_N FRAMEB_P/ FRAMEB_N DCIA_P/ DCIA_N DCIB_P/ DCIB_N B[15:0]_P/ B[15:0]_N A[15:0]_P/ A[15:0]_N IOUT1_P IOUT1_N AUX1_P AUX1_N IOUT2_P IOUT2_N AUX2_P AUX2_N IOUT3_P IOUT3_N AUX3_P AUX3_N IOUT4_P IOUT4_N AUX4_P AUX4_N VREF I120 CLK_P CLK_N REFCLK_P/ SYNC_P REFCLK_N/ SYNC_N 08910-002 fS/2 MOD fS/2 MOD fS/2 MOD Figure 2.

AD9148 Preliminary Technical Data Rev. PrA | Page 4 of 73 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V , IOVDD = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error ±0.001 % FSR Gain Error (with Internal Reference) ±2 % FSR Full-Scale Output Current1 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns TEMPERATURE DRIFT Main DAC Offset 0.04 ppm/°C Main DAC Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES IOVDD 1.71 1.8/3.3 3.47 V DVDD18 1.71 1.8 1.89 V POWER CONSUMPTION (NCO OFF , PLL DISABLED, AND SINC−1 FILTER BYPASSED, UNLESS OTHERWISE NOTED) 1 × Mode, fDAC = 300 MSPS, fINTERFACE = 600 MSPS 0.79 W 2 × Mode, fDAC = 500 MSPS, fINTERFACE = 500 MSPS 1.49 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS 2.18 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, NCO On 2.47 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, PLL Enabled 2.23 W 4 × Mode, fDAC = 800 MSPS, fINTERFACE = 400 MSPS, Sinc−1 Filter Enabled 2.44 W 8 × Mode, fDAC = 1000 MSPS, fINTERFACE = 250 MSPS 2.48 W Power-Down Mode 0.03 TBD W OPERATING RANGE −40 +25 +85 °C 1 Based on a 10 kΩ external resistor.

Preliminary Technical Data AD9148 Rev. PrA | Page 5 of 73 INPUT/OUTPUT SIGNAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V , IOVDD = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter Min Typ Max Unit CMOS INPUT LOGIC LEVEL (SCLK, SDIO, CSB, RESET E , TMS, TDI, TCK) Input VIN Logic High (IOVDD = 1.8 V) 1.2 V Input VIN Logic High (IOVDD = 3.3 V) 2.0 V Input VIN Logic Low (IOVDD = 1.8 V) 0.6 V Input VIN Logic Low (IOVDD = 3.3 V) 0.8 V CMOS OUTPUT LOGIC LEVEL (SDIO, SDO, IRQ E , PLL_LOCK, TDO) Output VOUT Logic High (IOVDD = 1.8 V) 1.4 V Output VOUT Logic High (IOVDD = 3.3 V) 2.4 V Output VOUT Logic Low (IOVDD = 1.8 V) 0.4 V Output VOUT Logic Low (IOVDD = 3.3 V) 0.4 V LVDS RECEIVER INPUTS (A[15:0]_x, B[15:0]_x, DCIA_x, DCIB_x, FRAMEA_x, FRAMEB_x) Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH to VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate, fINTERFACE (See Table 4) 1200 MSPS DAC CLOCK INPUT (CLK_P , CLK_N) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage (Self-Biasing, AC-Coupled) 1.25 V Maximum Clock Rate 1000 MSPS REFERENCE CLOCK INPUT (REFCLK_P/SYNC_P AND REFCLK_N/SYNC_N) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage (Self-Biasing, AC-Coupled) 1.25 V Maximum Clock Rate 500 MSPS Minimum Clock Rate (PLL Enabled) Loop Divider = /2 125 MSPS Loop Divider = /4 62.5 MSPS Loop Divider = /8 31.25 MSPS Loop Divider = /16 15.625 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High (tPWH) 12.5 ns Minimum Pulse Width Low (tPWL) 12.5 ns Set-Up Time, SDI to SCLK (tDS) 1.9 ns Hold Time, SDI to SCLK (tDH) 0.2 ns Data Valid, SDO to SCLK (tDV) 23 ns Setup time, CSB to SCLK (tDCSB) 1.4 ns

Table 4. Maximum Rate Figure 3. Defining Maximum Rates

Preliminary Technical Data AD9148 Rev. PrA | Page 7 of 73 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V , IOVDD = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 5. Parameter Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 400 MSPS, fOUT = 80 MHz 72 dBc fDAC = 600 MSPS, fOUT = 100 MHz 67 dBc fDAC = 1000 MSPS, fOUT = 100 MHz 65 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 400 MSPS, fOUT = 100 MHz 85 dBc fDAC = 600 MSPS, fOUT = 120 MHz 82 dBc fDAC = 1000 MSPS, fOUT = 150 MHz 76 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING fDAC = 200 MSPS, fOUT = 80 MHz −160 dBm/Hz fDAC = 400 MSPS, fOUT = 100 MHz −161 dBm/Hz fDAC = 800 MSPS, fOUT = 100 MHz −162.5 dBm/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL Off −81 dBc fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL On −78 dBc fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL Off −79 dBc fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL On −72.5 dBc W-CDMA ALTERNATE CHANNEL LEAKAGE RATIO, SINGLE CARRIER fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL Off −87 dBc fDAC = 737.28 MSPS, fOUT = 100 MHz, PLL On −83 dBc fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL Off −84 dBc fDAC = 737.28 MSPS, fOUT = 200 MHz, PLL On −80.5 dBc

Table 7. Thermal Resistance

25 PCB vias

The maximum junction temperature for the AD9148 is 125°C. Table 9. The maximum fDAC rate applies to all interpolation rates. DAC rate specified in Table 9 decreases.

Table 8. Thermal Resistance and Maximum Power 1 Heat sink is used in the thermal model: 13 mm × 13 mm, 15 mm tall. Table 9. Power vs. fDAC Rate and Functionality

2.22 CSP_BGA No 820 740 695 630

2.50 CSP_BGA Yes 950 875 810 740

2.67 BGA_EP No 1000 945 870 810

2.86 BGA_EP Yes 1000 1000 940 870

1 Typical maximum fDAC rate with inverse sinc filter off. 2 Heat sink is used in the thermal model: 13 mm × 13 mm, 15 mm tall.

Figure 4. Pin Configuration (Top View), Analog and Clock Domain Pins

Figure 5. Pin Configuration (Top View), Digital Domain Pins Table 10. Pin Function Description E6, E7, E8, E9 CVDD18 1.8 V Clock Supply. F5, F6, F7, F8, F9, F10 AVDD33 3.3 V Analog Supply. DVDD18 1.8 V Digital Supply. B7, B8, H11 NC Not Connect. Leave this pin unconnected. C1 IOUT1_N DAC 1 Complementary Output Current. D1 IOUT1_P DAC 1 Positive Output Current. A3 IOUT2_N DAC 2 Complementary Output Current. A4 IOUT2_P DAC 2 Positive Output Current. A11 IOUT3_P DAC 3 Positive Output Current. A12 IOUT3_N DAC 3 Complementary Output Current. C14 IOUT4_N DAC 4 Complementary Output Current. D14 IOUT4_P DAC 4 Positive Output Current. C2 AUX1_N Auxiliary DAC 1 Complementary Output Current. D2 AUX1_P Auxiliary DAC 1 Positive Output Current.

AD9148 Preliminary Technical Data Rev. PrA | Page 12 of 73 Pin No. Mnemonic Description B3 AUX2_N Auxiliary DAC 2 Complementary Output Current. B4 AUX2_P Auxiliary DAC 2 Positive Output Current. B11 AUX3_P Auxiliary DAC 3 Positive Output Current. B12 AUX3_N Auxiliary DAC 3 Complementary Output Current. C13 AUX4_N Auxiliary DAC 4 Complementary Output Current. D13 AUX4_P Auxiliary DAC 4 Positive Output Current. A8 I120 Tie to analog ground via 10 kΩ resistor to generate a 120 μA reference current. A7 VREF Band Gap Voltage Reference I/O. Decouple to analog ground via 0.1 μF capacitor. Output impedance is approximately 5 kΩ. B6, A6 CLK_P/CLK_N Positive/Negative DAC Clock Input (CLK). B9, A9 REFCLK_P/REFCLK_N or SYNC_P/SYNC_N PLL Reference Clock Input (REFCLK_x). This pin has a secondary function as a synchronization input (SYNC_x). H4 IRQ Active Low Open-Drain Interrupt Request Output. Pull up to IOVDD with a 10 kΩ resistor. H3 RESET An active low LVCMOS input resets the device. Pull up to IOVDD. G1 SDO Serial Data Output for SPI. G2 CSB Active Low Chip Select for SPI. H1 SDIO Serial Data Input/Output for SPI. H2 SCLK Qualifying Clock Input for SPI. G11, G12 TRENCH Connect this pin to VSS. H12 PLL_LOCK Active High LVCMOS Output. It indicates the lock status of the PLL circuitry. G13 TMS TAP Test Mode Select G14 TDI TAP Test Data Input. H13 TCK TAP Test Clock Input. H14 TDO TAP Test Data Output. M1, L1 A0_P/A0_N LVDS Data Input Pair, Port A (LSB). P1, N1 A1_P/A1_N LVDS Data Input Pair, Port A. M2, L2 A2_P/A2_N LVDS Data Input Pair, Port A. P2, N2 A3_P/A3_N LVDS Data Input Pair, Port A. P3, N3 A4_P/A4_N LVDS Data Input Pair, Port A. P4, N4 A5_P/A5_N LVDS Data Input Pair, Port A. P5, N5 A6_P/A6_N LVDS Data Input Pair, Port A. P6, N6 A7_P/A7_N LVDS Data Input Pair, Port A. P7, N7 A8_P/A8_N LVDS Data Input Pair, Port A. P8, N8 A9_P/A9_N LVDS Data Input Pair, Port A. P9, N9 A10_P/A10_N LVDS Data Input Pair, Port A. P10, N10 A11_P/A11_N LVDS Data Input Pair, Port A. P11, N11 A12_P/A12_N LVDS Data Input Pair, Port A. P12, N12 A13_P/A13_N LVDS Data Input Pair, Port A. P13, N13 A14_P/A14_N LVDS Data Input Pair, Port A. P14, N14 A15_P/A15_N LVDS Data Input Pair, Port A (MSB). K13, J13 DCIA_P/DCIA_N LVDS Data Clock Input Pair for Port A. K14, J14 FRAMEA_P/FRAMEA_N LVDS Frame Input for Port A. K3, J3 B0_P/B0_N LVDS Data Input Pair, Port B (LSB). M3, L3 B1_P/B1_N LVDS Data Input Pair, Port B. K4, J4 B2_P/B2_N LVDS Data Input Pair, Port B. M4, L4 B3_P/B3_N LVDS Data Input Pair, Port B. M5, L5 B4_P/B4_N LVDS Data Input Pair, Port B M6, L6 B5_P/B5_N LVDS Data Input Pair, Port B. M7, L7 B6_P/B6_N LVDS Data Input Pair, Port B. M8, L8 B7_P/B7_N LVDS Data Input Pair, Port B. M9, L9 B8_P/B8_N LVDS Data Input Pair, Port B. M10, L10 B9_P/B9_N LVDS Data Input Pair, Port B. M11, L11 B10_P/B10_N LVDS Data Input Pair, Port B.

Preliminary Technical Data AD9148 Rev. PrA | Page 13 of 73 Pin No. Mnemonic Description K11, J11 B11_P/B11_N LVDS Data Input Pair, Port B. M12, L12 B12_P/B12_N LVDS Data Input Pair, Port B. K12, J12 B13_P/B13_N LVDS Data Input Pair, Port B. M13, L13 B14_P/B14_N LVDS Data Input Pair, Port B. M14, L14 B15_P/B15_N LVDS Data Input Pair, Port B (MSB). K2, J2 DCIB_P/DCIB_N LVDS Data Clock Input Pair for Port B. K1, J1 FRAMEB_P/FRAMEB_N LVDS Frame Input for Port B.

AD9148 Preliminary Technical Data Rev. PrA | Page 20 of 73 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTx_P , 0 mA output is expected when the inputs are all 0s. For IOUTx_N, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temp er atu re D r i ft Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degrees Celsius. For reference drift, the drift is reported in ppm per degrees Celsius. Power Supply Rejection (PSR) The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. In-Band Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Out-of-Band Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the Nyquist frequency of the DAC output sample rate. Normally, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter An interpolation filter up-samples the input digital data by a multiple of fDATA (interpolation rate) and then filters out the undesired spectral images created by the up-sampling process. Adjacent Channel Leakage Ratio (ACLR) The ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Figure 40. SPI Port read/write access to all registers that configure the AD9148. pins for input/output (SDIO/SDO). There are two phases to a communication cycle with the AD9148. starting register address for the first byte of the data transfer. are used to write the instruction byte into the device. transfer cycle, none of the present data is written. upon writing to the last bit of each transfer byte. The instruction byte contains the information shown in Table 11. Table 11. SPI Instruction Byte a write data transfer occurs after the instruction byte write. edge of SCLK. All data is driven out on the falling edge of SCLK. low during the entire communication cycle. Logic 0, configuring the SDIO pin as unidirectional. output data and is set to a high impedance state.

Table 12. Register Map

AD9148 Preliminary Technical Data Rev. PrA | Page 24 of 73 Addr Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x201 Coeff I Byte0 0 Coeff_1i[3:0] Coeff_0i[2:0] 0x00 0x211 Coeff I Byte1 Coeff_3i[2:0] Coeff_2i[4:0] 0xC0 0x221 Coeff I Byte 2 Coeff_4i[2:0] 0 Coeff_3i[6:3] 0xEF 0x231 Coeff I Byte 3 0 Coeff_4i[9:3] 0x7F 0x241 Coeff Q Byte 0 0 Coeff_1q[3:0] Coeff_0q[2:0] 0x69 0x251 Coeff Q Byte 1 Coeff_3q[2:0] Coeff_2q[4:0] 0xE6 0x261 Coeff Q Byte 2 Coeff_4q[2:0] 0 Coeff_3q[6:3] 0x0D 0x271 Coeff Q Byte3 0 Coeff_4q[9:3] 0x00 0x281 I phase adj LSB Phase Word I[7:0] 0x00 0x291 I phase adj MSB Phase Word I[9:8] 0x00 0x2A1 Q phase adj LSB Phase Word Q[7:0] 0x00 0x2B1 Q phase adj MSB Phase Word Q[9:8] 0x00 0x2C1 I DC offset LSB DC Offset I[7:0] 0x00 0x2D1 I DC offset MSB DC Offset I[15:8] 0x00 0x2E1 Q DC offset LSB DC Offset Q[7:0] 0x00 0x2F1 Q DC offset MSB DC Offset Q[15:8] 0x00 0x301 IDAC FSC adj IDAC FSC Adj[7:0] 0xF9 0x311 IDAC control IDAC sleep IDAC FSC Adj[9:8] 0x01 0x321 AUX IDAC data AUX IDAC Data[7:0] 0x00 0x331 AUX IDAC control AUX IDAC sign AUX IDAC current direction AUX IDAC power down AUX IDAC Data[9:8] 0x00 0x341 QDAC FSC adj QDAC FSC Adj[7:0] 0xF9 0x351 QDAC control QDAC sleep QDAC FSC Adj[9:8] 0x01 0x361 AUX QDAC data AUX QDAC Data[7:0] 0x00 0x371 AUX QDAC control AUX QDAC sign AUX QDAC current direction AUX QDAC power down AUX QDAC Data[9:8] 0x00 0x381 SED_S0_L SED Compare Pattern Sample0[7:0] 0xB6 0x391 SED_S0_H SED Compare Pattern Sample0[15:8] 0x7A 0x3A1 SED_S1_L SED Compare Pattern Sample1[7:0] 0x45 0x3B1 SED_S1_H SED Compare Pattern Sample1[15:8] 0xEA 0x3C1 SED3_S2_L SED Compare Pattern Sample2[7:0] 0x16 0x3D1 SED3_S2_H SED Compare Pattern Sample2[15:8] 0x1A 0x3E1 SED4_S3_L SED Compare Pattern Sample3[7:0] 0xC6 0x3F1 SED4_S3_H SED Compare Pattern Sample3[15:8] 0xAA 0x40 SED control/ status SED compare enable Port B error detected Port A error detected Auto- clear enable Port B compare failed Port A compare failed Compare passed 0x00 0x411 SED_R_L SED Status Rising Edge Samples[7:0] 0x421 SED_R_H SED Status Rising Edge Samples[15:8] 0x431 SED_F_L SED Status Falling Edge Samples[7:0] 0x441 SED_F_H SED Status Falling Edge Samples[15:8] 0x501 I gain control I Gain[7:0] 0x40 0x511 Q gain control Q Gain[7:0] 0x40

to Register 0x3F and Register 0x41 to Register 0x51 configure DAC 3 (I) and DAC 4 (Q) data paths with DAC SPI select = 1 (Register 0x00[4]). Table 13. Register Descriptions 0 = SDIO operates as an input only. 1 = SDIO operates as bidirectional input/output. Reset is asserted when this bit transitions from 0 to 1.

4 DAC SPI select Selects which DAC data path Register 0x20 to Register 0x3F and

Register 0x41 to Register 0x51 configure. 1 = DAC 3 (I path) and DAC 4 (Q path) are configured.

6 Power-Down

5 Power-down

AD9148 Preliminary Technical Data Rev. PrA | Page 26 of 73 Register Name Addr (Hex) Bit Name Function Default Data Format 03 7 Binary format Input data is in twos complement format (0) or unsigned binary format (1). 6 Q first enable Indicates I/Q data pairing on data input; I first (0), Q first (1). 0 5 Dual port mode Number of input data ports used. 1 Single port (0), dual port (1). 4 Bus swap 0 = normal data input bus pin out (MSB to LSB). 0 1 = inverted data input bus pin out (LSB to MSB). 3 Byte mode 0 = data input bus is 16-bit wide on each port. 0 1 = data input bus is two 8-bit wide buses on Port A. 2 Byte swap 0 = normal data input bus pin out (MSB to LSB). 0 1 = inverted data input bus pin out (LSB to MSB). Interrupt Enable 0 04 7 Enable PLL lock lost Enables interrupt for PLL lock lost. 0 6 Enable PLL lock Enables interrupt for PLL lock. 0

5 Enable sync

Enables interrupt for sync lock lost. 0 4 Enable sync lock Enables interrupt for sync lock. 0

2 Enable FIFO

Enables interrupt for FIFO SPI aligned. 0

1 Enable FIFO

Enables interrupt for FIFO Warning 1. 0

0 Enable FIFO

Enables interrupt for FIFO Warning 2. 0 Interrupt Enable 1 05 4 Enable AED compare pass Enable interrupt for AED compare pass. 0

3 Enable AED

Enables interrupt for AED compare fail. 0

2 Enable SED

Enables interrupt for SED compare fail. 0

Preliminary Technical Data AD9148 Rev. PrA | Page 27 of 73 Register Name Addr (Hex) Bit Name Function Default Event Flag 0 (All bits are high when interrupt is active. Clear interrupt by writing respective bit high.) 06 7 PLL lock lost 1 = indicates that the PLL that was previously locked, has unlocked from the reference signal.

6 PLL lock 1 = indicates that the PLL has locked to the reference clock

input.

5 Sync lock lost 1 = indicates that the sync logic that was previously locked,

has lost alignment. 4 Sync lock 1 = indicates that the sync logic achieved sync alignment. This is indicated when no phase changes are requested for at least a few full averaging cycles.

2 FIFO SPI aligned 1 = indicates that a FIFO reset originating from a serial port-

based request has successfully completed.

1 FIFO Warning 1 1 = indicates that the difference between the FIFO read and

write pointers is 1.

0 FIFO Warning 2 1 = indicates that the difference between the FIFO read and

write pointers is 2. Event Flag 1(All bits are high when interrupt is active. Clear interrupt by writing respective bit high). 07 4 AED compare pass 1 = indicates that the SED logic detected a valid input data pattern comparison against the preprogrammed expected values.

3 AED compare fail 1 = indicates that the SED logic detected an invalid input data

pattern comparison against the preprogrammed expected values. This automatically clears when eight valid I/Q data pairs are received.

2 SED compare fail 1 = indicates that the SED logic detected an invalid input data

pattern comparison against the preprogrammed expected values. Clock receiver control 08 7 CLK duty correction Enables duty-cycle correction on CLK input. 0

6 REFCLK duty

Enables duty-cycle correction on REFCLK input. 0

5 CLK cross

Enables differential crossing correction on CLK input. 1

4 REFCLK cross

Enables differential crossing correction on REFCLK input. 1 3:0 0111 Always set these bits to 0111 0111 PLL Control 0 0A 7 PLL enable En ables PLL clock multiplier. 0

6 PLL manual

Enables PLL band selection mode (0 = auto, and 1 = manual). 1 5:0 Manual VCO band VCO band used in manual mode. 0 PLL Control 1 0C 7:5 PLL loop bandwidth Selects PLL loop filter bandwidth. 110 000 = narrowest bandwidth. 111 = widest bandwidth. 4:0 01001 Set these bits to 01001 for optimal PLL operation. 10001

AD9148 Preliminary Technical Data Rev. PrA | Page 28 of 73 Register Name Addr (Hex) Bit Name Function Default PLL Control 2 0D 7:6 N2 DAC CLK to PLL controller clock rate (fPC_CLK). 11 00 = 2. 01 = 4. 10 = 8. 11 = 16. f PC_CLK must always be less than 50 MHz.

4 PLL cross

Enables PLL cross point control. 3:2 N0 VCO to DACCLK divider. 001 00 = 1. 01 = 2. 10 = 4. 11 = 4. 1:0 N1 DACCLK-to-REFCLK divider. 01 00 = 2. 01 = 4. 10 = 8. 11 = 16. PLL Status 0 0E 3:0 PLL control voltage PLL VCO control voltage readback value. Read- only PLL Status 1 0F 5:0 VCO band readback VCO band value. Read- only Sync Control 0 10 7 Sync enable Enables synchronization logic. 0

6 FIFO rate/data

Operates synchronization at the FIFO reset rate (0)/data rate (1). 0

3 Rising edge sync Rising edge of CLK samples sync input (1), falling edge of

CLK samples sync input (0). 2:0 Sync averaging Average sync input of number of samples. 000 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128.

Preliminary Technical Data AD9148 Rev. PrA | Page 29 of 73 Register Name Addr (Hex) Bit Name Function Default Sync Control 1 11 5:0 Sync phase request Offset of internal divided by 64 clock phase after sync. 000000 000000 = 0 DAC clocks. 111111 = 63 DAC clocks. Sync Status 0 12 7 Sync Lost Synchronization lost. Read- only 6 Sync locked Synchronization found. Read- only Data Receiver Control 14 6 One DCI 0 = two DCIs used, DCIA_x and DCIB_x. 0 1 = one DCI used, DCIA_x. Data Receiver Status 15 7 LVDS receiver frame high Frame input LVDS level > 1.7 V. Read- only

6 LVDS receiver

Frame input LVDS level < 0.7 V. Read- only

5 LVDS receiver

DCI input LVDS level > 1.7 V. Read- only

4 LVDS receiver

DCI input LVDS level < 0.7 V. Read- only

3 LVDS receiver

Port B input LVDS level > 1.7 V. Read- only

2 LVDS receiver

Port B input LVDS level < 0.7 V. Read- only

1 LVDS receiver

Port A input LVDS level > 1.7 V. Read- only

0 LVDS receiver

Port A input LVDS level < 0.7 V. Read- only FIFO status/ Control Port A 17 7 FIFO Warning 1 FIFO read and write pointers within ±1. Read- only

6 FIFO Warning 2 FIFO read and write pointers within ±2 Read-

5 FIFO reset aligned FIFO read and write pointers aligned after chip reset. Read- only

4 FIFO SPI align

FIFO read and write pointers aligned after SPI driven FIFO reset. Read- only

3 FIFO SPI align

Request FIFO read and write pointers alignment via SPI. 0 2:0 FIFO phase offset FIFO read and write pointer phase offset from optimal phase following FIFO reset. 000 000 = 0 offset from optimal phase. 111 = 7 offset from optimal phase. The optimal value is 0.

AD9148 Preliminary Technical Data Rev. PrA | Page 30 of 73 Register Name Addr (Hex) Bit Name Function Default FIFO Status Port A 18 7:0 FIFO Level Thermo meter encoded measure of the FIFO level. Read- only FIFO status/ Control Port B 7 FIFO Warning 1 FIFO read and write pointers within ±1. Read- only 6 FIFO Warning 2 FIFO read and write pointers within ±2. Read- only 5 FIFO reset aligned FIFO read and write pointers aligned after chip reset. Read- only FIFO read and write pointers aligned after SPI driven FIFO reset. Read- only Request FIFO read and write pointers alignment via SPI. 0 2:0 FIFO phase offset FIFO read and write pointer phase offset from optimal phase following FIFO reset. 000 000 = 0 offset from optimal phase. 111 = 7 offset from optimal phase. The optimal value is 0. FIFO Status Port B 1A 7:0 FIFO level Thermometer encoded measure of the FIFO Level Read- only HB1 Control 1C 7 Enable pre mod Enable fS/2 modulation stage that precedes Stage 1 interpolation filter. 6 Bypass sinc-1 Sinc -1 filter bypass. 1 2:1 HB1[1:0] Modulation mode for first stage interpolation filter HB1 = 2 × fIN1). 00 = input signal modulated by dc. Filter pass band is from −0.2 to +0.2 of fHB1. 01 = input signal modulated by dc. Filter pass band is from 0.05 to 0.45 of fHB1. 10 = input signal modulated by fHB1/2. Filter pass band is from 0.3 to 0.7 of fHB1. 11 = input signal modulated by fHB1/2. Filter pass band is from 0.55 to 0.95 of fHB1. 0 Bypass HB1 First stage interpolation filter bypass. 0

Preliminary Technical Data AD9148 Rev. PrA | Page 31 of 73 Register Name Addr (Hex) Bit Name Function Default HB2 Control HB2[2:0] Modulation mode for second stage interpolation filter (fHB2 = 2 × fIN2). 000 000 = input signal modulated by dc. Filter pass band is from −0.1 to +0.1 of fHB2. 001 = input signal modulated by dc. Filter pass band is from 0.025 to 0.225 of fHB2. 010 = input signal modulated by fHB2/4. Filter pass band is from 0.15 to 0.35 of fHB2. 011 = input signal modulated by fHB2/4. Filter pass band is from 0.275 to 0.475 of fHB2. 100 = input signal modulated by fHB2/2. Filter pass band is from 0.4 to 0.6 of fHB2. 101 = input signal modulated by fHB2/2. Filter pass band is from 0.525 to 0.725 of fHB2. 110 = input signal modulated by 3fHB2/4. Filter pass band is from 0.65 to 0.85 of fHB2. 111 = input signal modulated by 3fHB2/4. Filter pass band is from 0.775 to 0.975 of fHB2. 0 Bypass HB2 Second stage interpolation filter bypass. 0 HB3 Control 1E 7 Bypass Phase Adj 1 = bypass phase compensation. 1 3:1 HB3[2:0] Modulation mode for third stage interpolation filter HB3 = 2 × fIN3). 000 000 = input signal modulated by dc. Filter pass band is from −0.1 to +0.1 of fHB3. 001 = input signal modulated by dc. Filter pass band is from 0.025 to 0.225 of fHB3. 010 = input signal modulated by fHB3/4. Filter pass band is from 0.15 to 0.35 of fHB3. 011 = input signal modulated by fHB3/4. Filter pass band is from 0.275 to 0.475 of fHB3. 100 = input signal modulated by fHB3/2. Filter pass band is from 0.4 to 0.6 of fHB3. 101: Input signal modulated by fHB3/2. Filter pass band is from 0.525 to 0.725 of fHB3. 110 = input signal modulated by 3fHB3/4. Filter pass band is from 0.65 to 0.85 of fHB3. 111 = input signal modulated by 3F HB3/4. Filter pass band is from 0.775 to 0.975 of fHB3. 0 Bypass HB3 Third stage interpolation filter bypass. 1 Chip ID 1F 7:0 Chip ID Chip ID Readback 20

AD9148 Preliminary Technical Data Rev. PrA | Page 32 of 73 Register Name Addr (Hex) Bit Name Function Default Coeff I Byte 0 20 7 0 Set this bit to 0. 0 6:3 Coeff_1i I-Path DAC Sinc-1 Filter Coefficient 2 in twos complement format. 2:0 Coeff_0i I-Path DAC Sinc-1 Filter Coefficient 1 in twos complement format. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Coeff I Byte 1 21 7:5 Coeff_3i[2:0] I-Path DAC Sinc-1 Filter Coefficient 4 (LSB) in twos complement format. 4:0 Coeff_2i I-Path DAC Sinc-1 Filter Coefficient 3 in twos complement format. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Coeff I Byte 2 22 7:5 Coeff_4i[2:0] I-Path DAC Sinc-1 Filter Coefficient 5 (LSB) in twos complement format. 4 0 Set this bit to 0. 0 3:0 Coeff_3i[6:3] Set I-Path DAC Sinc-1 Filter Coefficient 4 (MSB) in twos complement format. F DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Coeff I Byte 3 23 7 0 Set this bit to 0. 0 6:0 Coeff_4i[9:3] I-Path DAC Sinc-1 Filter Coefficient 5 (MSB) in twos complement format. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Coeff Q Byte 0 24 7 0 Set this bit to 0. 0 6:3 Coeff_1q Q-Path DAC Sinc-1 Filter Coefficient 2 in twos complement format D 2:0 Coeff_0q Q-Path DAC Sinc-1 Filter Coefficient 1 in twos complement format. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Coeff Q Byte 1 25 7:5 Coeff_3q[2:0] Q-Path DAC Sinc-1 Filter Coefficient 4 (LSB) in twos complement format. 4:0 Coeff_2q Q-Path DAC Sinc-1 Filter Coefficient 3 in twos complement format. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path.

Preliminary Technical Data AD9148 Rev. PrA | Page 33 of 73 Register Name Addr (Hex) Bit Name Function Default Coeff Q Byte 2 26 7:5 Coeff_4q[2:0] Q-Path DAC Sinc-1 Filter Coefficient 5 (LSB) in twos complement format. 4 0 Set this bit to 0. 0 3:0 Coeff_3q[6:3] Q-Path DAC Sinc-1 Filter Coefficient 4 (MSB) in twos complement format. D Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Coeff Q Byte 3 27 7 0 Set this bit to 0. 0 6:0 Coeff_4q[9:3] Q-Path DAC Sinc-1 Filter Coefficient 5 (MSB) in twos complement format. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. I Phase Adj LSB 28 7:0 Phase Word I[7:0] See Register 0x29. 0 I Phase Adj MSB 29 1:0 Phase Word I[9:8] Phase Word I[9:0] is used to insert a phase offset between the I and Q data paths. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Q Phase Adj LSB 2A 7:0 Phase Word Q[7:0] See Register 0x2B. 0 Q Phase Adj MSB 2B 1:0 Phase Word Q[9:8] Phase Word Q[9:0] is used to insert a phase offset between the I and Q data paths. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. I DC Offset LSB 2C 7:0 DC Offset I[7:0] See Register 0x2D. 0 I DC Offset MSB 2D 7:0 DC Offset I[15:8] DC Offset I[15:0] is a value added directly to the samples written to the IDAC. The LSB bit weight is 2 Set DAC SPI select = 0 to configure DAC 1 path. 0 Set DAC SPI select = 1 to configure DAC 3 path. Q DC Offset LSB 2E 7:0 DC Offset Q[7:0] See Register 0x2F. 0 Q DC Offset MSB 2F 7:0 DC Offset Q[15:8] DC Offset Q[15:0] is a value added directly to the samples written to the QDAC. The LSB bit weight is 2 Set DAC SPI select = 0 to configure DAC 2 path. 0 Set DAC SPI select = 1 to configure DAC 4 path. 0

AD9148 Preliminary Technical Data Rev. PrA | Page 34 of 73 Register Name Addr (Hex) Bit Name Function Default IDAC FSC Adj 30 7:0 IDAC FSC Adj[7:0] IDAC full-scale current adjustment (LSB part). IDAC FS Adj[9:0] sets the full-scale current of the IDAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. ... 0x200 = 20.14 mA. 0x3FF = 31.66 mA. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. IDAC Control 31 7 IDAC sleep I DAC sleep mode (fast wake-up mode). 0 1:0 IDAC FSC Adj[9:8] IDAC full-scale current adjustment (MSB part) 01 Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Aux IDAC Data 32 7:0 AUX IDAC Data[7:0] Auxiliary IDAC data (LSB part). AUX IDAC Data[9:0] sets the magnitude of the aux DAC current. The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0x002 mA. 0x3FF = 2.046 mA. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Aux IDAC Control 33 7 AUX IDAC sign Auxiliary IDAC output sign. 0 0 = positive, current is directed to the AUXx_P pin. 1 = negative, current is directed to the AUXx_N pin.

6 AUX IDAC

Auxiliary IDAC current direction. 0 0 = source. 1 = sink.

5 AUX IDAC

Auxiliary IDAC power down. 0 1:0 AUX IDAC Data[9:8] Auxiliary IDAC data (MSB part). 00 Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select =1 to configure DAC 3 path.

Preliminary Technical Data AD9148 Rev. PrA | Page 35 of 73 Register Name Addr (Hex) Bit Name Function Default QDAC FSC Adj 34 7:0 QDAC FSC Adj[7:0] Q DAC full-scale current adjustment (LSB part). QDAC FS Adj[9:0] sets the full-scale current of the QDAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA ... 0x200 = 20.14mA 0x3FF = 31.66 mA Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. QDAC Control 35 7 QDAC sleep Q DAC sleep mode (fast wake-up mode). 0 1:0 QDAC FSC Adj[9:8] QDAC full-scale current adjustment (MSB part). 01 Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Aux QDAC Data 36 7:0 AUX QDAC Data[7:0] Auxiliary QDAC data (LSB part). AUX QDAC Data[9:0] sets the magnitude of the AUX DAC current. The range is 0 mA to 2 mA and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0x002 mA. 0x3FF = 2.046 mA. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path. Aux QDAC Control 37 7 AUX QDAC sign Auxiliary QDAC output sign. 0 0 = positive, current is directed to the AUXx_P pin. 1 = negative, current is directed to the AUXx_N pin.

6 AUX QDAC

Auxiliary QDAC current direction. 0 0 = source. 1 = sink.

5 AUX QDAC

Auxiliary QDAC power down. 0 1:0 AUX QDAC Data[9:8] Auxiliary QDAC data (MSB part). 00 Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path.

AD9148 Preliminary Technical Data Rev. PrA | Page 36 of 73 Register Name Addr (Hex) Bit Name Function Default SED_S0_L 38 7:0 SED Compare Pattern Sample0[7:0] Compare Pattern Sample0[15:0] is the word that is compared with Data Sample 0 captured at the input interface by the rising edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S0_H 39 7:0 SED Compare Pattern Sample0[15:8] Compare Pattern Sample0[15:0] is the word that is compared with Data Sample 0 captured at the input interface by the rising edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S1_L 3A 7:0 SED Compare Pattern Sample1[7:0] Compare Pattern Sample1[15:0] is the word that is compared with Data Sample 1 captured at the input interface by the falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S1_H 3B 7:0 SED Compare Pattern Sample1[15:8] Compare Pattern Sample1[15:0] is the word that is compared with Data Sample 1 captured at the input interface by the falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S2_L 3C 7:0 SED Compare Pattern Sample2[7:0] Compare Pattern Sample2[15:0] is the word that is compared with Data Sample 2 captured at the input interface by the rising edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S2_H 3D 7:0 SED Compare Pattern Sample2[15:8] Compare Pattern Sample2[15:0] is the word that is compared with Data Sample 2 captured at the input interface by the rising edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S3_L 3E 7:0 SED Compare Pattern Sample3 [7:0] Compare Pattern Sample3[15:0] is the word that is compared with Data Sample 3 captured at the input interface by the falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B. SED_S3_H 3F 7:0 SED Compare Pattern Sample3[15:8] Compare Pattern Sample3[15:0] is the word that is compared with Data Sample 3 captured at the input interface by the falling edge of DCI. Set DAC SPI select = 0 to configure Port A. Set DAC SPI select = 1 to configure Port B.

Preliminary Technical Data AD9148 Rev. PrA | Page 37 of 73 Register Name Addr (Hex) Bit Name Function Default SED Control/Status 40 7 SED compare enable Enables the SED circuitry. 0

6 Port B error

Status of last compare on Port B. 0

5 Port A error

Status of last compare on Port A. 0 3 Auto-clear enable Enables the auto reset after eight valid sample sets. 0

2 Port B compare

Fail status determined for last sample set on Port B. 0

1 Port A compare

Fail status determined for last sample set on Port A. 0 0 Compare passed Pass status determined for last sample set. 0 SED_R_L 41 7:0 SED Status Rising Edge Samples[7:0] SED Status Rising Edge Samples[15:0] indicate which bits were received in error. Read- only Set DAC SPI select = 0 to read back errors on Port A. Set DAC SPI select = 1 to read back errors on Port B. SED_R_H 42 7:0 SED Status Rising Edge Samples[15:8] SED Status Rising Edge Samples[15:0] indicate which bits were received in error. Read- only Set DAC SPI select = 0 to read back errors on Port A. Set DAC SPI select = 1 to read back errors on Port B. SED_F_L 43 7:0 SED Status Falling Edge Samples[7:0] SED Status Falling Edge Samples[15:0] indicate which bits were received in error. Read- only Set DAC SPI select = 0 to read back errors on Port A. Set DAC SPI select = 1 to read back errors on Port B. SED_F_H 44 7:0 SED Status Falling Edge Samples[15:8] SED Status Falling Edge Samples[15:0] indicate which bits were received in error. Read- only Set DAC SPI select = 0 to read back errors on Port A. Set DAC SPI select = 1 to read back errors on Port B. I Gain Control 50 7:0 IGain[7:0] IGain[7:0] is a value that directly scales the samples written to the IDAC. The bit weighting is MSB = 2 1 and LSB = 2−6, which yields a multiplier range of 0 to 3.984375. Set DAC SPI select = 0 to configure DAC 1 path. Set DAC SPI select = 1 to configure DAC 3 path. Q Gain Control 51 7:0 QGain[7:0] QGain[7:0] is a value that directly scales the samples written to the QDAC. The bit weighting is MSB = 2 1 and LSB = 2−6, which yields a multiplier range of 0 to 3.984375. Set DAC SPI select = 0 to configure DAC 2 path. Set DAC SPI select = 1 to configure DAC 4 path.

AD9148 Preliminary Technical Data Rev. PrA | Page 38 of 73 Register Name Addr (Hex) Bit Name Function Default FTW (LSB) 54 7:0 FTW[7:0] See Register 0x57. 0 FTW 55 7:0 FTW[15:8] See Register 0x57. 0 FTW 56 7:0 FTW [23:16] See Register 0x57. 0 FTW (MSB) 57 7:0 FTW [31:24] FTW[31:0] is the 32-bit frequency tuning word that determines frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Register 0x5A[2] transitions from 0 to 1. Phase Offset MSB 58 7:0 NCO Phase Offset[15:8] See Register 0x59. 0 Phase Offset LSB 59 7:0 NCO Phase Offset[7:0] NCO Phase Offset[15:0] sets the phase of the complex carrier signal when the NCO is reset. The phase offset spans between 0º and 360º. Each bit represents an offset of 0.0055º. Value is in twos complement format. DDS/Mod Control 5A 7 Bypass DDS/MOD 1 = bypass NCO. 1

5 Frame NCO reset ack

1 = indicates that the NCO has been reset due to an extended FRAME pulse signal.

4 Frame NCO

0→1 = The NCO is reset on the first extended FRAME pulse after this bit transitions from 0 to 1.

3 FTW update ack 1 = indicates that the FTW has been updated with the

SPI value.

2 FTW update request 0→1 = FTW is updated with the SPI value on 0 to 1

transition of this bit. 0 Sideband select 0 = The modulator outputs high-side image. 0 1 = The modulator outputs low-side image. The image is spectrally inverted compared to the input data. Die Temp Control 0 5C 1 Latch temp data 0 → 1 = latches temp sensor data. This should be completed before the Die Temp[15:0] is readback.

0 Temp Sensor

1 = powers down aux ADC that converts die temperature. 1 Die Temp Control 1 5D 7:0 00001010 Set these bits to 00001010 for optimal temperature sensor operation. 100000 Die Temp (LSBs) 5E 7:0 Die Temp[7:0] Die Temp[15:0] indicates the approximate die temperature. Read- only Die Temp (MSBs) 5F 7:0 Die Temp[15:8] Die Temp[15:0] indicates the approximate die temperature. Read- only DCI Delay 72 1:0 DCI Delay[1:0] Programmable delay added DCI. 00 00 = no added delay. 01 = 200 ps delay. 10 = 400 ps delay. 11 = 600 ps delay. PLL Ctrl (Test) 79 7:0 11111111 Set these bits to 11111111 for optimal PLL operation. 40

FRAME signal indicates to which DAC the data is intended. Figure 48. Timing Diagram for Byte Mode Table 14. Byte Swap Formatting

0 MSB Data Set 1[15:8] Data Set 2[15:8]

0 LSB Data Set 1[7:0] Data Set 2[7:0]

1 MSB Data Set 1[8:15] Data Set 2[8:15]

1 LSB Data Set 1[0:7] Data Set 2[0:7]

• Data format (Register 0x03)
• Data receiver control (Register 0x14)
• Data receiver status (Register 0x15) Depending on the data rate and DCI vs. data skew, the internal DCI can be inverted to make the valid data timing window.

32 BITS

3232 DATA

Figure 49. Block Diagram of FIFO significantly increases the timing budget of the interface. overall pipeline delay of the AD9148. written to FIFO B at the data rate. is made to read and write a single FIFO register simultaneously. through the FIFO and must be avoided.

Preliminary Technical Data AD9148 Rev. PrA | Page 43 of 73 No Synchronization In this mode, Bit 7 in Register 0x10 is set to 0, the pipeline delay in the signal processing is not controlled, and the read pointer of the FIFO is never reset. However, to assure that the FIFO can operate safely and there is no concurrent access to FIFO from the write and read pointer to the same address, it is important to ensure that the phase offset between the two pointers is greater than 2. In consequence, the only FIFO reset that can be used safely is the data rate synchronization, Bit 6 of Register 0x10 set to 0, where the FIFO is reset with a fixed offset of 4 between the write and read pointers. As there is no SYNC signal, the reset of the FIFO write pointer can only be done by a FRAME signal or an SPI command. FIFO Reset Commands Depending on the configuration of the system, the FIFO reset could be done manually or periodically for a multichip system. The AD9148 provides two ways to resetting the FIFO pointers: SPI interface or periodic reset using the FRAME signal. The SPI also gives access to each FIFO phase offset in Bits [2:0] of the corresponding FIFO status/control registers, Address 0x17 and Address 0x19. The value in these three bits corresponds either to the offset between the write and read pointer in the data rate synchronization or to the absolute address of the FIFO write pointer in the FIFO rate synchronization. SPI Command for Manual Reset If a manual reset is acceptable, the FIFO pointer addresses can be reset using the SPI interface. To initialize the FIFO data level through the SPI, Bit 3 of Register 0x17 (FIFO Port A) or Bit 3 of Register 0x19 (FIFO Port B) should be toggled from 0 to 1 and back. When the write to the register is complete, the corresponding FIFO data level is initialized. The recommended procedure for a SPI FIFO data level initialization is: Request FIFO Port A or FIFO Port B level reset by setting Bit 3 in Register 0x17 or Bit 3 in Register 0x19 to Logic 1. The FIFO phase offset, Bits [2:0] in Register 0x17 or Bits [2:0] in Register 0x19 should also be written at the same time to set the desired value of offset between the FIFO write and read pointers. Verify the part acknowledges the request by ensuring Bit 4 in Register 0x17 or Bit 4 in Register 0x19 is set to Logic 1. Remove the request by resetting Bit 3, Register 0x17 or Bit 3, Register 0x19 to 0. The FIFO SPI aligned flag in the Event Flag 0 register, Bit 2 in Register 0x06, is set when the reset of the write pointer has been realized. Bit 4 in Register 0x17 or Bit 4 in Register 0x19 is reset to 0 to indicate which FIFO has generated this flag. Note that the SPI writes to Register 0x17 or Register 0x19 should be done while maintaining a constant value in the FIFO phase offset bits. FIFO Reset Using FRAME Signal The FIFO pointers can also be reset using the FRAME signals. If only one DCI is used, only the FRAMEA signal is used for the FIFO reset. This mode is enabled by setting Bit 6 in Register 0x10. As discussed in the FIFO Synchronization Modes section, the FRAME input is used to initialize the FIFO data level value. When the FRAME signal is asserted high for at least the time interval needed to load the complete data to the four DACs, the write pointer is reset depending on the mode of synchronization chosen:

• Data rate synchronization (default), Bit 6 of Register 0x10, is set to 0. Write pointer reset to FIFO offset phase when read pointer reaches 0.
• FIFO rate synchronization, Bit 6 of Register 0x10, is set to 1. Write pointer reset to FIFO start level on rising edge of FRAME signal. MONITORING THE FIFO STATUS The FIFO initialization and status can be read from Register 0x17. This register provides information about the FIFO initialization method and whether the initialization was successful. The MSB of Register 0x17 is a FIFO warning flag that can optionally trigger a device IRQ. This flag is an indication that the FIFO is close to emptying (FIFO level is 1) or overflowing (FIFO level is 7). This is an indication that the data may soon be corrupted, and action should be taken. The FIFO data level can be read from Register 0x18 at any time. The SPI reported FIFO data level is denoted as a 7-bit thermometer code of the write counter state relative to the absolute read counter being 0. The optimum FIFO data level of four is, therefore, reported as a value of 00001111 in the status register. Note that, depending on the timing relationship between DCI and the main DACCLK, the FIFO level value can be off by a ±1 count. Therefore, it is important to keep the difference between the read and write points to at least two.

more DACs to be synchronized with a system-level reference clock. be synchronized to each other or to a system clock. tighter setup and hold time requirements. typical configuration is shown in Figure 52. Figure 52. Typical Circuit Diagram for Synchronizing Devices with Clock Multiplication Enabled

writing 0xC0 to the sync control register (Register 0x10).

1. Read the sync status register (Register 0x12) and verify that

relative to the sync signal. fDATA = 200 MHz, fSYNC = 100 MHz would be a viable solution. Figure 53. Timing Diagram Required for Synchronizing Two Devices

AD9148 Preliminary Technical Data Rev. PrA | Page 48 of 73 Timing Optimization The SYNC signal is sampled by a version of the DACCLK. If sampling errors are detected, the opposite sampling edge can be selected to improve the sampling point. The sampling edge can be selected by setting Bit 3, Register 0x10 (1 = rising and 0 = falling). The synchronization logic resynchronizes when a phase change between the SYNC signal and the state of the clock generation state machine exceeds a threshold. To mitigate the effects of jitter and prevent erroneous resynchronizations, the relative phase can be averaged. The amount of averaging is set by the Sync Averaging[2:0] bits (Bits[2:0], Register 0x10) and can be set from 1 to 128. The higher the number of averages, the more slowly the device recognizes and resynchronizes to a legitimate phase correction. Generally, the averaging should be made as large as possible while still meeting the allotted resynchronization time interval.

Figure 58. The sampling point of the data bus nominally occurs FRAME signals must be valid throughout this sampling interval. Table 15. Data Port Setup and Hold Times

00 TBD TBD

01 TBD TBD

10 TBD TBD

11 TBD TBD

circuitry. See the Interface Timing Validation section for details. between DCI and DACCLK is shown in Figure 57. Figure 57. Timing Diagram for Input Data Port (Data Rate Mode with Sync On) Table 16. DCI to DACCLK Setup and Hold Times vs. DCI Figure 58. Timing Diagram for Input Data Ports

Preliminary Technical Data AD9148 Rev. PrA | Page 55 of 73 The NCO operating frequency, fNCO, is at the DAC rate. The frequency of the complex carrier signal can be set from dc up to fDAC/2. The frequency tuning word (FTW) is calculated as 322× = DAC CENTER f fFTW The generated quadrature carrier signal is mixed with the I and Q data. The quadrature products are then summed into the I and Q data paths, as shown in Figure 70. When using the fine modulator, the maximum signal bandwidth of 0.8 × fDATA is always achieved. Updating the Frequency Tuning Word The frequency tuning word registers do not get updated immediately upon writing as the other configuration registers do. After loading the FTW registers with the desired values, Bit 2 of Register 0x5A must transition from 0 to 1 for the new FTW to take effect. Phase Offset Adjustment A 16-bit phase offset may be added to the output of the phase accumulator via the serial port. This static phase adjustment results in an output signal that is offset by a constant angle relative to the nominal signal. This allows the user to phase align the NCO output with some external signal, if necessary. This can be especially useful when NCOs of multiple AD9148s are programmed for synchronization. The phase offset allows for the adjustment of the output timing between the devices. The static phase adjustment is sourced from the NCO Phase Offset Word[15:0] value located in Register 0x58 and Register 0x59.

DACCLK rate, most commonly the data input frequency. particularly at higher output frequencies. diagram of the input, along with a recommended drive circuit. of ac coupling capacitors and a differential 100 Ω termination. jitter and fast edge rates to optimize the DAC noise performance. it provides the lowest noise spectral density at the DAC outputs. sampling clock, set the PLL enable bit to 0 (Register 0x0A, Bit 7). source for the internal DACCLK. functions can be found in Register 0x08. Figure 71. Clock Receiver Circuitry and Recommended Drive Circuitry using LVPECL (Left) and LVDS (Right)

enable the auto band select mode by writing 0x80 to Register 0x0A. Put device in manual band select mode.

1. Sweep the VCO band over a range of bands that result in
2. Verify that the PLL is locked and read the VCO control

Table 25. VCO Control Voltage Range Indications

1111 Move to higher VCO band

1101 VCO is operating in the higher end of

1001 VCO is operating with an optimal region

0101 VCO is operating in the lower end of

0001 Move to lower VCO band

AD9148 Preliminary Technical Data Rev. PrA | Page 62 of 73 Reducing LO Leakage and Unwanted Sidebands Analog Devices modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output. This can be done either by using the auxiliary DACs (Register 0x32, Register 0x33, Register 0x36, and Register 0x37) or by using the digital dc offset adjustments (Register 0x2C to Register 0x2F). Using the auxiliary DACs has the advantage that none of the main DAC dynamic range is used for performing the dc offset adjustment. The disadvantage is that the common-mode level of the output signal changes as a function of the auxiliary DAC current. The opposite is true when the digital offset adjustment is used. Good sideband suppression requires both gain and phase matching of the I and Q signals. The phase adjust (Register 0x28 to Register 0x2B) and gain control (Register 0x50 and Register 0x51) registers can be used to calibrate I and Q transmit paths to optimize the sideband suppression. As an alternative to the digital gain scaling, the DAC full-scale output current (Register 0x30, Register 0x31, Register 0x34, and Register 0x35) can also be adjusted to calibrate the I and Q transmit paths; however, changing the DAC full-scale output current affects the common-mode voltage level. For more information on correcting imperfections in IQ modulators to improve RF signal fidelity, refer to Application Note AN-1039.

Preliminary Technical Data AD9148 Rev. PrA | Page 65 of 73 TEMPERATURE SENSOR The AD9148 has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed by Register 0x5E and Register 0x5F. The temperature of the die can be calculated as 9 . 126 ) 46875 ] 0 : 15 [ (−= DieTempTDIE where TDIE is the die temperature in degrees Celsius. The temperature accuracy is ±5°C typical over TBD range. Estimates of the ambient temperature can be made if the power dissipation of the device is known. For example, if the device power dissipation is 800 mW and the measured die temperature is 50°C, then the ambient temperature can be calculated as T A = TDIE – PD × TJA = 50 – 0.8 × 19.1 = 34.7°C where: T A is the ambient temperature in degrees Celsius. TJA is the thermal resistance from junction to ambient of the AD9148 as shown in Table 7. To use the temperature sensor, it must be enabled by setting Bit 0, Register 0x5C to 0. Before the temperature sensor data can be readback, it must be latched by toggling Bit 1, Register 0x5C from 0 to 1. In addition, to get accurate readings, the range control register (Register 0x5D) should be set to 0x02.

• TMS ,test mode select input
• TCK , test clock input
• TDI , test data input
• TDO , test data output The instruction register holds the current instruction used by the TAP controller to decide what to do with the test signals that are received. Most commonly, the content of the instruction register defines to which of the data registers signals should be passed. Table 26 shows the supported instructions, the instruction code, and the data register selected. All instruction codes that are not listed in Table 26 are reserved.

Table 26. Instruction Code Register Definition configuration for the device. The content of the 32-bit IDCODE register is 0x227E51CB. Figure 90. Basic Timing Diagram of the TAP Controller Signals

Table 28. TAP Load and Read Sequence

0 SDIOEN SDOEN

1 SDOEN SDO

2 SDO PLL_LOCK

3 PLL_LOCK IRQ

4 IRQ SDIO, preload

5 SDIO SDIO, current

6 SCLK SCLK, current

7 CSB CSB, current

8 RESET

9 B15_P B15_P

10 B14_P B14_P

11 B13_P B13_P

12 B12_P B12_P

13 B11_P B11_P

14 B10_P B10_P

15 B9_P B9_P

16 B8_P B8_P

17 B7_P B7_P

18 B6_P B6_P

19 B5_P B5_P

20 B4_P B4_P

21 B3_P B3_P

22 B2_P B2_P

23 B1_P B1_P

24 B0_P B0_P

25 A15_P A15_P

26 A14_P A14_P

27 A13_P A13_P

28 A12_P A12_P

29 A11_P A11_P

30 A10_P A10_P

31 A9_P A9_P

32 A8_P A8_P

33 A7_P A7_P

34 A6_P A6_P

35 A5_P A5_P

36 A4_P A4_P

37 A3_P A3_P

38 A2_P A2_P

39 A1_P A1_P

40 A0_P A0_P

41 FRAMEB_P FRAMEB_P

42 DCIB_P DCIB_P

43 FRAMEA_P FRAMEA_P

44 DCIA_P DCIA_P

Preliminary Technical Data AD9148 Rev. PrA | Page 71 of 73 EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9148, certain sequences should be followed. An example start-up routine using the following device configuration is used for this example:

• fDATA = 122.88 MSPS
• Interpolation = 4×, using HB1 = ’00’ and HB2 = ’000’
• Input data = baseband data
• Dual port mode with 1 DCI
• fOUT = 140 MHz
• fREFCLK = 122.88 MHz
• PLL = enabled
• Fine NCO = enabled
• Inverse SINC Filter = disabled
• Synchronization = enabled DERIVED PLL SETTINGS The following PLL settings can be derived from the device configuration:
• fDACCLK = fDATA × Interpolation = 491.52 MHz
• fVCO = 4 × fDACCLK = 1966.08 MHz (1 GHz < fVCO < 2 GHz)
• N1 = fDACCLK/fREFCLK = 4
• N0 = fVCO/fDACCLK = 4 DERIVED NCO SETTINGS The following NCO settings can be derived from the device configuration:
• fOUT = 140 MHz
• fDACCLK = fDATA × Interpolation = 491.52 MHz
• FTW = 140/(491.52) × 232 = 0x48, EAAAAA START-UP SEQUENCE The power clock and register write sequencing for reliable device start-up follows:
• Power up the device (no specific power supply sequence is required)
• Apply stable REFCLK input signal.
• Apply stable DCI input signal.
• Issue hardware reset (optional)
• Configure device registers with the following write sequence: 0x0C → 0xC9 0x0D → 0xD9 0x0A → 0xC0 0x0A → 0x80 0x10 → 0x48 0x14 → 0x40 0x17 → 0x80 0x17 → 0x00 0x19 → 0x80 0x19 → 0x00 0x1C → 0x40 0x1D → 0x00 0x1E → 0x01 0x54 → 0xAA 0x55 → 0xAA 0x56 → 0xEA 0x57 → 0x48 0x5A → 0x01 0x5A → 0x00 DEVICE VERIFICATION SEQUENCE The following device polling can be conducted to verify the device is working properly: Read 0x06, Expect Bit 7 = 0, Bit 6 = 1, Bit 5 = 0, Bit 4 = 1, Bit 2 = 1
• Read 0x12, Expect Bit 6 = 1
• Read 0x18, Expect 0x0F (0x07 is also normal)
• Read 0x1A, Expect 0x0F (0x07 is also normal)

WITH EXCEPTION TO PACKAGE HEIGHT. Figure 92. 196-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]

COMPLIANT TO JEDEC STANDARDS MO-192.

0.80 REF

0.24 REF

Figure 93. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_EP] registered trademarks are the prop erty of their respective owners.