AD9142

AD9142

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 64

Technical content

Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter Data Sheet AD9142 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Very small inherent latency variation: <2 DAC clock cycles Proprietary low spurious and distortion design 6-carrier GSM ACLR = 79 dBc at 200 MHz IF SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF Flexible 16-bit LVDS interface Supports word and byte load Multiple chip synchronization Fixed latency and data generator latency compensation Selectable 2×, 4×, 8× interpolation filter Low power architecture fS/4 power saving coarse mixer Input signal power detection Emergency stop for downstream analog circuitry protection FIFO error detection On-chip numeric control oscillator allows carrier placement anywhere in the DAC Nyquist bandwidth Transmit enable function for extra power saving High performance, low noise PLL clock multiplier Digital gain and phase adjustment for sideband suppression Digital inverse sinc filter Supports single DAC mode Low power: 2.0 W at 1.6 GSPS, 1.7 W at 1.25 GSPS, full operating conditions 72-lead LFCSP

APPLICATIONS

Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment GENERAL DESCRIPTION The AD9142 is a dual, 16-bit, high dynamic range digital-to- analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142 TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital mod- ulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the pro- gramming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142 is available in a 72-lead LFCSP . PRODUCT HIGHLIGHTS 1. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. 2. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. 3. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. 4. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. 5. Programmable transmit enable function allows easy design balance between power consumption and wakeup time.

Rev. 0 | Page 2 of 64 TABLE OF CONTENTS

Rev. 0 | Page 3 of 64

REVISION HISTORY

11/12—Revision 0: Initial Version

Rev. 0 | Page 4 of 64 FUNCTIONAL BLOCK DIAGRAM Figure 1. REF AND BIAS FSADJ REFIO POWER-ON RESET MULTICHIP SYNCHRONIZATION SERIAL INPUT/OUTPUT PORT PROGRAMMING REGISTERS SDIO SCLK CS RESET TXEN IRQ1 IRQ2 DACCLKP DACCLKN REFP/SYNCP REFN/SYNCN CLOCK MULTIPLIER CLK RCVR REF RCVR DAC_CLK LVDS DATA RECEIVER INPUT POWER DETECTION FIFO 8-SAMPLE D15P/D15N D0P/D0N FRAMEP/ FRAMEN DCIP/DCIN INTERFACE CTRL FIFO CTRL INTERP MODE CTRL1 HB1 INTERP MODE CTRL2 HB2 INTERP MODE CTRL3 HB3 DAC_CLK INV SINC GAIN AND PHSE CONTROL DC OFFSET CONTROL OVER-THRESHOLD PROTECTION COMPLEX MODULATION fDAC/4 MOD NCO DAC 1 16-BIT IOUT1P IOUT1N DAC 2 16-BIT IOUT2P IOUT2N GAIN 1 GAIN 2 INTERNAL CLOCK TIMING AND CONTROL LOGIC DAC CLK SYNC AD9142 10930-001

Rev. 0 | Page 5 of 64 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AV DD 3 3 = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 % FSR Gain Error With internal reference −3.2 2 4.7 % FSR Full-Scale Output Current Based on a 10 kΩ external resistor between FSADJ and AVSS 19.06 19.8 +20.6 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.17 1.19 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES DVDD18 1.71 1.8 1.89 V POWER CONSUMPTION 2× Mode fDAC = 491.52 MSPS NCO OFF 700 mW NCO ON 870 mW 4× Mode fDAC = 737.28 MSPS NCO OFF 836 mW NCO ON 1085 mW 4× Mode fDAC = 983.04 MSPS NCO OFF 1030 mW NCO ON 1365 mW 8× Mode fDAC = 1600 MSPS NCO OFF 1315 mW NCO ON 1815 mW Phase-Lock Loop 70 mW Inverse Sinc fDAC = 1474.56 MSPS 113 mW Reduced Power Mode (Power Down) 96.6 mW AVDD33 1.5 mA CVDD18 42.3 mA DVDD18 8.6 mA OPERATING RANGE −40 +25 +85 °C

Rev. 0 | Page 6 of 64 DIGITAL SPECIFICATIONS TMIN to TMAX, AV DD 3 3 = 3.3 V, DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input Logic High DVDD18 = 1.8 V 1.2 V Logic Low DVDD18 = 1.8 V 0.6 V CMOS OUTPUT LOGIC LEVEL Output Logic High DVDD18 = 1.8 V 1.4 V Logic Low DVDD18 = 1.8 V 0.4 V LVDS RECEIVER INPUTS Input Voltage Range VIA or VIB 825 1675 mV Input Differential Threshold VIDTH Data and FRAME inputs −100 +100 mV DCI input −225 +225 mV Input Differential Hysteresis VIDTHH to VIDTHL 20 mV Receiver Differential Input Impedance RIN 120 Ω DAC UPDATE RATE 1600 MSPS DAC Adjusted Update Rate 2× interpolation 250 MSPS DAC CLOCK INPUT (DACCLKP , DACCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage Self biased input, ac-coupled 1.25 V REFCLK/SYNCCLK INPUT (REFP/SYNCP, REFN/SYNCN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V Input Clock Frequency 1 GHz ≤ fVCO ≤ 2.1 GHz 450 MHz SERIAL PORT INTERFACE Maximum Clock Rate SCLK 40 MHz Minimum Pulse Width High tPWH 12.5 ns Low tPWL 12.5 ns Setup Time tDS SDIO to SCLK 1.5 ns Hold Time tDH SDIO to SCLK 0.68 ns Setup Time tDCSB CS to SCLK 2.38 1.4 ns

Rev. 0 | Page 7 of 64 DAC LATENCY SPECIFICATIONS TMIN to TMAX, AV DD 3 3 = 3.3 V, DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, FIFO level is set to 4 (half of the FIFO depth), unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit WORD INTERFACE MODE Fine/coarse modulation, inverse sinc, gain/phase compensation off 2× Interpolation 134 DACCLK cycles 4× Interpolation 244 DACCLK cycles 8× Interpolation 481 DACCLK cycles BYTE INTERFACE MODE Fine/coarse modulation, inverse sinc, gain/phase compensation off 2× Interpolation 145 DACCLK cycles 4× Interpolation 271 DACCLK cycles 8× Interpolation 506 DACCLK cycles INDIVIDUAL FUNCTION BLOCKS Modulation Fine 17 DACCLK cycles Coarse 10 DACCLK cycles Inverse Sinc 20 DACCLK cycles Phase Compensation 12 DACCLK cycles Gain Compensation 16 DACCLK cycles LATENCY VARIATION SPECIFICATIONS1 Table 4. Parameter Min Typ Max Unit DAC LATENCY VARIATION SYNC Off 2 DACCLK cycles SYNC On 1 DACCLK cycles 1 DAC latency is defined as the elapsed time from a data sample clocked at the input to the AD9142 until the analog output begins to change. AC SPECIFICATIONS TMIN to TMAX, AV DD 3 3 = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) −14 dBFS single tone fDAC = 737.28 MSPS fOUT = 200 MHz BW = 125 MHz 85 dBc BW = 270 MHz 80 dBc fDAC = 983.04 MSPS fOUT = 200 MHz BW = 360MHz 85 dBc fDAC = 1228.8 MSPS fOUT = 280 MHz BW = 200MHz 85 dBc BW = 500MHz 75 dBc fDAC = 1474.56 MSPS BW = 737MHz fOUT = 10 MHz 85 dBc BW = 400MHz fOUT = 280 MHz 80 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) −6 dBFS each tone fDAC = 737.28 MSPS fOUT = 200 MHz 80 dBc fDAC = 983.04 MSPS fOUT = 200 MHz 82 dBc fDAC = 1228.8 MSPS fOUT = 280 MHz 80 dBc fDAC = 1474.56 MSPS fOUT = 10 MHz 85 dBc fOUT = 280 MHz 79 dBc

Rev. 0 | Page 8 of 64 Parameter Test Conditions/Comments Min Typ Max Unit NOISE SPECTRAL DENSITY (NSD) Eight-tone, 500 kHz tone spacing fDAC = 737.28 MSPS fOUT = 200 MHz −160 dBm/Hz fDAC = 983.04 MSPS fOUT = 200 MHz −161.5 dBm/Hz fDAC = 1228.8 MSPS fOUT = 280 MHz −164.5 dBm/Hz fDAC = 1474.56 MSPS fOUT = 10 MHz −166 dBm/Hz fOUT = 280 MHz −162.5 dBm/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR) Single carrier fDAC = 983.04 MSPS fOUT = 200 MHz 81 dBc fDAC = 1228.8 MSPS fOUT = 20 MHz 83 dBc fOUT = 280 MHz 80 dBc fDAC = 1474.56 MSPS fOUT = 20 MHz 81 dBc fOUT = 280 MHz 80 dBc W-CDMA SECOND (ACLR) Single carrier fDAC = 983.04 MSPS fOUT = 200 MHz 85 dBc fDAC = 1228.8 MSPS fOUT = 20 MHz 86 dBc fOUT = 280 MHz 86 dBc fDAC = 1474.56 MSPS fOUT = 20 MHz 86 dBc fOUT = 280 MHz 85 dBc OPERATING SPEED SPECIFICATIONS Table 6. Interpolation Factor DVDD18, CVDD18 = 1.8 V ± 5% DVDD18, CVDD18 = 1.8 V ± 2% or 1.9 V ± 5% fINTERFACE (Mbps) Max fDAC (Mbps) Max fINTERFACE (Mbps) Max fDAC (Mbps) Max 2× 250 500 250 500 4× 250 1000 250 1000 8× 187.5 1500 200 1600

thermal, and mechanical connection to the board. Table 8. Thermal Resistance

Figure 2. Pin Configuration Table 9. Pin Function Descriptions 1 CVDD18 1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution. 2 REFP/SYNCP PLL Reference Clock Input, Positive. 3 REFN/SYNCN PLL Reference Clock Input, Negative. 4 CVDD18 1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution. 5 RESET Reset, Active Low. CMOS levels with respect to DVDD18. Recommended reset pulse length is 1 μs. selectable actions in the DAC. See Register 0x43 in Table 77 for details. 8 FRAMEP Frame Input, Positive. 9 FRAMEN Frame Input, Negative. 10 D15P Data Bit 15 (MSB), Positive. 11 D15N Data Bit 15 (MSB), Negative. 12 DVDD18 1.8 V Digital Supply. Pin 12 supplies the power to the digital core and digital data ports. 13 D14P Data Bit 14, Positive. 14 D14N Data Bit 14, Negative. 15 D13P Data Bit 13, Positive. 16 D13N Data Bit 13, Negative. 17 D12P Data Bit 12, Positive. 18 D12N Data Bit 12, Negative. 20 D11P Data Bit 11, Positive. 21 D11N Data Bit 11, Negative. 22 D10P Data Bit 10, Positive. 23 D10N Data Bit 10, Negative. 24 D9P Data Bit 9, Positive.

1. EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND

AND MECHANICAL CONNECTION TO THE BOARD.

1. EPAD IS THE GROUND CONNECTION FOR CVSS AND DVSS.

Rev. 0 | Page 11 of 64 Pin No. Mnemonic Description 25 D9N Data Bit 9, Negative. 26 D8P Data Bit 8, Positive. 27 D8N Data Bit 8, Negative. 28 DCIP Data Clock Input, Positive. 29 DCIN Data Clock Input, Negative. 30 D7P Data Bit 7, Positive. 31 D7N Data Bit 7, Negative. 32 D6P Data Bit 6, Positive. 33 D6N Data Bit 6, Negative. 34 D5P Data Bit 5, Positive. 35 D5N Data Bit 5, Negative. 36 DVDD18 1.8 V Digital Supply. Pin 36 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. 37 D4P Data Bit 4, Positive. 38 D4N Data Bit 4, Negative. 39 D3P Data Bit 3, Positive. 40 D3N Data Bit 3, Negative. 41 D2P Data Bit 2, Positive. 42 D2N Data Bit 2, Negative. 43 DVDD18 1.8 V Digital Supply. Pin 43 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. 44 D1P Data Bit 1, Positive. 45 D1N Data Bit 1, Negative. 46 D0P Data Bit 0 (LSB), Positive. 47 D0N Data Bit 0 (LSB), Negative. 48 DVDD18 1.8 V Digital Supply. Pin 48 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. 49 DVDD18 1.8 V Digital Supply. Pin 49 supplies power to the digital core, digital data ports, serial port input/output pins, RESET, IRQ1, and IRQ2. 50 IRQ2 Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a 10 kΩ resistor. 51 IRQ1 First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a 10 kΩ resistor. 52 SDIO Serial Port Data Input/Output. CMOS levels with respect to DVDD18. 53 SCLK Serial Port Clock Input. CMOS levels with respect to DVDD18. 54 CS Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18). 55 AVDD33 3.3 V Analog Supply. 56 IOUT2P QDAC Positive Current Output. 57 IOUT2N QDAC Negative Current Output. 58 AVDD33 3.3 V Analog Supply. 59 CVDD18 1.8 V Clock Supply. Supplies clock receivers and clock distribution. 60 CVDD18 1.8 V Clock Supply. Supplies clock receivers and clock distribution. 61 DACCLKN DAC Clock Input, Negative. 62 DACCLKP DAC Clock Input, Positive. 63 CVDD18 1.8 V Clock Supply. Supplies clock receivers and clock distribution. 64 CVDD18 1.8 V Clock Supply. Supplies clock receivers and clock distribution. 65 AVDD33 3.3 V Analog Supply. 66 IOUT1N IDAC Negative Current Output. 67 IOUT1P IDAC Positive Current Output. 68 AVDD33 3.3 V Analog Supply. 69 FSADJ Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS. 70 REFIO Voltage Reference. Nominally 1.2 V output. Decouple REFIO to AVSS. 71 CVDD18 1.8 V Clock Supply. Pin 71 supplies the clock receivers, clock multiplier, and clock distribution. 72 CVDD18 1.8 V Clock Supply. Pin 72 supplies the clock receivers, clock multiplier, and clock distribution. EPAD Exposed Pad. The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical, thermal, and mechanical connection to the board.

Figure 27. CVDD18, AVDD33 Current vs. fDAC

Rev. 0 | Page 17 of 64 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset Error Offset error is the deviation of the output current from the ideal of 0 mA. For IOUT1P , 0 mA output is expected when all inputs are set to 0. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in ppm of full- scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, the interpoloation filters reject energy in this band. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of f DATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

read/write access to all registers that configure the AD9142. share a single pin input/output (SDIO). Figure 28. Serial Port Interface Pins There are two phases to a communication cycle with the AD9142. the starting register address for the following data transfer. serial port timing to the initial state of the instruction cycle. instruction bits of the current I/O operation. the frequency tuning word (FTW) update bit is set. The instruction byte contains the information shown in Table 10. Table 10. Serial Port Instruction Word or a write data transfer occurs after the instruction word write. addresses based on the SPI_LSB_FIRST bit. of SCLK. All data is driven out on the falling edge of SCLK. The SDIO pin is a bidirectional data line. (Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0). for each data byte of the multibyte communication cycle. for each data byte of the multibyte communication cycle. address written toward 0xFF for multibyte I/O operations.

53 SCLK

52 SDIO

setup and hold times for each delay tap. Table 13. Setup and Hold Times when it is on the right side of the clock edge.

• f DCI = 200 MHz
• Delay setting = 0 The shadow area in Figure 36 is the interface setup and hold time window set to 0. To optimize the interface timing, this window must be placed in the middle of the data transitions. Because the input is double data rate, the available data period is 2.5 ns. Therefore, the optimal data bus delay, with respect to the DCI at the data source, can be calculated as ns63.025.188.1 PERIODDATAHS DELAY tttt SPI Sequence to Enable Delay Line-Based Mode It is recommended that the following SPI sequence be used to enable the delay line-based mode: 1. 0x79 → 0x18 /* Configure Data Interface */ 2. 0x5E → 0x00 /* Delay setting 0 */ 0x5F → 0x00 3. 0x5F[3] → 1b /* Enable the delay line */

Figure 36. Example of Interfacing Timing in the Delay Line-Based Mode

and the fractional FIFO level. Table 14. Examples of FIFO Level Configuration interpolation, the maximum allowed for x is 7.

• Serial port (SPI) initiated FIFO reset.
• Frame initiated FIFO reset. SERIAL PORT INITIATED FIFO RESET A SPI initiated FIFO reset is the most common method to reset the FIFO. To initialize the FIFO level through the serial port, toggle FIFO_SPI_RESET_REQUEST (Register 0x25[0]) from 0 to 1 and back to 0. When the write to this register is complete, the FIFO level is initialized to the requested FIFO level and the readback of FIFO_SPI_RESET_ACK (Register 0x25[1]) is set to 1. The FIFO level readback, in the same format as the FIFO level request, should be within ±1 DACCLK cycle of the requested level. For example, if the requested value is 0x40 in 4× interpolation, the readback value should be one of the following: 0x33, 0x40, or 0x41. The range of ±1 DACCLK cycle indicates the default DAC latency uncertainty from power-on to power-on without turning on synchronization. The recommended procedure for a serial port FIFO reset is as follows: 1. Configure the DAC in the desired interpolation mode (Register 0x28[1:0]). 2. Ensure that the DACCLK and DCI are running and stable at the clock inputs. 3. Program Register 0x23 to the customized value, if the desired value is not 0x40. 4. Request the FIFO level reset by setting Register 0x25[0] to 1. 5. Verify that the part acknowledges the request by setting Register 0x25[1] to 1. 6. Remove the request by setting Register 0x25[0] to 0. 7. Verif y that the part drops the acknowledge signal by setting Register 0x25[1] to 0. 8. Read back Register 0x24 multiple times to verify that the actual FIFO level is set to the requested level and that the readback values are stable. By design, the readback should be within ±1 DACCLK around the requested level. FRAME INITIATED FIFO RESET The frame input has two functions. One function is to indicate the beginning of a byte stream in the byte interface mode, as discussed in the Data Interface section. The other function is to initialize the FIFO level by asserting the frame signal high for at least the time interval required to load complete data to the I and QDACs. This corresponds to one DCI period in word mode and two DCI periods in byte mode. Note that this requirement of the frame pulse length is longer than that of the frame signal when it serves only to assemble the byte stream. The device accepts either a continuous frame or a one shot frame signal. In the continuous reset mode, the FIFO responds to every valid frame pulse and resets itself. In the one shot reset mode, the FIFO responds only to the first valid frame pulse after the FRAME_RESET_MODE bits (Register 0x22[1:0]) are set. Therefore, even with a continuous frame input, the FIFO resets one time only; this prevents the FIFO from toggling between the two states from periodic resets. The one shot frame reset mode is the default and the recommended mode.

Rev. 0 | Page 25 of 64 The recommended procedure for a frame initiated FIFO reset is as follows: 1. Configure the DAC in the desired interpolation mode (Register 0x28[1:0]). 2. Ensure that the DACCLK and DCI are running and stable at the clock inputs. 3. Program Register 0x23 to the customized value, if the desired value is not 0x40. 4. Configure the FRAME_RESET_MODE bits (Register 0x22[1:0])to 00b. 5. Choose whether continuous or one shot mode is desired by writing 0 or 1 to EN_CON_FRAME_RESET (Register 0x22[2]). 6. Toggle the frame input from 0 to 1 and back to 0. The pulse width needs to be longer than the minimum requirement. a. If the frame input is a continuous clock, turn on the signal. 7. Read back FRAME_RESET_ACK, Register 0x22[3], to verify that the reset is complete. 8. Read back Register 0x24 multiple times to verify that the actual FIFO level is set to the requested level and the readback values are stable. By design, the readback should be within ±1 DACCLK around the requested level. Monitoring the FIFO Status The real-time FIFO status can be monitored from the SPI Register 0x24 and reflects the real-time FIFO depth after a FIFO reset. Without timing drifts in the system, this readback should not change from that which resulted from the FIFO reset. When there is a timing drift or other abnormal clocking situation, the FIFO level readback can change. However, as long as the FIFO does not overflow or underflow, there is no error in data trans- mission. Three status bits in Register 0x06, Bits[2:0], indicate if there are FIFO underflows, overflows, or similar situations. The status of the three bits can be latched and used to trigger hardware interrupts, IRQ1 and IRQ2. To enable latching and interrupts, configure the corresponding bits in Register 0x03 and Register 0x04.

Table 16. Half-Band Filter 2 Coefficient Table 17. Half-Band Filter 3 Coefficient quadrature signal to the desired DAC output frequency.

• Coarse (fS/4) modulation
• Fine (NCO) modulation fS/4 Modulation The fS/4 modulation is a convenient and low power modulation mode to translate the input baseband frequency to a fixed fS/4 IF frequency, fS being the DAC sampling rate. When modulation frequencies other than this frequency are required, the NCO modulation mode must be used. NCO Modulation The NCO modulation mode makes use of a numerically controlled oscillator (NCO), a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block diagram of the digital modulator is shown in Figure 45. The NCO modulation allows the DAC output signal to be placed anywhere in the output spectrum with very fine frequency resolution.

Figure 45. NCO Modulator Block Diagram TUNING_WORD[31:0] in Register 0x31 through Register 0x34. signal can be set from dc up to ±0.5 × fNCO. and Q data paths, as shown in Figure 45. FIFO reset, the NCO update can be triggered in two ways.

• SPI initiated update
• Frame initiated update COSINE SINE I DATA IN Q DATA IN I DATA OUT Q DATA OUT FTW[31:0] NCO PHASE[15:0] 10930-050

shot mode (EN_CON_FRAME_RESET, Register 0x22[2] = 0). information to generate a valid frame pulse.

• The application requirements of the input data rate
• The interpolation ratio
• The output signal center frequency
• The output signal bandwidth Given these four parameters, the first step in configuring the datapath is to verify that the device supports the desired input data rate, the DAC sampling rate, and the bandwidth requirements. After this verification, the modes of the interpolation filters can be chosen. If the output signal center frequency is different from the baseband input center frequency, additional frequency offset requirements are determined and applied with on-chip digital modulation. DIGITAL QUADRATURE GAIN AND PHASE ADJUSTMENT The digital quadrature gain and phase adjustment function enables compensation of the gain and phase imbalance of the I and Q paths caused by analog mismatches between DAC I/Q outputs, quadrature modulator I/Q baseband inputs, and DAC/modulator interface I/Q paths. The undesired imbalances cause unwanted sideband signal to appear at the quadrature modulator output with significant energy. Tuning the quadrature gain and phase adjust values optimizes image rejection in single sideband radios. Quadrature Gain Adjustment Ordinarily, the I and Q channels have the same gain or signal magnitude. The quadrature gain adjustment is used to balance the gain between the I and Q channels. The digital gain of the I and Q channels can be adjusted independently through two 6-bit registers, IDAC_GAIN_ADJ (Register 0x3F[5:0]) and QDAC_GAIN_ADJ (Register 0x40[5:0]). The range of the adjustment is [0, 2] or [−∞, 6 dB] with a step size of 2−5 (−30 dB). The default setting is 0x20, corresponding to a gain equal to 1 or 0 dB. Quadrature Phase Adjustment Under normal circumstances, I and Q channels have an angle of precisely 90 degrees between them. The quadrature phase adjust- ment is used to change the angle between the I and Q channels. IQ_PHASE_ADJ[12:0] (Register 0x37 and Register 0x38) provide an adjustment range of ±14 degrees with a resolution of 0.0035 degrees. If the original angle is precisely 90 degrees, setting IQ_PHASE_ADJ[12:0] to 0x0FFF adds approximately 14 degrees between I and QDAC outputs, creating an angle of 104 degrees between the channels. Likewise, if the original angle is precisely 90 degrees, setting IQ_PHASE_ADJ[12:0] to 0x1000 adds approximately −14 degrees between the I and QDAC outputs, creating an angle of 76 degrees between the channels. DC OFFSET ADJUSTMENT The dc value of the I datapath and the Q datapath can be controlled independently by adjusting the values in the two 16-bit registers, IDAC_DC_OFFSET, Bits[15:0] and QDAC_DC_OFFSET, Bits[15:0] (Register 0x3B through Register 0x3E). These values are added directly to the datapath values. Care should be taken not to overrange the transmitted values. As shown in Figure 46, the DAC offset current varies as a function of the I/QDAC_DC_OFFSET values. Figure 46 shows the nominal current of the positive node of the DAC output, IOUTP, when the digital inputs are fixed at midscale (0x0000, twos complement data format) and the DAC offset value is swept from 0x0000 to 0xFFFF. Because IOUTP and IOUTN are complementary current outputs, the sum of IOUTP and IOUTN is always 20 mA.

Figure 46. DAC Output Currents vs. DAC Offset Value

Rev. 0 | Page 31 of 64 TRANSMIT ENABLE FUNCTION The transmit enable (TXEN) function provides the user a hardware switch of the DAC output. The function accepts a CMOS signal via Pin 6 (TXEN). When this signal is detected high, the transmit path is enabled and the DAC transmits the data normally. When this signal is detected low, one of the three actions related to the DAC output is triggered. 1. The DAC output is gradually attenuated from full scale gain to 0. The attenuation step size is set in Register 0x42[5:0]. 2. The DAC is put in sleep mode and the output current is turned off. Other parts of the DAC are still running in this mode. 3. The DAC is put in power-down mode. In this mode, not only the DAC output current is turned off but the rest of the DAC is powered down. This minimizes the power consumption of the DAC when the data is not transmitting but it takes a bit longer than the first two modes to start to re-transmit data due to the device power-up time. The TXEN function also provides a gain ramp-up function that lets the user turn on the DAC output gradually when the TXEN signal switches from low to high. The ramp-up gain step can be configured using Register 0x41[5:0]. Although all of these actions can be taken through SPI writes, TXEN provides a much faster way to turn on and off the DAC output. The response time of a SPI write command is dominated by the SPI port communication time. This feature is useful when the user must turn off the DAC very quickly. DIGITAL FUNCTION CONFIGURATION Each of the digital gain and phase adjust functions and the inverse sinc filter can be enabled and adjusted independently. The pipeline latencies these blocks add into the data path are different between enabled and disabled. If fixed DAC pipeline latency is desired during operation, leave these functions always on or always off after initial configuration. The digital dc adjust function is always on. The default value is 0; that is, there is no additional dc offset. The pipeline latency that this block adds is a constant, no matter the value of the dc offset. There is also a latency difference between using and not using the input signal power detection and protection function. Therefore, to keep the overall latency fixed, leave this function always on or always off after the initial configuration.

A DAC introduces a variation of pipeline latency to a system. multiple DAC outputs varies from power-on to power-on.

• The phase of DAC internal clocks
• The FIFO level
• The alignment of the input data VERY SMALL INHERENT LATENCY VARIATION The innovative architecture of the AD9142 minimizes the inherent latency variation. The worst-case variation in the AD9142 is two DAC clock cycles. For example, in the case of a 1.5 GHz sample rate, the variation is less than 1.4 ns under any scenario. Therefore, without turning on the synchronization engine, the DAC outputs from multiple AD9142 devices are guaranteed to be aligned within two DAC clock cycles, regardless of the timing between the DCI and the DACCLK. No additional clocks are required to achieve this accuracy. The user must reset the FIFO in each DAC device through the SPI at start-up. Therefore, the AD9142 can decrease the complexity of system design in multi transmit channel applications. Note the alignment of the DCI signals in the design. The DCI is used as a reference in the AD9142 design to align the FIFO and the phase of internal clocks in multiple parts. The achieved DAC output alignment depends on how well the DCIs are aligned at the input of each device. The equation below is the expression of the worst-case DAC output alignment accuracy in the case of DCI mismatches. tSK (OUT) = tSK (DCI) + 2/fDAC where: tSK (OUT) is the worst case skew between the DAC output from two AD9142 devices. tSK (DCI) is the skew between two DCIs at the DCI input of the two AD9142 devices. fDAC is the DACCLK frequency. The better the alignment of the DCIs, the smaller is the overall skew between two DAC outputs. FURTHER REDUCING THE LATENCY VARIATION For applications that require finer synchronization accuracy (DAC latency variation < 2 DAC clock cycles), the AD9142 has a provision for enabling multiple devices to be synchronized to each other within a single DAC clock cycle. To further reduce the latency variation in the DAC, the synchronization machine needs to be turned on and two external clocks (frame and sync) need to be generated in the system and fed to all the DAC devices. Set Up and Hold Timing Requirement The sync clock (fSYNC) serves as a reference clock in the system to reset the clock generation circuitry in multiple AD9142 devices simultaneously. Inside the DAC, the sync clock is sampled by the DACCLK to generate a reference point for aligning the internal clocks, so there is a setup and hold timing requirement between the sync clock and the DAC clock. If the user adopts the continuous frame reset mode, that is, the FIFO and sync engine periodically reset, the timing requirements between the sync clock and the DAC clock must be met. Otherwise, the device can lose lock and corrupt the output. In the one shot frame reset mode, it is still recommended that this timing be met at the time when the sync routine is run because not meeting the timing can degrade the sync alignment accuracy by one DAC cycle, as shown in Table 19. For users who want to synchronize the device in a one-shot manner and continue to monitor the synchronization status, the AD9142 provides a sync monitoring mode. It provides a continuous sync and frame clock to synchronize the part once and ignore the clock cycles after the first valid frame pulse is detected. In this way, the user can monitor the sync status without periodically resynchronizing the device; to engage the sync monitoring mode, set Register 0x22[1:0] (FRAME_RESET_ MODE) to 11b.

Table 19. Sync Clock and DAC Clock Setup and Hold Times

specification, as listed in Table 2. The frame clock resets the FIFO in multiple AD9142 devices. cycle in the word mode and two DCI cycles in the byte mode. fDATA or slower by a factor of 2n, n being an integer (1, 2, 3…). Table 20. Frame Clock Speed and Pulse Width Requirement cycle and byte mode = two DCI cycles. other than the regular start-up procedure sequence. see the DAC Latency and System Skews section.

1. Configure the DAC interpolation mode and, if NCO is

used, configure t h e N C O F T W.

1. Set up the DAC data interface according to the procedure
2. Choose the appropriate mode in FRAME_RESET_MODE.

a. If NCO is not used, choose FIFO only mode.

1. Configure Bit 2 in Register 0x22 for continuous or one shot

reset mode. One shot reset mode is recommended.

1. Ensure that the DACCLK, DCI, and sync clock to all of the

AD9142 devices are running and stable.

1. Enable the sync engine by writing 1 to Register 0x21[0].
2. Send a valid frame pulse(s) to all of the AD9142 devices.
3. Verif y that the frame pulse is received by each device by

reading back Register 0x22[3]. All the readback values are 1. At this point, the devices should be synchronized. 2× interpolation is supported for synchronization with PLL on.

1. Set up the PLL according to the procedure in the Clock

Multiplication section and ensure that the PLL is locked.

1. Configure the DAC interpolation mode and, if NCO is

used, configure t h e N C O F T W.

1. Set up the DAC data interface according to the procedure
2. Choose the appropriate mode in FRAME_RESET_MODE.

a. If NCO is not used, choose the FIFO only mode.

1. Configure Bit 2 in Register 0x22 for continuous or one shot

reset mode. One shot reset mode is recommended.

1. Ensure that DACCLK, DCI, and sync clock to all of the
2. Enable the sync engine by writing 1 to Register 0x21[0].
3. Send a valid frame pulse(s) to all of the AD9142 devices.
4. Verif y that the frame pulse is received by each device by

reading back Register 0x22[3]. All the readback values are 1. At this point, the devices should be synchronized.

temperature code readback is shown in Figure 50. Figure 50. Die Temperature vs. Die Temperature Code Readback TA is the ambient temperature in degrees Celsius. temperature control register (Register 0x1C) should be set to 0x03.

recommended settings for these parameters. Table 21. PLL Settings 1.0 GHz to 2.1 GHz covered in 64 overlapping frequency bands. operating temperature affect the actual band frequency range. be determined for each individual device. The device has an automatic VCO band select feature on chip. that determines the optimal VCO band setting for the device. Figure 53. PLL Lock Range for a Typical Device

1. Configure the loop divider and the VCO divider registers

for the desired divide ratios.

1. Set 00111b to PLL charge pump current and 111b to PLL

loop bandwidth for the best performance.

1. Set the PLL mode to manual using Register 0x12[6] = 1b.
2. Enable the PLL using Register 0x12[7] = 1b.
3. Set the PLL mode to automatic using Register 0x12[6] = 0b.
4. Enable the PLL using Register 0x12[7] = 1b.
5. Configure the loop divider and the VCO divider registers

for the desired divide ratios.

1. Set 00111b to PLL charge pump current and 111b to PLL

loop bandwidth for the best performance.

1. Set the PLL mode to manual using Register 0x12[6] = 1b.
2. Enable the PLL using Register 0x12[7] = 1b.
3. Enable the PLL one more time using Register 0x12[7] = 1b.

Rev. 0 | Page 40 of 64 REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the local oscillator (LO) frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output using the digital dc offset adjustments (Register 0x3B through Register 0x3E). Effective sideband suppression requires both gain and phase matching of the I and Q signals. The I/Q phase adjust registers (Register 0x37 and Register 0x38) and the DAC FS adjust registers (Register 0x18 through Register 0x1B) can be used to calibrate the I and Q transmit paths to optimize sideband suppression. For more information about suppressing LO leakage and sideband image, refer to Application Note AN-1039, Correcting Imperfections in IQ Modulators to Improve RF Signal Fidelity and Application Note AN-1100, Wireless Transmitter IQ Balance and Sideband Suppression from the Analog Devices website.

Rev. 0 | Page 41 of 64 EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9142, certain sequences must be followed. This section shows an example start-up routine. Device Configuration and Start-Up Sequence

• fDATA = 200 MHz, interpolation is 8×.
• Input data is baseband data.
• fOUT = 350 MHz.
• PLL is enabled, fREF = 200 MHz.
• Fine NCO is enabled, inverse sinc filter is enabled.
• A delay line-based mode is used with an interface delay setting of 0. Derived PLL Settings The following PLL settings can be derived from the device configuration:
• fDAC = 200 × 8 = 1600 MHz.
• fVCO= fDAC = 1600 MHz (1 GHz < fVCO < 2 GHz).
• VCO divider = fVCO/fDAC = 1.
• Loop divider = fDAC/fREF = 8. Derived NCO Settings The following NCO settings can be derived from the device configuration:
• fDAC = 200 × 8 = 1600 MHz.
• fCARRIER = fOUT = 350 MHz.
• FTW = fCARRIER/fDAC × 232 = 0x38000000. Start-Up Sequence 1. Power up the device (no specific power supply sequence is required). 2. Apply stable DAC clock. 3. Apply stable DCI clock. 4. Feed stable input data. 5. Issue H/W reset (optional). /* Device configuration register write sequence. Must be written in sequence for every device after reset*/ 0x00 → 0x20 /* Issue software reset */ 0x20 → 0x01 /* Device Startup Configuration */ 0x79 → 0x18 /* Device Startup Configuration */ 0x80 → 0xAD /* Device Startup Configuration */ 0xE1 → 0x1A /* Device Startup Configuration */ /* Configure PLL */ 0x14 → 0xE3 /* Configure PLL loop BW and charge pump current */ 0x15 → 0xC2 /* Configure VCO divider and Loop divider */ 0x12 → 0xC0 /*Enable the PLL */ 0x12 → 0x80 /* Configure Data Interface */ 0x5E → 0x00 /* Delay setting 0 */ 0x5F → 0x08 /* Enable the delay line */ /* Configure Interpolation filter */ 0x28 → 0x03 /* 8× interpolation */ /* Reset FIFO */ 0x25 → 0x01 Read 0x25[1] /* Expect 1b if the FIFO reset is complete */ Read 0x24 /* The readback should be one of the three values: 0x37, 0x40, or 0x41 */ /* Configure NCO */ 0x27→ 0x40 /* Enable NCO */ 0x31 → 0x00 0x32 → 0x00 0x33 → 0x00 0x34 → 0x38 0x30 → 0x01 Read 0x30[1] /* Expect 1b if the NCO update is complete */ /* Enable Inverse SINC filter */ 0x27 → 0xC0 /* Power up DAC outputs */ 0x01 → 0x00

Table 22. Device Configuration Register Map

Rev. 0 | Page 43 of 64 0x28 INTERPOLATION_ CTRL [7:0] Reserved INTERPOLATION_MODE 0x00 RW 0x29 OVER_ THRESHOLD_ CTRL0 [7:0] THRESHOLD_LEVEL_REQUEST_LSB 0x00 RW 0x2A OVER_ THRESHOLD_ CTRL1 [7:0] Reserved THRESHOLD_LEVEL_REQUEST_MSB 0x00 RW 0x2B OVER_ THRESHOLD_ CTRL2 [7:0] ENABLE_ PROTECTION IQ_DATA_ SWAP Reserved SAMPLE_WINDOW_LENGTH 0x00 RW 0x2C INPUT_POWER_ READBACK_LSB [7:0] INPUT_POWER_READBACK_LSB 0x00 R 0x2D INPUT_POWER_ READBACK_MSB [7:0] Reserved INPUT_POWER_READBACK_MSB 0x00 R 0x30 NCO_CTRL [7:0] Reserved NCO_FRAME_ UPDATE_ACK SPI_NCO_ PHASE_RST_ ACK SPI_NCO_ PHASE_ RST_REQ Reserved NCO_SPI_ UPDATE_ACK NCO_SPI_ UPDATE_REQ 0x00 RW 0x31 NCO_FREQ_ TUNING_ WORD0 [7:0] NCO_FTW0 0x00 RW 0x32 NCO_FREQ_ TUNING_ WORD1 [7:0] NCO_FTW1 0x00 RW 0x33 NCO_FREQ_ TUNING_ WORD2 [7:0] NCO_FTW2 0x00 RW 0x34 NCO_FREQ_ TUNING_ WORD3 [7:0] NCO_FTW3 0x10 RW 0x35 NCO_PHASE_ OFFSET0 [7:0] NCO_PHASE_OFFSET_LSB 0x00 RW 0x36 NCO_PHASE_ OFFSET1 [7:0] NCO_PHASE_OFFSET_MSB 0x00 RW 0x37 IQ_PHASE_ ADJ0 [7:0] IQ_PHASE_ADJ_LSB 0x00 RW 0x38 IQ_PHASE_ ADJ1 [7:0] Reserved IQ_PHASE_ADJ_MSB 0x00 RW 0x3B IDAC_DC_ OFFSET0 [7:0] IDAC_DC_OFFSET_LSB 0x00 RW 0x3C IDAC_DC_ OFFSET1 [7:0] IDAC_DC_OFFSET_MSB 0x00 RW 0x3D QDAC_DC_ OFFSET0 [7:0] QDAC_DC_OFFSET_LSB 0x00 RW 0x3E QDAC_DC_ OFFSET1 [7:0] QDAC_DC_OFFSET_MSB 0x00 RW 0x3F IDAC_GAIN_ADJ [7:0] Reserved IDAC_GAIN_ADJ 0x20 RW 0x40 QDAC_GAIN_ ADJ [7:0] Reserved QDAC_GAIN_ADJ 0x20 RW 0x41 GAIN_STEP_ CTRL0 [7:0] Reserved RAMP_UP_STEP 0x01 RW 0x42 GAIN_STEP_ CTRL1 [7:0] DAC_OUTPUT_ STATUS DAC_OUTPUT_ ON RAMP_DOWN_STEP 0x01 RW 0x43 TX_ENABLE_ CTRL [7:0] Reserved TXENABLE_ GAINSTEP_EN TXENABLE_ SLEEP_EN TXENABLE_ POWER_ DOWN_EN 0x07 RW 0x44 DAC_OUTPUT_ CTRL [7:0] DAC_OUTPUT_ CTRL_EN Reserved FIFO_WARNING_ SHUTDOWN_EN OVER- THRESHOLD_ SHUTDOWN_ EN Reserved FIFO_ERROR_ SHUTDOWN_ EN 0x8F RW 0x5E DATA_RX_CTRL0 [7:0] DLY_TAP_LSB 0xFF RW 0x5F DATA_RX_CTRL1 [7:0] Reserved DLYLINE_EN DLY_TAP_MSB 0x07 RW 0x79 DEVICE_ CONFIG0 [7:0] DEVICE_CONFIGURATION0 0x00 RW 0x7F Version [7:0] Version 0x05 R 0x80 DEVICE_ CONFIG1 [7:0] DEVICE_CONFIGURATION1 0x00 RW 0xE1 DEVICE_ CONFIG2 [7:0] DEVICE_CONFIGURATION2 0x00 RW

Table 23. Bit Descriptions for Common 5 DEVICE_RESET The device resets when 1 is written to this bit. DEVICE_RESET is a self clear bit. After the reset, the bit returns to 0 automatically. The readback is always 0. Table 24. Bit Descriptions for PD_CONTROL only the analog portion of the IDAC. The IDAC digital data path is not affected. the analog portion of the QDAC. The QDAC digital data path is not affected. 5 PD_DATARCV The data interface circuitry is powered down when PD_DATARCV is set to 1. This bit powers down the data interface and the write side of the FIFO. the DAC clocking path and, thus, the majority of the digital functions. is internally pulled low. Set to 1 when frame is not used. Table 25. Bit Descriptions for INTERRUPT_ENABLE0 Table 26. Bit Descriptions for INTERRUPT_ENABLE1

Table 27. Bit Descriptions for INTERRUPT_FLAG0

1 OVER_THRESHOLD OVER_THRESHOLD is set to 1 when input power is

0 DACOUT_MUTED DACOUT_MUTED is set to 1 when the DAC output is muted

Table 28. Bit Descriptions for INTERRUPT_FLAG1

2 FIFO_UNDERFLOW FIFO_UNDERFLOW is set to 1 when the FIFO read pointer

catches the FIFO write pointer.

1 FIFO_OVERFLOW FIFO_OVERFLOW is set to 1 when the FIFO write pointer

catches the FIFO read pointer.

0 FIFO_WARNING FIFO_WARNING is set to 1 when the FIFO is one slot from

Table 29. Bit Descriptions for IRQ_SEL0

Table 30. Bit Descriptions for IRQ_SEL1 Table 31. Bit Descriptions for DACCLK_RECEIVER_CTRL Table 32. Bit Descriptions for REFCLK_RECEIVER_CTRL

Table 33. Bit Descriptions for PLL_CTRL0 111111 Highest band (2.1 GHz). Table 34. Bit Descriptions for PLL_CTRL2 setting is 111 for optimal PLL performance. setting is 00111 for optimal PLL performance. Table 35. Bit Descriptions for PLL_CTRL3 digital clock is below 75 MHz. setting is turned off (0) for optimal PLL performance. frequency to the REFCLK frequency.

Table 36. Bit Descriptions for PLL_STATUS0 1111 The highest VCO control voltage. value and selecting a lower VCO band increases this value. 0000 The lowest VCO control voltage. Table 37. Bit Descriptions for PLL_STATUS1 Table 38. Bit Descriptions for IDAC_FS_ADJ0 Table 39. Bit Descriptions for IDAC_FS_ADJ1 Table 40. Bit Descriptions for QDAC_FS_ADJ0

Table 41. Bit Descriptions for QDAC_FS_ADJ1 [1:0] QDAC_FULLSCALE_ADJUST_MSB QDAC full-scale adjust, Bits[9:0] sets the full-scale current of the QDAC. default value (0x1F9) sets the full-scale current to 20 mA. Table 42. Bit Descriptions for DIE_TEMP_SENSOR_CTRL Table 43. Bit Descriptions for DIE_TEMP_LSB Table 44. Bit Descriptions for DIE_TEMP_MSB [7:0] DIE_TEMP_MSB Die temperature, Bits[15:0] indicate the approximate die temperature. For more information, see the Temperature Sensor section. Table 45. Bit Descriptions for CHIP_ID

Table 46. Bit Descriptions for INTERRUPT_CONFIG Table 47. Bit Descriptions for SYNC_CTRL 0 SYNC CLK is sampled by rising edges of DACCLK. 1 SYNC CLK is sampled by falling edges of DACCLK. Table 48. Bit Descriptions for FRAME_RST_CTRL

0 Responds to only the first valid frame pulse and resets the FIFO and/or

NCO one time only. This is the default and recommended mode.

1 Responds to every valid frame pulse and resets the FIFO and/or NCO

Table 49. Bit Descriptions for FIFO_LEVEL_CONFIG FIFO Operation section for details. Table 50. Bit Descriptions for FIFO_LEVEL_READBACK used in combination with the readback in Bit[6:4]. Table 51. Bit Descriptions for FIFO_CTRL

Table 52. Bit Descriptions for DATA_FORMAT_SEL 0 Input data in twos complement format. 1 Input data in binary format. 0 I samples are paired with the next Q samples. 1 I samples are paired with the prior Q samples. 0 The order of the data bits corresponds to the pin descriptions in Table 9. 1 The order of the data bits is inverted. information about the operation of the different interface modes. 0 Word mode; 16-bit interface bus width. 1 Byte mode; 8-bit interface bus width. Table 53. Bit Descriptions for DATAPATH_CTRL 0 The NCO outputs the high-side image. 1 The NCO outputs the low-side image. Table 54. Bit Descriptions for INTERPOLATION_CTRL 00 2× Mode 1; use HB1 filter. 10 4× mode; use HB1 and HB2 filters. 11 8× mode; use all three filters (HB1, HB2, and HB3).

Table 55. Bit Descriptions for OVER_THRESHOLD_CTRL0 Table 56. Bit Descriptions for OVER_THRESHOLD_CTRL1 input power protection function. Table 57. Bit Descriptions for OVER_THRESHOLD_CTRL2 0000 512 IQ data sample pairs. 0001 1024 IQ data sample pairs. 1010 219 IQ data sample pairs. Table 58. Bit Descriptions for INPUT_POWER_READBACK_LSB Table 59. Bit Descriptions for INPUT_POWER_READBACK_MSB

Table 60. Bit Descriptions for NCO_CTRL Table 61. Bit Descriptions for NCO_FREQ_TUNING_WORD0 Table 62. Bit Descriptions for NCO_FREQ_TUNING_WORD1 Table 63. Bit Descriptions for NCO_FREQ_TUNING_WORD2 Table 64. Bit Descriptions for NCO_FREQ_TUNING_WORD3 frequency of the complex carrier generated by the on-chip NCO. initialized in Register 0x30. It is in twos complement format. Table 65. Bit Descriptions for NCO_PHASE_OFFSET0

Table 66. Bit Descriptions for NCO_PHASE_OFFSET1 [7:0] NCO_PHASE_OFFSET_MSB This register sets the initial phase of the complex carrier signal upon reset. an offset of 0.0055 degrees. This value is in twos complement format. Table 67. Bit Descriptions for IQ_PHASE_ADJ0 Table 68. Bit Descriptions for IQ_PHASE_ADJ1 Quadrature Phase Adjustment section for more information. Table 69. Bit Descriptions for IDAC_DC_OFFSET0 Table 70. Bit Descriptions for IDAC_DC_OFFSET1 sample values written to the IDAC. Table 71. Bit Descriptions for QDAC_DC_OFFSET0

Table 72. Bit Descriptions for QDAC_DC_OFFSET1 sample values written to the QDAC. Table 73. Bit Descriptions for IDAC_GAIN_ADJ −∞ to 6 dB. The default gain setting is 0x20, which maps to unity gain (0 dB). Table 74. Bit Descriptions for QDAC_GAIN_ADJ −∞ to 6 dB. The default gain setting is 0x20, which maps to unity gain (0 dB). Table 75. Bit Descriptions for GAIN_STEP_CTRL0 I/QDAC_GAIN_ADJ (Register 0x3F and Register 0x40). Table 76. Bit Descriptions for GAIN_STEP_CTRL1 is automatically turned off, this bit is 1.

6 DAC_OUTPUT_ON In the case where the DAC output is automatically turned off in the

for turning on the DAC output manually. It is a self clear bit. I/QDAC_GAIN_ADJ (Register 0x3F and Register 0x40).

Table 77. Bit Descriptions for TX_ENABLE_CTRL

2 TXENABLE_GAINSTEP_EN DAC output gradually turns on/off under the control of the

in Register 0x41 and Register 0x42.

1 TXENABLE_SLEEP_EN When set to 1, the device is put in sleep mode when the

TXENABLE signal from the TXEN pin is low.

0 TXENABLE_POWER_DOWN_EN When set to 1, the device is put in power down mode when

TXENABLE signal from the TXEN pin is low. Table 78. Bit Descriptions for DAC_OUTPUT_CTRL enable the rest of the bits in this register.

3 FIFO_WARNING_SHUTDOWN_EN When this bit and Bit 7 are both high, if a FIFO warning occurs,

2 OVERTHRESHOLD_SHUTDOWN_EN The DAC output is turned off when the input average power is

greater than the predefined threshold. Table 79. Bit Descriptions for DATA_RX_CTRL0 Table 80. Bit Descriptions for DATA_RX_CTRL1

Table 81. Bit Descriptions for DEVICE_CONFIG0 Table 82. Bit Descriptions for Version Table 83. Bit Descriptions for DEVICE_CONFIG1 Table 84. Bit Descriptions for DEVICE_CONFIG2

from inherent phase uncertainty of the static frequency dividers. the divider appears as a varying skew between two DAC outputs. Figure 63. Latency Variation in 2× Interpolation from Clock Generation sources can also drift over temperature. Synchronization Implementation section. Figure 64. DAC Output Skew from Skewed Input Data and DCI

2 MATCH SYNC LINE FOR ALL DATA GEN

Figure 65. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

0.20 REF

0.80 MAX

0.05 MAX

0.02 NOM

8.50 REF

0.25 MIN

Rev. 0 | Page 62 of 64 NOTES

Rev. 0 | Page 63 of 64 NOTES

Rev. 0 | Page 64 of 64 NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10930-0-11/12(0)