AD9135BCPAZRL

AD9135 AD | Alldatasheet

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Dual, 11-/16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converters Data Sheet AD9135/AD9136 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2014–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, or 8× interpolation filter Low power architecture Transmit enable function allows extra power saving and instant control of the output status High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.42 W at 1.6 GSPS full operating conditions 88-lead LFCSP with exposed pad

APPLICATIONS

3G/4G W-CDMA base stations Wideband repeaters Software defined radios Wideband communications Point to point Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS) Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment TYPICAL APPLICATION CIRCUIT Figure 1. GENERAL DESCRIPTION The AD9135/AD9136 are dual, 11-/16-bit, high dynamic range digital-to-analog converters (DACs) that provide a maximum sample rate of 2800 MSPS, permitting a multicarrier generation over a very wide bandwidth. The DAC outputs are optimized to interface seamlessly with the ADRF6720, as well as other analog quadrature modulators (AQMs) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full- scale output current can be programmed over a typical range of 13.9 mA to 27.0 mA. The AD9135/AD9136 are available in an 88-lead LFCSP . PRODUCT HIGHLIGHTS 1. Greater than 2 GHz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless applications. 2. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. 3. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. 4. Fewer pins for data interface width with a serializer/ deserializer (SERDES) JESD204B eight-lane interface. 5. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. 6. Small package size with 12 mm × 12 mm footprint. AD9135/ AD9136 QUAD MOD ADRF6720 LPF 0°/90° PHASE SHIFTER JESD204B SYSREF± SYNCOUT0± LO_IN RF OUTPUT MOD_SPI DAC DAC SYNCOUT1± DAC SPI CLK ± 12578-001

Rev. C | Page 2 of 117 TABLE OF CONTENTS Maximum DAC Update Rate Speed Specifications by Supply 7

Rev. C | Page 3 of 117

REVISION HISTORY

5/2017— Rev. B to Rev. C 3/2017— Rev. A to Rev. B Changed 10.64 Gbps to 12.4 Gbps, 2.76 Gbps to 3.1 Gbps, and 7/2015— Rev. 0 to Rev. A Changed Functional Block Diagram Section to Typical Changed Detailed Functional Block Diagram Section to Changed 1× Interpolation Mode Parameter to 1× Interpolation Changes to Output Voltage (VOUT) Logic High Parameter, Output Voltage (VOUT) Logic Low Parameter, JESD204B Serial Interface Speed Minimum Parameter, and SYSREF± Frequency Changed Junction Temperature Parameter to Operating Changes to Overview Section, Table 15, Table 16, and Added SERDES PLL Fixed Register Writes Section and Added DAC PLL Fixed Register Writes Section and Changes to Start-Up Sequence Section, Table 77, and Deleted Lookup Tables for Three Different DAC PLL Reference 9/2014— Revision 0: Initial Version

Rev. C | Page 4 of 117 FUNCTIONAL BLOCK DIAGRAM Figure 2. SDIO SCLK CS IRQ RESET SYNCOUT0– SYNCOUT0+ DAC PLL SERDES PLL POWER-ON RESET SERIAL I/O PORT CONFIG REGISTERS CLK_SELPLL_CTRL DACCLK PLL_LOCK SYNCHRONIZATION LOGIC DAC ALIGN DETECT HB1 TXEN0 TXEN1 SERDIN7± VTT SERDIN0± CLOCK DATA RECOVERYAND CLOCK FORMATTER SYNCOUT1+ SYNCOUT1– REF AND BIAS I120 SYSREF+ SYSREF– SDO HB3HB2 OUT1+ OUT1– INV SINCINV SINC Q-GAIN SYSREF Rx CLK+ CLK– MODE CONTROL DACCLK CLK Rx Q-OFFSET HB3HB2HB1 FSC DACCLK I-GAIN I-OFFSET FSC OUT0+ OUT0– CLOCK DISTRIBUTION AND CONTROL LOGIC 12578-002

Rev. C | Page 5 of 117 SPECIFICATIONS DC SPECIFICATIONS TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 1. AD9135 AD9136 Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit RESOLUTION 11 16 Bits ACCURACY With calibration Differential Nonlinearity (DNL) ±0.175 ±1.0 LSB Integral Nonlinearity (INL) ±0.35 ±2.0 LSB MAIN DAC OUTPUTS Gain Error With internal reference −2.5 +2 +5.5 −2.5 +2 +5.5 % FSR I/Q Gain Mismatch −0.6 +0.6 −0.6 +0.6 % FSR Full-Scale Output Current (IOUTFS) Based on a 4 kΩ external resistor between I120 and GND Output Compliance Range −250 +750 −250 +750 mV Output Resistance 0.2 0.2 MΩ Output Capacitance 3.0 3.0 pF Gain DAC Monotonicity Guaranteed Guaranteed Settling Time To within ±0.5 LSB 20 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 0.04 ppm Gain 32 32 ppm/°C REFERENCE Internal Reference Voltage 1.2 1.2 V ANALOG SUPPLY VOLTAGES DIGITAL SUPPLY VOLTAGES POWER CONSUMPTION 1× Interpolation Mode, JESD Mode 8, 8 SERDES Lanes fDAC = 1.6 GSPS, IF = 40 MHz, PLL on, digital gain on, inverse sinc on, DAC full-scale current (IOUTFS) = 20 mA 1.42 1.74 1.42 1.74 W AVDD33 68 73 68 73 mA PVDD12 100 113.4 100 113.4 mA CVDD12 101 112 101 112 mA SVDD12 Includes VTT 554 665 554 665 mA DVDD12 196 224 196 224 mA SIOVDD33 11 12 11 12 mA IOVDD 36 50 36 50 µA

Rev. C | Page 6 of 117 DIGITAL SPECIFICATIONS TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL Input Voltage (VIN) Logic High 1.8 V ≤ IOVDD ≤ 3.3 V 0.7 × IOVDD V Low 1.8 V ≤ IOVDD ≤ 3.3 V 0.3 × IOVDD V CMOS OUTPUT LOGIC LEVEL Output Voltage (VOUT) Logic High 1.8 V ≤ IOVDD ≤ 3.3 V 0.75 × IOVDD V Low 1.8 V ≤ IOVDD ≤ 3.3 V 0.25 × IOVDD V MAXIMUM DAC UPDATE RATE1 1× interpolation2 (see Table 4) 2120 MSPS 2× interpolation2 2120 MSPS 4× interpolation3 2800 MSPS 8× interpolation3 2800 MSPS ADJUSTED DAC UPDATE RATE 1× interpolation 2120 MSPS 2× interpolation 1060 MSPS 4× interpolation 700 MSPS 8× interpolation 350 MSPS INTERFACE4 Number of JESD204B Lanes 8 Lanes JESD204B Serial Interface Speed Minimum Per lane 1.44 Gbps Maximum Per lane, SVDD12 = 1.3 V ± 2% 12.4 Gbps DAC CLOCK INPUT (CLK+, CLK−) Differential Peak-to-Peak Voltage 400 1000 2000 mV Common-Mode Voltage Self biased input, ac-coupled 600 mV Maximum Clock Rate 2800 MHz REFCLK5 Frequency (PLL Mode) 6 .0 GHz ≤ f VCO ≤ 12.0 GHz 35 1000 MHz SYSTEM REFERENCE INPUT (SYSREF+, SYSREF−) Differential Peak-to-Peak Voltage 400 1000 2000 mV Common-Mode Voltage 0 2000 mV SYSREF± Frequency6 f DATA/(K × S) Hz SYSREF SIGNAL TO DAC CLOCK7 SYSREF differential swing = 0.4 V, slew rate = 1.3 V/ns, common modes tested: ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V Setup Time t SSD 131 ps Hold Time t HSD 119 ps Keep Out Window KOW 20 ps SPI Maximum Clock Rate SCLK IOVDD = 1.8 V 10 MHz Minimum SCLK Pulse Width High t PWH 8 ns Low t PWL 12 ns SDIO to SCLK Setup Time t DS 5 ns Hold Time t DH 2 ns

Rev. C | Page 7 of 117 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SDO to SCLK Data Valid Window t DV 25 ns CS to SCLK Setup Time tSCS 5 ns Hold Time tHCS 2 ns 1 See Table 3 for detailed specifications for DAC update rate conditions. 2 The maximum speed for 1× and 2× interpolation is limited by the JESD204B interface with increased supply levels. See Table 4 for details. 3 The maximum speed for 4× and 8× interpolation is limited by the DAC core. See Table 4 for details. 4 See Table 4 for detailed specifications for JESD204B speed conditions. 5 REFCLK is the reference clock. 6 K, F, and S are JESD204B transport layer parameters. See Table 43 for the full definitions. 7 See Table 5 for detailed specifications for SYSREF signal to DAC clock timing conditions. MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit MAXIMUM DAC UPDATE RATE 2×, 4×, and 8× Interpolation DVDD12, CVDD12 = 1.2 V ± 5% 2.23 GSPS DVDD12, CVDD12 = 1.2 V ± 2% 2.41 GSPS DVDD12, CVDD12 = 1.3 V ± 2% 2.80 GSPS 1× Interpolation DVDD12, CVDD12 = 1.2 V ± 5% 1.81 GSPS DVDD12, CVDD12 = 1.2 V ± 2% 1.93 GSPS DVDD12, CVDD12 = 1.3 V ± 2% 2.21 GSPS JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit HALF RATE SVDD12 = 1.2 V ± 5% 5.75 11.4 Gbps SVDD12 = 1.2 V ± 2% 5.75 12.0 Gbps SVDD12 = 1.3 V ± 2% 5.75 12.4 Gbps FULL RATE SVDD12 = 1.2 V ± 5% 2.88 5.98 Gbps SVDD12 = 1.2 V ± 2% 2.88 6.06 Gbps SVDD12 = 1.3 V ± 2% 2.88 6.2 Gbps OVERSAMPLING SVDD12 = 1.2 V ± 5% 1.44 3.0 Gbps SVDD12 = 1.2 V ± 2% 1.44 3.04 Gbps SVDD12 = 1.3 V ± 2% 1.44 3.1 Gbps

Rev. C | Page 8 of 117 SYSREF SIGNAL TO DAC CLOCK TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SYSREF DIFFERENTIAL SWING = 0.4 V, SLEW RATE = 1.3 V/ns Setup Time AC-coupled 126 ps DC-coupled 131 ps Hold Time AC-coupled 92 ps DC-coupled 119 ps SYSREF DIFFERENTIAL SWING = 0.7 V, SLEW RATE = 2.28 V/ns Setup Time AC-coupled 96 ps DC-coupled 104 ps Hold Time AC-coupled 77 ps DC-coupled 95 ps SYSREF SWING = 1.0 V, SLEW RATE = 3.26 V/ns Setup Time AC-coupled 83 ps DC-coupled 90 ps Hold Time AC-coupled 68 ps DC-coupled 84 ps DIGITAL INPUT DATA TIMING SPECIFICATIONS TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 6. Parameter Min Typ Max Unit LATENCY Interface 17 PClock1 cycles Interpolation 1× 66 DAC clock cycles 2× 137 DAC clock cycles 4× 251 DAC clock cycles 8× 484 DAC clock cycles Inverse Sinc 17 DAC clock cycles Digital Gain Adjust 12 DAC clock cycles POWER-UP TIME 60 µs

1 PClock is the

AD9135/AD9136 internal processing clock and equals the lane rate ÷ 40.

Rev. C | Page 9 of 117 LATENCY VARIATION SPECIFICATIONS TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 7. Parameter Min Typ Max Unit DAC LATENCY VARIATION SYNC On PLL Off 0 1 DAC clock cycles PLL On −1 +1 DAC clock cycles JESD204B INTERFACE ELECTRICAL SPECIFICATIONS TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 8. Parameter Symbol Test Conditions/Comments Min Typ Max Unit JESD204B DATA INPUTS Input Leakage Current T A = 25°C Logic High Input level = 1.2 V ± 0.25 V, VTT = 1.2 V 10 µA Logic Low Input level = 0 V −4 µA Unit Interval UI 94 714 ps Common-Mode Voltage V RCM AC-coupled, VTT = SVDD121 −0.05 +1.85 V Differential Voltage R_V DIFF 110 1050 mV VTT Source Impedance Z TT At dc 30 Ω Differential Impedance Z RDIFF At dc 80 100 120 Ω Differential Return Loss RLRDIF 8 dB Common-Mode Return Loss RLRCM 6 dB DIFFERENTIAL OUTPUTS (SYNCOUTx±)2 Output Differential Voltage V OD Normal Swing Mode Register 0x2A5[0] = 0 192 235 mV High Swing Mode Register 0x2A5[0] = 1 341 394 mV Output Offset Voltage V OS 1.19 1.27 V DETERMINISTIC LATENCY Fixed 17 PClock3 cycles Variable 2 P Clock3 cycles SYSREF± to LOCAL MULTIFRAME COUNTER (LMFC) DELAY

4 DAC clock cycles

1 As measured on the input side of the ac coupling capacitor. 2 IEEE Standard 1596.3 LVDS compatible.

3 PClock is an

AD9135/AD9136 internal processing clock and equals the lane rate ÷ 40.

Rev. C | Page 10 of 117 AC SPECIFICATIONS TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 9. Parameter Test Conditions/Comments Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) −9 dBFS single-tone fDAC = 983.04 MSPS f OUT = 20 MHz 82 dBc fDAC = 983.04 MSPS f OUT = 150 MHz 76 dBc fDAC = 1966.08 MSPS f OUT = 20 MHz 81 dBc fDAC = 1966.08 MSPS fOUT = 170 MHz 69 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) −9 dBFS fDAC =983.04 MSPS f OUT = 20 MHz 90 dBc fDAC = 983.04 MSPS fOUT = 150 MHz 82 dBc fDAC = 1966.08 MSPS f OUT = 20 MHz 90 dBc fDAC = 1966.08 MSPS f OUT = 170 MHz 81 dBc NOISE SPECTRAL DENSITY (NSD), SINGLE-TONE 0 dBFS fDAC = 983.04 MSPS f OUT = 150 MHz −162 dBm/Hz fDAC = 1966.08 MSPS f OUT = 150 MHz −163 dBm/Hz W-CDMA FIRST ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE-CARRIER 0 dBFS fDAC = 983.04 MSPS f OUT = 30 MHz 82 dBc fDAC = 983.04 MSPS f OUT = 150 MHz 80 dBc fDAC = 1966.08 MSPS f OUT = 150 MHz 80 dBc W-CDMA SECOND ACLR, SINGLE-CARRIER 0 dBFS fDAC = 983.04 MSPS f OUT = 30 MHz 84 dBc fDAC = 983.04 MSPS f OUT = 150 MHz 85 dBc fDAC = 1966.08 MSPS fOUT = 150 MHz 85 dBc 1 SVDD12 = 1.3 V for all fDAC = 1966.08 MSPS conditions in Table 9.

and mechanical connection to the board. case temperature monitored at the bottom of the exposed pad. θJA in still air test conditions. TT is the temperature measured at the top of the package. P is the total device power dissipation. TB is the temperature measured at the board. Table 11. Thermal Resistance 1 The exposed pad must be securely connected to the ground plane.

Figure 3. Pin Configuration Table 12. Pin Function Descriptions 1 PVDD12 1.2 V Supply. PVDD12 provides a clean supply. 2 CLK+ PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input. 3 CLK− PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input. 4 PVDD12 1.2 V Supply. PVDD12 provides a clean supply. 7 PVDD12 1.2 V Supply. PVDD12 provides a clean supply. 8 PVDD12 1.2 V Supply. PVDD12 provides a clean supply. 9 PVDD12 1.2 V Supply. PVDD12 provides a clean supply. 10 PVDD12 1.2 V Supply. PVDD12 provides a clean supply. 11 TXEN0 Transmit Enable for DAC0. CMOS levels are determined with respect to IOVDD. 12 TXEN1 T ransmit Enable for DAC1. CMOS levels are determined with respect to IOVDD. 13 DVDD12 1.2 V Digital Supply. 14 DVDD12 1.2 V Digital Supply. using a calibrated 50 Ω resistor. This pin is ac-coupled only. using a calibrated 50 Ω resistor. This pin is ac-coupled only. 17 SVDD12 1.2 V JESD204B Receiver Supply. using a calibrated 50 Ω resistor. This pin is ac-coupled only.

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.

59 PROTECT_OUT0

60 IRQ

61 RESET

62 SDO

63 SDIO

64 SCLK

66 IOVDD

80 DNC

81 CVDD12

82 LDO24

83 OUT0–

84 OUT0+

85 AVDD33

86 I120

87 CVDD12

88 LDO_BYP2

Rev. C | Page 13 of 117 Pin No. Mnemonic Description 19 SERDIN1− Serial Channel Input 1, Negative. CML compliant. SERDIN1− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 20 SVDD12 1.2 V JESD204B Receiver Supply. 21 V TT 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 22 SVDD12 1.2 V JESD204B Receiver Supply. 23 SYNCOUT0+ Positive LVDS Sync (Active Low) Output Signal Channel Link 0. 24 SYNCOUT0− Negative LVDS Sync (Active Low) Output Signal Channel Link 0. 25 V TT 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 26 SERDIN2+ Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 27 SERDIN2− Serial Channel Input 2, Negative. CML compliant. SERDIN2− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 28 SVDD12 1.2 V JESD204B Receiver Supply. 29 SERDIN3+ Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 30 SERDIN3− Serial Channel Input 3, Negative. CML compliant. SERDIN3− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 31 SVDD12 1.2 V JESD204B Receiver Supply. 32 SVDD12 1.2 V JESD204B Receiver Supply. 33 SVDD12 1.2 V JESD204B Receiver Supply. 34 LDO_BYP1 LDO SERDES Bypass. This pin requires a 1 Ω resistor in series with a 1 µF capacit or to ground. 35 SIOVDD33 3.3 V Supply for SERDES. 36 SVDD12 1.2 V JESD204B Receiver Supply. 37 SERDIN4− Serial Channel Input 4, Negative. CML compliant. SERDIN4− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 38 SERDIN4+ Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 39 SVDD12 1.2 V JESD204B Receiver Supply. 40 SERDIN5− Serial Channel Input 5, Negative. CML compliant. SERDIN5− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 41 SERDIN5+ Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 42 VTT 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 43 SYNCOUT1− Negative LVDS Sync (Active Low) Output Signal Channel Link 1. 44 SYNCOUT1+ Positive LVDS Sync (Active Low) Output Signal Channel Link 1. 45 SVDD12 1.2 V JESD204B Receiver Supply. 46 V TT 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 47 SVDD12 1.2 V JESD204B Receiver Supply. 48 SERDIN6− Serial Channel Input 6, Negative. CML compliant. SERDIN6− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 49 SERDIN6+ Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 50 SVDD12 1.2 V JESD204B Receiver Supply. 51 SERDIN7− Serial Channel Input 7, Negative. CML compliant. SERDIN7− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 52 SERDIN7+ Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 53 DVDD12 1.2 V Digital Supply. 54 GND Ground. Connect GND to the ground plane. 55 GND Ground. Connect GND to the ground plane. 56 PVDD12 1.2 V Supply. PVDD12 provides a clean supply. 57 PVDD12 1.2 V Supply. PVDD12 provides a clean supply. 58 PROTECT_OUT1 Power Detection and Protection Pin Output for DAC1. Pin 58 is high when power protection is in process. 59 PROTECT_OUT0 Power Detection and Protection Pin Output for DAC0. Pin 59 is high when power protection is in process. 60 IRQ Interrupt Request (Active Low, Open Drain).

Rev. C | Page 14 of 117 Pin No. Mnemonic Description 61 RESET Reset. This pin is active low. CMOS levels are determined with respect to IOVDD. 62 SDO Serial Port Data Output. CMOS levels are determined with respect to IOVDD. 63 SDIO Serial Port Data Input/Output. CMOS levels are determined with respect to IOVDD. 64 SCLK Serial Port Clock Input. CMOS levels are determined with respect to IOVDD. 65 CS Serial Port Chip Select. This pin is active low. CMOS levels are determined with respect to IOVDD. 66 IOVDD IOVDD Supply for CMOS Input/Output and SPI. Operational for 1.8 V ≤ IOVDD ≤ 3.3 V. 67 AVDD33 3.3 V Analog Supply for DAC Cores. 68 DNC Do not connect to this pin. 69 DNC Do not connect to this pin. 70 DNC Do not connect to this pin. 71 CVDD12 1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 71. 72 LDO24 2.4 V LDO. Requires a 1 µF capacitor to ground. 73 OUT1− DAC1 Negative Current Output. 74 OUT1+ DAC1 Positive Current Output. 75 AVDD33 3.3 V Analog Supply for DAC Cores. 76 CVDD12 1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 76. 77 AVDD33 3.3 V Analog Supply for DAC Cores. 78 DNC Do not connect to this pin. 79 DNC Do not connect to this pin. 80 DNC Do not connect to this pin. 81 CVDD12 1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 81. 82 LDO24 2.4 V LDO. Requires a 1 µF capacitor to ground. 83 OUT0− DAC0 Negative Current Output. 84 OUT0+ DAC0 Positive Current Output. 85 AVDD33 3.3 V Analog Supply for DAC Cores. 86 I120 Output Current Generation Pin for DAC Full-Scale Current. Tie a 4 kΩ resistor from the I120 pin to ground. 87 CVDD12 1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 87. 88 LDO_BYP2 LDO Clock Bypass for DAC PLL. This pin requires a 1 Ω resistor in series with a 1 µF capacitor to ground. EPAD Exposed Pad. The exposed pad must be securely connected to the ground plane.

Rev. C | Page 15 of 117 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset Error Offset error is the deviation of the output current from the ideal of 0 mA. For OUTx+, 0 mA output is expected when all inputs are set to 0. For OUTx−, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when the input is at its minimum code and the output when the input is at its maximum code. Output Compliance Range The output compliance range is the range of allowable voltages at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Offset drift is a measure of how far from full-scale range (FSR) the DAC output current is at 25°C (in ppm). Gain drift is a measure of the slope of the DAC output current across its full ambient operating temperature range, TA (in ppm/°C). Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Adjusted DAC Update Rate The adjusted DAC update rate is defined as the DAC update rate divided by the smallest interpolating factor. For clarity on DACs with multiple interpolating factors, the adjusted DAC update rate for each interpolating factor may be given. Physical Lane Physical Lane x refers to SERDINx±. Logical Lane Logical Lane x refers to physical lanes after optionally being remapped by the crossbar block (Register 0x308 to Register 0x30B). Link Lane Link Lane x refers to logical lanes considered per link. When paging Link 0 (Register 0x300[2] = 0), Link Lane x = Logical Lane x. When paging Link 1 (Register 0x300[2] = 1, dual link only), Link Lane x = Logical Lane x + 4.

Figure 22. AD9136 Single-Tone NSD (0 dBFS) vs. fOUT, fDAC = 983 MHz and

1966 MHz, PLL On and Off

Figure 23. AD9135 Single-Tone NSD (0 dBFS) vs. fOUT, fDAC = 983 MHz and Figure 24. AD9136 Single-Tone Phase Noise vs. Offset Frequency over fOUT, Figure 25. AD9136 Four-Carrier W-CDMA ACLR, fOUT = 30 MHz, Figure 26. AD9135 Four-Carrier W-CDMA ACLR, fOUT = 30 MHz, Figure 27. AD9136 Four-Carrier W-CDMA ACLR, fOUT = 122 MHz,

Figure 34. Total Power Consumption vs. fDAC over Interpolation,

8 SERDES Lanes Enabled, 2 DACs Enabled, Digital Gain, Inverse Sinc and

Figure 35. Power Consumption vs. fDAC over Digital Functions Figure 36. SVDD12 Current vs. Lane Rate over Number of SERDES Lanes and Figure 37. DVDD12, CVDD12, PVDD12, and AVDD33 Supply Currents vs. fDAC

2 LANES

4 LANES

8 LANES

Rev. C | Page 22 of 117 THEORY OF OPERATION The AD9135/AD9136 are 11-/16-bit, dual DACs with a SERDES interface. Figure 2 shows a detailed functional block diagram of the AD9135/AD9136. Eight high speed serial lanes carry data at a maximum speed of 12.4 Gbps, and a 2120 MSPS input data rate to each DAC. Compared to either LVDS or CMOS interfaces, the SERDES interface simplifies pin count, board layout, and input clock requirements to the device. The clock for the input data is derived from the device clock (required by the JESD204B specification). This device clock can be sourced with a PLL reference clock used by the on-chip PLL to generate a DAC clock or a high fidelity direct external DAC sampling clock. The device can be configured to operate in one-, two-, four-, or eight-lane modes, depending on the required input data rate. The digital datapath of the AD9135/AD9136 offers four interpolation modes (1×, 2×, 4×, and 8×) through three half-band filters with a maximum DAC sample rate of 2.8 GSPS. An inverse sinc filter is provided to compensate for sinc related roll-off. The AD9135/AD9136 DAC cores provide a fully differential current output with a nominal full-scale current of 20 mA. The full-scale current, IOUTFS, is user adjustable to between 13.9 mA and 27.0 mA, typically. The differential current outputs are complementary and are optimized for easy integration with the Analog Devices the ADRF6720 AQM. The AD9135/AD9136 are capable of multichip synchronization that can both synchronize multiple DACs and establish a constant and deterministic latency (latency locking) path for the DACs. The latency for each of the DACs remains constant from link establishment to link establishment. An external alignment (SYSREF±) signal makes the AD9135/AD9136 Subclass 1 compliant. Several modes of SYSREF± signal handling are available for use in the system. An SPI configures the various functional blocks and monitors their statuses. The various functional blocks and the data interface must be set up in a specific sequence for proper operation (see the Device Setup Guide section). Simple SPI initialization routines set up the JESD204B link and are included in the evaluation board package. The following sections describe the various blocks of the AD9135/AD9136 in greater detail. Descriptions of the JESD204B interface, control parameters, and various registers to set up and monitor the device are provided. The recommended start-up routine reliably sets up the data link.

Figure 38. Serial Port Interface Pins serial port timing to the initial state of the instruction cycle. instruction bits of the current I/O operation. The instruction byte contains the information shown in Table 13. Table 13. Serial Port Instruction Word or a write data transfer occurs after the instruction word write. the address decrements by 1 every 8 bits. of SCLK. All data is driven out on the falling edge of SCLK. acts as the data input, and SDO acts as the data output. A[14:0] as the instruction word, and D[7:0] is the data-word. When the LSB first bits = 1 (LSB first), the opposite is true. and the SDIO pin is used for both input and output.

Register 0x003 to Register 0x006 contain chip information, as shown in Table 14. Table 14. Chip Information Chip Type The product type is high speed DAC, which is represented by a code of 0x04 in Register 0x003. Product ID Eight MSBs in Register 0x005 and eight LSBs in Register 0x004. The product ID is 0x9144. Product Grade Register 0x006[7:4]. The product grade is 0x6 for the AD9136 and 0x4 for the AD9135. Device Revision Register 0x006[3:0]. The device revision is 0x08.

1. Set up the SPI interface, power up necessary circuit blocks,

up the DAC clocks (see the Step 1: Start Up the DAC section).

1. Set the digital features of the

Step 2: Digital Datapath section).

1. Set up the JESD204B links (see the Step 3: Transport Layer
2. Set up the physical layer of the SERDES interface (see the

Step 4: Physical Layer section).

1. Set up the data link layer of the SERDES interface (see the

Step 5: Data Link Layer section).

1. Check for errors (see the Step 6: Optional Error Monitoring
2. Optionally, enable any needed features as described in the

Step 7: Optional Features section. priate variable values for the conditions of the desired application. registers, and set up the DAC clocks, listed in Table 15. Table 15. Power-Up and DAC Initialization Settings 0x000 0x3C Deassert reset, set 4-wire SPI. 0x081 0x PdSysref PdSysref = 0x00 for Subclass 1. PdSysref = 0x10 for Subclass 0. Description columns for information on selecting the appropriate register value. hard reset, or power-up occurs. Table 16. Required Device Configurations If using the optional DAC PLL, also set the registers in Table 17. Table 17. Optional DAC PLL Configuration Procedure addresses and values for each.

2 Verify that Register 0x084[1] reads back 1 after enabling the DAC PLL to

indicate that the DAC PLL has locked.

provides further details on the feature blocks available. Table 18. Digital Datapath Settings see the Interpolation section.

7 DataFmt DataFmt = 0 if twos

Description columns for information on selecting the appropriate register value. mode. See the JESD204B Setup section for details. Register 0x201 need only be written once). Table 19. Transport Layer Settings 0x200 0x00 Power up the interface.

6 CheckSumMode See the JESD204B

3 DualLink See the JESD204B

2 CurrentLink See the JESD204B

7 Scrambling See the JESD204B

7 HD S ee the JESD204B

Description columns for information on selecting the correct register value.

are configured along with the CDR sampling and SERDES PLL. Table 20. Device Configurations and Physical Layer Settings

5 Halfrate Set up the CDR; see the SERDES

1 OvSmp Set up the CDR; see the SERDES

Description columns for information on selecting the correct register value.

2 Verify that Register 0x281[0] reads back 1 after enabling the SERDES PLL to

indicate that the SERDES PLL has locked. Table 21. Data Link Layer Settings

2 CurrentLink Set to 0 to access

Description columns for information on selecting the correct register value.

2 Verify that Register 0x03B[3] reads back 1 after sending at least one SYSREF±

edge to the device to indicate that the LMFC sync machine has properly locked.

There are a number of optional features that can be enabled. Table 22 provides links to the sections describing each feature. important for DAC specific settings like digital gain and dc offset. Table 22. Optional Features paged by the dual paging register. See the Self Calibration section.

clock frequency (fDAC) and DAC reference clock frequency (fREF). to the CLK± differential pins (Pin 2 and Pin 3). Table 23. DAC PLL LODivMode Settings Table 24. DAC PLL RefDivMode Settings where 6 GHz ≤ fVCO ≤ 12 GHz. where RefDivFactor = 2RefDivMode (see Table 24). Table 25. VCO Control Lookup Table Reference Clock Configurations section. maximum fDATA rate attainable. Table 26. Interpolation Modes and Their Usable Bandwidth and Lanes needed for the Step 3: Transport Layer section. parameter means, see the JESD204B Serial Data Interface section. Table 27. JESD204B Operating Modes (Single- or Dual-Link) are not available in this mode.

Table 28. JESD204B Operating Modes (Single-Link Only)

1 Note that for Mode 11 to Mode 13, the M and L parameters programmed on

are not available in this mode. where LaneRate is between 1.44 Gbps and 12.4 Gbps. setting must be set to one (HD = 1). Otherwise, set HD = 0. modes that are available are shown in Table 28. if scrambling is being used, or to 0 if it is not. signal. See the Subclass Setup section for more information. or Link 1, respectively, needs to be configured. Table 29. Lanes Setting per JESD Operating Mode ensure that the transmitter is set up as expected. Scrambling, HD, Subclass, and JESDVer variables. and in single-link mode), PdDACs must be set to 7.

lane rate is established in the JESD204B Setup section). Table 30. SERDES Lane Rate Configuration Settings SYSREF± signal that is accurately phase aligned to the DAC clock. which can be left disconnected. Set Subclass to 0 or 1 as desired. lanes in a system arrive in the same LMFC cycle. processing clock (PClock), whose rate is 1/40th the lane rate. Table 31. PClockFactor and PClockPerMF LMFCDel can be calculated directly. Table 8. TxFixed (the fixed transmitter delay in PClock cycles) delays, convert the delays into PClock cycles.

AD9136 cannot tolerate the variable delay in the system. used to calculate LMFCVar and LMFCDel.

1. Follow the steps in Table 15 through Table 21 of the Device
2. Set the subclass and perform a sync. For one-shot sync,

Signals section for alternate sync modes.

1. Record DYN_LINK_LATENCY_0 (Register 0x302) as a

value of Delay for that link and power cycle.

1. Record DYN_LINK_LATENCY_1 (Register 0x303) as a

value of Delay for that link and power cycle the system. Table 32. Register Configuration and Procedure for One- Description columns for information on selecting the appropriate register value. PClocksPerMF to the set of values near 0. new set of Delay values 6, 7, 8, and 9.

• MinDelay is the minimum of all Delay measurements
• MaxDelay is the maximum of all Delay measurements For safety, a guard band of 1 PClock cycle is added to each end of the link delay and calculate LMFCVar and LMFCDel with the following equation: LMFCVar = (MaxDelay + 1) − (MinDelay − 1) Note that if LMFCVar must be more than 10, the AD9135/ AD9136 cannot tolerate the variable delay in the system. For Subclass 1 LMFCDel = ((MinDelay − 1) × PClockFactor) For Subclass 0 LMFCDel = (MinDelay − 1) % PClockPerMF Program the same LMFCDel and LMFCVar across all links and devices. See the Link Delay Setup Example, Without Known Delay section for an example calculation. CROSSBAR SETUP Register 0x308 to Register 0x30B allow arbitrary mapping of physical lanes (SERDINx±) to logical lanes used by the SERDES deframers.

Table 33. Crossbar Registers desired physical lane (SERDINx±) from which to receive data. for Logical Lane 0, write LOGICAL_LANE0_SRC = 4.

reference (SYSREF±) and device clock (CLK±). the physical layer, the data link layer, and the transport layer. are defined in detail in the Transport Layer section. where LaneRate must be between 1.44 Gbps and 12.4 Gbps. Figure 43. Functional Block Diagram of Serial Link Receiver

Table 34. Single-Link and Dual-Link JESD204B Operating Modes Table 35. Single-Link JESD204B Operating Modes (CDR) circuit, and the 1:40 demux function (see Figure 45). 1.2 V differential input pins as per the JESD204B specification. 0 if the physical lane is being used, and to 1 if it is not being used. 0x2B2 as described in Table 36 to guarantee proper calibration. controls autocalibration for PHY 0, PHY 1, PHY 6, and PHY 7. The PHY termination autocalibration routine is shown in Table 36. Table 36. PHY Termination Autocalibration Routine regarding the eye mask and permitted receiver eye opening. Figure 44. Receiver Eye Mask Figure 45. Deserializer Block Diagram

M is the JESD204B parameter for converters per link. L is the JESD204B parameter for lanes per link. byte is represented by 10 bits. The processing clock is used for a quad-byte decoder. where F is defined as bytes per frame per lane. where F is the JESD204B parameter for octets per frame per lane. PLL VCO operates over the range of 5.65 GHz to 12.04 GHz. frequency, fREF, that is equal to 1/40 of the lane rate (PClockRate). settings for each of the desired DivFactor options available. Table 37. SERDES PLL Divider Settings Register 0x280 controls the synthesizer enable and recalibration. writing 1 to Register 0x280[0]. must be recalibrated by writing 0 and then 1 to Register 0x280[2]. the register writes in Table 38 are recommended. Table 38. SERDES PLL Fixed Register Writes SERDES PLL lock and lost signals are available as IRQ events.

Figure 46. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block

6.2 GHz output from the SERDES PLL, shown in Figure 46, is

desired lane rate is less than 5.65 GHz, disable half rate operation. must be set dependent on the LaneRate. Table 39. CDR Operating Modes implementation of multiple serial interfaces on a PCB. reset by writing 1 and then 0 to Register 0x206[0]. the equalizer can compensate for up to 17.5 dB of insertion loss. baud rate for the AD9135/AD9136. recommendations for the JESD204B channel. supported channel for low power mode (shown in Figure 47). ensure functionality and/or to optimize for power.

Figure 52. Lane Alignment During ILAS JESD204B specifications document for complete details. to the transmitter block at the receiver LMFC edge. lane alignment sequence (ILAS). link and to verify the parameters of the link. of each multiframe is a multiframe alignment character, /A/. lane to align the ends of the multiframes within the receiver. multiframes can be added to the ILAS if needed by the receiver. exactly four multiframes must be used. until the very first octet following the ILAS.

• Bad running disparity (8-bit/10-bit error)
• Not in table (8-bit/10-bit error)
• Unexpected control character
• Bad ILAS
• Interlane skew error (through character replacement) If any of these errors exist, they are reported back to the transmitter in one of a few ways (see the JESD204B Error Monitoring section for details).
• SYNCOUTx± signal assertion: resynchronization (SYNCOUTx± signal pulled low) is requested at each error for the last two errors. For the first three errors, an optional resynchronization request can be asserted when the error counter reaches a set error threshold.
• For the first three errors, each multiframe with an error in it causes a small pulse on SYNCOUTx±
• Errors can optionally trigger an IRQ event, which can be sent to the transmitter. Various test modes for verifying the link integrity can be found in the JESD204B Test Modes section. L RECEIVE LANES (LATEST ARRIVAL) L ALIGNED RECEIVE LANES

0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL

4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL

whether the FIFOs are full or empty. Table 40. Crossbar Registers desired physical lane (SERDINx±) from which to receive data. Logical Lane x, set Bit x of Register 0x334 to 1 to invert it. AD9135/AD9136 consist of two quad-byte deframers (QBDs). (or octets) per processing clock (PClock) cycle. JESD204B frames into samples. enabled by setting the SCR bit (Register 0x453[7]) to 1. registers are paged as described in the DAC Paging section. in a JESD204B Subclass 1 system to achieve deterministic latency. the SYSREF± pins. See Figure 53 for the SYSREF± internal circuit.

periodic SYSREF± signal can be used with ac coupling capacitors. SYSREF± vs. DAC clock keepout window (KOW) requirements. capacitor choice, and edge rate. Figure 53. SYSREF± Input Circuit the procedure for syncing the LMFC signals. occurs only once, the SYSREF signal can still be continuous. occurs on every alignment edge. Continuous mode differs from one-shot mode in two ways. deterministic by the size of the window. machine in this mode does not affect the operation of the device. phase error is on the low or high side. reference (Register 0x038 and Register 0x039, respectively).

1. Set Register 0x008 to 0x03 to sync the LMFC for both
2. Set the desired sync processing mode. The sync processing

mode settings are listed in Table 41.

1. For Subclass 1, set the error window according to the
2. Enable sync by writing 1 to SYNCENABLE
3. If in one-shot mode, arm the sync machine by writing 1 to

SYNCARM (Register 0x03A[6]).

1. If in Subclass 1, ensure that at least one SYSREF± pulse is
2. Check the status by reading the following bit fields:

the sync logic is no longer busy. window. This bit updates on every phase check. Table 41. Sync Processing Modes Table 42. Sync Window Tolerance SYNC_TRIP, and SYNC_WLIM) are available as IRQ events. See the Interrupt Request Operation section for more information. latency with mechanisms defined as Subclass 1 and Subclass 2. Register 0x301[2:0] and once per link to Register 0x458[7:5]. which can be left disconnected. cycle and that the two DACs be synchronized to each other. using Subclass 0 with F = 1.

described in the Link Delay Setup section. devices, deterministic latency is achieved. number of frame clock cycles per PClock cycle, is equal to 4/F. Register 0x307 for all devices in the system. and LMFCDel as described in the Link Delay Setup section.

1. Find the receiver delays using Table 8.
2. Find the transmitter delays. The equivalent table in the
3. Calculate MinDelayLane as follows:
4. Calculate MaxDelayLane as follows:
5. Calculate LMFCVar as follows:
6. Calculate LMFCDel as follows:
7. Write LMFCDel to both Register 0x304 and Register 0x305

Figure 57. LMFC_DELAY_x Calculation Example

Figure 60. Transport Layer Block Diagram parameters are defined in Table 44. Table 43. JESD204B Transport Layer Parameters F Number of octets per frame per lane: 1, 2, or 4. K Number of frames per multiframe. 1, 2, 4, or 8 (single-link mode). 1, 2, or 4 (dual-link mode). S Number of samples per conv erter, per frame: 1 or 2. Table 44. JESD204B Device Parameters CF Number of control words per device clock per link. Set to 1 when F = 1, otherwise 0. N Converter resolution = 16. Nʹ (or NP) Total number of bits per sample = 16. their associated clock relationships.

Table 45. Single-Link and Dual-Link JESD204B Operating Modes 1 Mode 8 can only be used with 1× interpolation. Other interpolation options are not available in this mode. 2 K must be 32 in Mode 8 and Mode 9. It can be 16 or 32 in Mode 10. Table 46. Single-Link JESD204B Operating Modes 1 Mode 11 can only be used with 1× interpolation. Other interpolation options are not available in this mode. on the transmit side reflect the true number of converters and lanes per link. 3 K must be 32 in Mode 11 and Mode 12. It can be 16 or 32 in Mode 13.

description and addresses for these settings. Table 47. Configuration Parameters HD High density format. Set to 1 if F = 1.

1 The values that need to be written in Register 0x454 and Register 0x476 are

different, F − 1 and F, respectively. are shown in Figure 62 through Figure 66. To use dual-link mode, set LINK_MODE (Register 0x300[3]) to 1. which can be done by setting Register 0x203[0] = 1.

Figure 61. JESD204B Mode 11 Data Deframing process of the JESD204B receiver for each of the modes. be set accordingly for single- or dual-link operation. Register Maps and Descriptions section.

40 BITS PARALLEL DATA

1 OCTET PER LANE

2 SAMPLES PER

2 CONVERTERS

Table 48. SPI Configuration Map— Register Settings for JESD204B Parameters for Mode 8 Figure 62. JESD204B Mode 8 Data Deframing

1 CONVERTER

Table 49. SPI Configuration Map— Register Settings for JESD204B Parameters for Mode 9 Figure 63. JESD204B Mode 9 Data Deframing

1 SAMPLE PER

Table 50. SPI Configuration Map— Register Settings for JESD204B Parameters for Mode 10 Figure 64. JESD204B Mode 10 Data Deframing

2 OCTETS PER LANE

Table 51. SPI Configuration Map— Register Settings for JESD204B Parameters for Mode 11 on the transmit side reflect the true number of converters and lanes per link. AD9135/AD9136 JESD204B Mode 11 data deframing process.

Table 52. SPI Configuration Map— Register Settings for JESD204B Parameters for Mode 12 on the transmit side reflect the true number of converters and lanes per link. Figure 65. JESD204B Mode 12 Data Deframing

Table 53. SPI Configuration Map— Register Settings for JESD204B Parameters for Mode 13 on the transmit side reflect the true number of converters and lanes per link. Figure 66. JESD204B Mode 13 Data Deframing

PRBS pattern checker on the back end of its physical layer. checker does not require that the JESD204B link be established.

1. Start sending a PRBS7, PRBS15, or PRBS31 pattern from
2. Select and write the appropriate PRBS pattern to

Register 0x316[3:2], as shown in Table 54.

1. Enable the PHY test for all lanes being tested by writing to

writing a 1 to Bit 0 enables the PRBS test for Physical Lane 0.

1. Toggle PHY_TEST_RESET (Register 0x316[0]) from 0 to 1
2. Set PHY_PRBS_ERROR_THRESHOLD (Register 0x317 to
3. Write a 0 and then a 1 to PHY_TEST_START
4. Stop the test by writing PHY_TEST_START
5. Read the PRBS test results.

corresponds to one SERDES lane: 0 is fail, 1 is pass. to Register 0x31C). The maximum error count is 224 − 1. Table 54. PHY PRBS Pattern Selection unique samples transmitted repeatedly until the test is stopped.

1. Synchronize JESD204B link.
2. Enable the STPL test at the JESD204B transmitter.
3. Select Converter 0 Sample 0 for testing. Write

SHORT_TPL_SP_SEL (Register 0x32C[5:4]) = 0.

1. Set the expected test sample for Converter 0, Sample 0.
2. Enable the STPL test. Write SHORT_TPL_TEST_EN
3. Toggle the STPL reset. SHORT_TPL_TEST_RESET

(Register 0x32C[1]) from 0 to 1 then back to 0.

1. Check for failures. Read SHORT_TPL_FAIL

(Register 0x32F[0]): 0 is pass, 1 is fail.

1. Repeat Step 3 to Step 7 for each sample of each converter,

Conv0Sample0 through ConvM − 1SampleS − 1. stream of ILAS is being received. the status of lanes on Link 1 for dual-link mode.

sending a repeated ILAS sequence. to monitor the status of lanes on Link 1 for dual-link mode. issue a sync request and reinitialize the link when errors occur. in the 8-bit/10-bit decoding table.

1. Select the desired link lane and error type of the counter to

view. Write these to Register 0x46B according to Table 55.

1. Read the error count from Register 0x46B. Note the

Table 55. Error Counters has reached a programmable threshold.

1. Program the desired error count threshold into

ERRORTHRES (Register 0x47C).

1. Read back the error status for each error type to see if the

error count has reached the error threshold. Disparity errors are reported in Register 0x46D. Not in table errors are reported in Register 0x46E.

1. Select the link lane to access. To select a link lane, first

Register 0x300[2] = 1 to select Link 1 (dual link only)).

1. Decide whether to reset the IRQ, disable the error count,

and/or reset the error count for the given lane and error type.

1. Write the link lane and desired reset or disable action to

Register 0x46D to Register 0x46F according to Table 56. Table 56. Error Counter and IRQ Control: Disparity

7 RstIRQ RstIRQ = 1 to reset IRQ for the lane

6 Disable_ErrCnt Disable_ErrCnt = 1 to disable the error

count for the lane selected in Bits[2:0].

5 RstErrCntr RsteErrCntr = 1 to reset the error count

for the lane selected in Bits[2:0].

a SYNCOUTx± pulse of 2 frame clock cycles are given in Table 57. Table 57. Setting SYNCOUTx± Error Pulse Duration

1 These register settings assert the SYNCOUTx±

IRQ events. Enable these events by writing to Register 0x47A[7:5]. (Register 0x47A[7:5]) after the IRQs are enabled. section for more information on IRQs. resync request is five frames and nine octets long.

1. Set THRESHOLD_MASK_EN (Register 0x477[3]) = 1.

saturate at either threshold or maximum value.

1. Enable the sync assertion mask for each type of error by

(Register 0x47B[7:5]) according to Table 58.

1. Program the desired error counter threshold into

ERRORTHRES (Register 0x47C).

1. For each error type enabled in the SYNCASSERTIONMASK

Table 58. Sync Assertion Mask

6 NIT_S Set to 1 to assert SYNCOUTx±

5 UCC_S Set to 1 to assert SYNCOUTx±

status of the lanes on Link 1. Lane x completed initial frame synchronization. eight bits of the sum of Register 0x400 to Register 0x40C and LID. Lane x passed the initial lane alignment sequence. as IRQ events. Enable them by writing to Register 0x47A[3:0]. See the Interrupt Request Operation section for more information.

parameters programmed to Register 0x453 and Register 0x456. ensures that the transmitted settings match the configured settings. must remain as noise free as possible for the best operation. shows the recommended power supply components. Figure 67. This filter scheme reduces high frequency noise AD9136 to the ground plane using vias. high speed transmission lines that require controlled impedances. (SERDIN0± to SERDIN7±) section. Table 59. Power Supplies rates. See Table 3 for details.

2 This supply can be combined with CVDD12 on the same regulator with a

separate supply filter network and sufficient bypass capacitors near the pins. rates. See Table 4 for details. 4 This supply can be connected to SVDD12 and does not need separate circuitry.

Figure 73. Block Diagram of Digital Datapath and gain, offset, and group delay adjustment blocks. how to use the DAC paging bits. Table 60. Paging Modes

1 DAC0

2 DAC1

dc offset, group delay, datapath PRBS, and LMFC sync. is negative full scale and 0xFFE0 is positive full scale. quantization error along the datapath. maximum data rates. Note that fDATA = fDAC/Interpolation Factor. interpolation mode is selected. Table 61. Interpolation Modes and Usable Bandwidth interpolation are only available in Mode 9, Mode 10, Mode 12, and Mode 13.

2 The maximum speed for 1× and 2× interpolation is limited by the JESD204B

interface. See Table 4 for the appropriate supply levels. shown for each filter in Figure 74. less than ±0.001 dB and an image rejection of greater than 85 dB. Figure 74. All Band Responses of Interpolation Filters

Table 62. Digital Gain Registers the I or Q DAC. This feature can be used to cancel LO leakage. LSBs Offset is the value of Register 0x136 and Register 0x137. Sixteenths Offset is the value of Register 0x13A. Table 63. DC Offset Registers be useful, for example, for DPD loop delay adjustment. where Group Delay is a 4-bit twos complement number.

Figure 77. Downstream Protection Block Diagram (BSM) and a transmit enable state machine (Tx ENSM). enable/disable downstream components, such as a PA. components on or off as desired. (nominally an additional ~35 µs). as described in the DAC Paging section. Table 64. Tx ENSM Registers

time, the datapath is flushed with zeros. high if disabling digital gain. The current BSM state can be read back as shown in Table 65. Table 65. Blanking State Machine Ramping Readbacks 0x147[7:6] 0b00 Data is being held at midscale. ramping to normal amplitude. 0b11 Data at normal amplitude. Blanking completion is available as an IRQ event. See the Interrupt Request Operation section for more information. are paged as described in the DAC Paging section. Table 66. PROTECT_OUTx Registers

3 SPI_PROTECT_OUT 1: SPI_PROTECT

2 SPI_PROTECT Sets SPI_PROTECT

designed to support input data rates of up to 1060 MHz.

1. Set up the device in the desired operating mode. See the
2. Send the PRBS7 or PRBS15 data.
3. Write Register 0x14B[2] = 0 for PRBS7 or 1 for PRBS15.
4. Write Register 0x14B[1:0] = 0b11 to enable and reset the
5. Write Register 0x14B[1:0] = 0b01 to enable the PRBS test
6. Check the status by checking the IRQ for DAC0 and DAC1

PRBS as described in the Datapath PRBS IRQ section.

1. If there are failures, set Register 0x008 = 0x01 to view the
2. Read Register 0x14B[6]. Bit 6 is 0 if the selected DAC has

any errors. This must match the IRQ.

1. Read Register 0x14C to read the error count of the selected

• Bits: 32 good, 31 good, 1 bad; 32 good (2 errors)
• Bits: 32 good, 22 good, 10 bad; 32 good (2 errors)
• Bits: 32 good, 31 good, 1 bad; 31 good, 1 bad; 32 good (3 errors)

Rev. C | Page 70 of 117 Datapath PRBS IRQ The PRBS fail signals for each DAC are available as IRQ events. Use Register 0x020, Bit 2 and Bit 0, to enable the fail signals, and then use Register 0x024, Bit 2 and Bit 0, to read back their statuses and reset the IRQ signals. See the Interrupt Request Operation section for more information. DC TEST MODE As a convenience, the AD9135/AD9136 provide a dc test mode, which is enabled by setting Register 0x520[1] to 1 and clearing Register 0x146[0] to 0. When this mode is enabled, the datapath is given 0 (midscale) for its data. Register 0x146[0] must be set to 1 for all other modes of operation. In conjunction with dc offset, this test mode can provide the desired dc data to the DACs.

clock operating at a submultiple of the desired DACCLK rate. coupling between the clock source and the receiver. Figure 79. Clock Receiver Input Simplified Equivalent Circuit the lowest noise spectral density at the DAC outputs. all clocks on the device, write Register 0x080 = 0x00. up the DAC PLL, including the loop filter and the charge pump. Table 69. DAC PLL Fixed Register Writes the DAC sample rate clock from a lower frequency reference clock. block diagram of the clock multiplier is shown in Figure 82. REFCLK input is referred to as fREF. The REFCLK input is divided by the variable RefDivFactor. Table 70. The REF_DIV_MODE register is programmed through Register 0x08C[2:0].

dependent SPI writes shown in Table 73. Table 73. VCO Control Lookup Table Reference

1. Program the registers in the DAC PLL Fixed Register
2. Determine the VCO frequency based on the DAC
3. Determine the VCO divider ratio to achieve the desired
4. Determine the BCount ratio to achieve the desired PLL

BCount ratio in Register 0x085[7:0].

1. Determine the reference divider ratio to achieve the

divider ratio in Register 0x08C[2:0].

1. Based on the fVCO found in Step 2, write the temperature

tracking registers as shown in Table 73.

1. Enable the DAC PLL synthesizer by setting Register 0x083[4]

Register 0x084[1] notifies the user that the PLL has locked. DAC PLL by setting Register 0x083[7] to 0 and then 1. The DAC PLL lock and lost signals are available as IRQ events. Figure 82. Device Clock PLL Block Diagram

Rev. C | Page 78 of 117 DEVICE POWER DISSIPATION The AD9135/AD9136 have eight supply rails, AVDD33, DVDD12, SVDD12, SIOVDD33, CVDD12, IOVDD, VTT, and PVDD12, which can be driven from five regulators to achieve optimum performance, as shown in Figure 67. The AVDD33 supply powers the DAC core circuitry. The power dissipation of the AVDD33 supply rail is independent of the digital operating mode and sample rate. The current drawn from the AVDD33 supply rail is typically 68 mA (225 mW) when the full-scale current of DAC0 and DAC1 are set to the nominal value of 20.48 mA. PVDD12 powers the DAC PLLs and varies depending on the DAC sample rate. CVDD12 can be combined with the PVDD12 regulator, but requires proper bypass capacitor networks near the pins. CVDD12 powers the clock tree, and the current varies directly with the DAC sample rate. DVDD12 powers the DSP core, and the current draw depends on the number of DSP functions and the DAC sample rate used. SVDD12 supplies the SERDES lanes and associated circuitry including the equalizers, SERDES PLL, PHY, and up to the input of the DSP . The current depends on the number lanes and the lane bit rate. IOVDD powers the SPI circuit and draws a very small current. SIOVDD33 powers the equalizers for the SERDES lanes. The VTT termination voltage draws a very small current of <5 mA. TEMPERATURE SENSOR The AD9135/AD9136 have a band gap temperature sensor for monitoring the temperature changes of the AD9135/AD9136. The temperature must be calibrated against a known temperature to remove the device-to-device variation on the band gap circuit used to sense the temperature. To monitor temperature change, the user must take a reading at a known ambient temperature for a single-point calibration of each AD9135/AD9136 device. Tx = TREF + 7.3 × (CODE_X − CODE_REF)/1000 where: CODE_X is the readback code at the unknown temperature, Tx. CODE_REF is the readback code at the calibrated temperature, TREF. To use the temperature sensor, it must be enabled by setting Register 0x12F[0] to 1. The user must write a 1 to Register 0x134[0] before reading back the die temperature from Register 0x132 and Register 0x133.

and the DAC PLL enabled with a 368.64 MHz reference clock.

1. Set up the SPI interface, power up necessary circuit blocks,

the DAC clocks (see the Step 1: Start Up the DAC section).

1. Set the digital features of the

Step 2: Digital Datapath section).

1. Set up the JESD204B links (see the Step 3: Transport Layer
2. Set up the physical layer of the SERDES interface (see the

Step 4: Physical Layer section).

1. Set up the data link layer of the SERDES interface. This
2. Check for errors on Link 0 and Link 1 (see the Step 6:

tables that list the required register write and read commands. Table 76. Power-Up and DAC Initialization Table 77. Required Device Configurations Table 78. Configure DAC PLL Table 79. Digital Datapath

Table 80. Link 0 Transport Layer

1 Note that for Mode 11 through Mode 13, the M and L the parameters

converters and lanes per link. Table 81. Physical Layer

Note that this procedure does not guarantee deterministic latency. Table 82. Data Link Layer— Does Not Guarantee Deterministic that system tasks are completed as described. Table 83. Link 0 Checks R 0x472 0xFF Check for good checksum. R 0x473 0xFF Check for ILAS.

and reset columns are hexadecimal numbers. Table 84. Device Configuration Register Map

Rev. C | Page 83 of 117 Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W 0x040 DACGAIN0_1 RESERVED DACFSC_0[9:8] 0x00 R/W 0x041 DACGAIN0_0 DACFSC_0[7:0] 0x00 R/W 0x044 DACGAIN1_1 RESERVED DACFSC_1[9:8] 0x00 R/W 0x045 DACGAIN1_0 DACFSC_1[7:0] 0x00 R/W 0x080 CLKCFG0 PD_CLK0 PD_CLK1 PD_CLK_DIG PD_SERDES_ PCLK PD_CLK_REC RESERVED 0xF8 R/W 0x081 SYSREF_ACTRL0 RESERVED PD_SYSREF HYS_ON SYSREF_RISE HYS_CNTRL1 0x10 R/W 0x082 SYSREF_ACTRL1 HYS_CNTRL0 0x00 R/W 0x083 DACPLLCNTRL RECAL_ DACPLL RESERVED ENABLE_ DACPLL RESERVED 0x00 R/W 0x084 DACPLLSTATUS DACPLL_ OVER- RANGE_H DACPLL_ OVER- RANGE_L DACPLL_ CAL_VALID RESERVED DACPLL_ LOCK RESERVED 0x00 R 0x085 DACINTEGER- WORD0 B_COUNT 0x08 R/W 0x087 DACLOOPFILT1 LF_C2_WORD LF_C1_WORD 0x88 R/W 0x088 DACLOOPFILT2 LF_R1_WORD LF_C3_WORD 0x88 R/W 0x089 DACLOOPFILT3 LF_ BYPASS_ LF_ BYPASS_R1 LF_BYPASS_ LF_BYPASS_C1 LF_R3_WORD 0x08 R/W 0x08A DACCPCNTRL RESERVED CP_CURRENT 0x20 R/W 0x08B DACLOGENCNTRL RESERVED LO_DIV_MODE 0x02 R/W 0x08C DACLDOCNTRL1 RESERVED REF_DIV_MODE 0x01 R/W 0x08D DACLDOCNTRL2 DAC_LDO 0x2B R/W 0x0E2 CAL_CTRL_ GLOBAL RESERVED CAL_START_ AVG CAL_EN_ AVG 0x00 R/W 0x0E7 CAL_CLKDIV RESERVED CAL_CLK_EN RESERVED 0x30 R/W 0x0E8 CAL_PAGE RESERVED CAL_PAGE 0x0F R/W 0x0E9 CAL_CTRL CAL_FIN CAL_ ACTIVE CAL_ERRHI CAL_ERRLO RESERVED CAL_START CAL_EN 0x00 R/W 0x0ED CAL_INIT CAL_INIT A6 R/W 0x110 DATA_FORMAT BINARY_ FORMAT RESERVED 00 R/W 0x111 DATAPATH_CTRL INVSINC_ ENABLE RESERVED DIG_GAIN_ ENABLE RESERVED 0xA0 R/W 0x112 INTERP_MODE RESERVED INTERP_MODE 0x01 R/W 0x11F TXEN_SM_0 FALL_COUNTERS RISE_COUNTERS RESERVED PROTECT_OUT_ INVERT RESERVED 0x83 R/W 0x121 TXEN_RISE_ COUNT_0 RISE_COUNT_0 0x0F R/W 0x122 TXEN_RISE_ COUNT_1 RISE_COUNT_1 0x00 R/W 0x123 TXEN_FALL_ COUNT_0 FALL_COUNT_0 0xFF R/W 0x124 TXEN_FALL_ COUNT_1 FALL_COUNT_1 0xFF R/W 0x12D DEVICE_CONFIG_ REG_0 DEVICE_CONFIG_0 0x46 R/W 0x12F DIE_TEMP_CTRL0 RESERVED AUXADC_ ENABLE 0x20 R/W 0x132 DIE_TEMP0 DIE_TEMP[7:0] 0x00 R 0x133 DIE_TEMP1 DIE_TEMP[15:8] 0x00 R 0x134 DIE_TEMP_ UPDATE RESERVED DIE_TEMP_ UPDATE 0x00 R/W

Rev. C | Page 84 of 117 Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W 0x135 DC_OFFSET_CTRL RESERVED DC_OFFSET_ ON 0x00 R/W 0x136 DAC_DC_ OFFSET_1PART0 LSB_OFFSET[7:0] 0x00 R/W 0x137 DAC_DC_ OFFSET_1PART1 LSB_OFFSET[15:8] 0x00 R/W 0x13A DAC_DC_ OFFSET_2PART RESERVED SIXTEENTH_OFFSET 0x00 R/W 0x13C DAC_DIG_GAIN0 DAC_DIG_GAIN[7:0] 0xEA R/W 0x13D DAC_DIG_GAIN1 RESERVED DAC_DIG_GAIN[11:8] 0x0A R/W 0x140 GAIN_RAMP_UP_ STEP0 GAIN_RAMP_UP_STEP[7:0] 0x04 R/W 0x141 GAIN_RAMP_ UP_STEP1 RESERVED GAIN_RAMP_UP_STEP[11:8] 0x00 R/W 0x142 GAIN_RAMP_ DOWN_STEP0 GAIN_RAMP_DOWN_STEP[7:0] 0x09 R/W 0x143 GAIN_RAMP_ DOWN_STEP1 RESERVED GAIN_RAMP_DOWN_STEP[11:8] 0x00 R/W 0x146 DEVICE_CONFIG_ REG_1 DEVICE_CONFIG_1 0x00 R/W 0x147 BSM_STAT SOFTBLANKRB RESERVED 0x00 R 0x14B PRBS RESERVED PRBS_ GOOD RESERVED PRBS_MODE PRBS_RESET PRBS_EN 0x10 R/W 0x14C PRBS_ERROR PRBS_COUNT 0x00 R 0x1B0 DACPLLT0 DAC_PLL_PWR 0xFA R/W 0x1B5 DACPLLT5 RESERVED VCO_VAR 0x83 R/W 0x1B9 DACPLLT9 DAC_PLL_CP1 0x34 R/W 0x1BB DACPLLTB RESERVED VCO_BIAS_TCF VCO_BIAS_REF 0x0C R/W 0x1BC DACPLLTC DAC_PLL_VCO_CTRL 0x00 R/W 0x1BE DACPLLTE DAC_PLL_VCO_PWR 0x00 R/W 0x1BF DACPLLTF DAC_PLL_VCOCAL 0x8D R/W 0x1C0 DACPLLT10 DAC_PLL_LOCK_CNTR 0x2E R/W 0x1C1 DACPLLT11 DAC_PLL_CP2 0x24 R/W 0x1C4 DACPLLT17 DAC_PLL_VAR1 0x33 R/W 0x1C5 DACPLLT18 DAC_PLL_VAR2 0x08 R/W 0x200 MASTER_PD RESERVED SPI_PD_ MASTER 0x01 R/W 0x201 PHY_PD SPI_PD_PHY 0x00 R/W 0x203 GENERIC_PD RESERVED SPI_ SYNC1_PD SPI_ SYNC2_PD 0x00 R/W 0x206 CDR_RESET RESERVED SPI_CDR_ RESETN 0x01 R/W 0x230 CDR_OPERATING_ MODE_REG_0 RESERVED ENHALFRATE RESERVED CDR_ OVERSAMP RESERVED 0x28 R/W 0x232 DEVICE_CONFIG_ REG_3 DEVICE_CONFIG_3 0x0 R/W 0x268 EQ_BIAS_REG EQ_POWER_MODE RESERVED 0x62 R/W 0x280 SERDESPLL_ ENABLE_CNTRL RESERVED RECAL_ SERDESPLL RESERVED ENABLE_ SERDESPLL 0x00 R/W 0x281 PLL_STATUS RESERVED SERDES_PLL_ OVERRANGE_ H SERDES_PLL_ OVERRANGE_L SERDES_PLL_CAL_ VALID_RB RESERVED SERDES_PLL_ LOCK_RB 0x00 R 0x284 LOOP_FILTER_1 LOOP_FILTER_1 0x77 R/W 0x285 LOOP_FILTER_2 LOOP_FILTER_2 0x87 R/W 0x286 LOOP_FILTER_3 LOOP_FILTER_3 0x08 R/W

Rev. C | Page 85 of 117 Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W 0x287 SERDES_PLL_CP1 SERDES_PLL_CP1 0x3F R/W 0x289 REF_CLK_ DIVIDER_LDO RESERVED DEVICE_ CONFIG_4 SERDES_PLL_DIV_MODE 0x00 R/W 0x28A VCO_LDO SERDES_PLL_VCO_LDO 0x2B R/W 0x28B SERDES_PLL_PD1 SERDES_PLL_PD1 0x7F R/W 0x290 SERDESPLL_VAR1 SERDES_PLL_VAR1 0x83 R/W 0x294 SERDES_PLL_CP2 SERDES_PLL_CP2 0xB0 R/W 0x296 SERDESPLL_VCO1 SERDES_PLL_VCO1 0x0C R/W 0x297 SERDESPLL_VCO2 SERDES_PLL_VCO2 0x00 R/W 0x299 SERDES_PLL_PD2 SERDES_PLL_PD2 0x00 R/W 0x29A SERDESPLL_VAR2 SERDES_PLL_VAR2 0xFE R/W 0x29C SERDES_PLL_CP3 SERDES_PLL_CP3 0x17 R/W 0x29F SERDESPLL_VAR3 SERDES_PLL_VAR3 0x33 R/W 0x2A0 SERDESPLL_VAR4 SERDES_PLL_VAR4 0x08 R/W 0x2A4 DEVICE_CONFIG_ REG_8 DEVICE_CONFIG_8 0x4B R/W 0x2A5 SYNCOUTB_ SWING RESERVED SYNCOUTB_ SWING_MD 0x00 R/W 0x2A7 TERM_BLK1_ CTRLREG0 RESERVED RCAL_ TERMBLK1 0x00 R/W 0x2AA DEVICE_CONFIG_ REG_9 DEVICE_CONFIG_9 0xC3 R/W 0x2AB DEVICE_CONFIG_ REG_10 DEVICE_CONFIG_10 0x93 R/W 0x2AE TERM_BLK2_ CTRLREG0 RESERVED RCAL_ TERMBLK2 0x00 R/W 0x2B1 DEVICE_CONFIG_ REG_11 DEVICE_CONFIG_11 0xC3 R/W 0x2B2 DEVICE_CONFIG_ REG_12 DEVICE_CONFIG_12 0x93 R/W 0x300 GENERAL_JRX_ CTRL_0 RESERVED CHECKSUM _MODE RESERVED LINK_MODE LINK_PAGE LINK_EN 0x00 R/W 0x301 GENERAL_JRX_ CTRL_1 RESERVED SUBCLASSV_LOCAL 0x01 R/W 0x302 DYN_LINK_ LATENCY_0 RESERVED DYN_LINK_LATENCY_0 0x00 R 0x303 DYN_LINK_ LATENCY_1 RESERVED DYN_LINK_LATENCY_1 0x00 R 0x304 LMFC_DELAY_0 RESERVED LMFC_DELAY_0 0x00 R/W 0x305 LMFC_DELAY_1 RESERVED LMFC_DELAY_1 0x00 R/W 0x306 LMFC_VAR_0 RESERVED LMFC_VAR_0 0x06 R/W 0x307 LMFC_VAR_1 RESERVED LMFC_VAR_1 0x06 R/W 0x308 XBAR_LN_0_1 RESERVED LOGICAL_LANE1_SRC LOGICAL_LANE0_SRC 0x08 R/W 0x309 XBAR_LN_2_3 RESERVED LOGICAL_LANE3_SRC LOGICAL_LANE2_SRC 0x1A R/W 0x30A XBAR_LN_4_5 RESERVED LOGICAL_LANE5_SRC LOGICAL_LANE4_SRC 0x2C R/W 0x30B XBAR_LN_6_7 RESERVED LOGICAL_LANE7_SRC LOGICAL_LANE6_SRC 0x3E R/W 0x30C FIFO_STATUS_ REG_0 LANE_FIFO_FULL 0x00 R 0x30D FIFO_STATUS_ REG_1 LANE_FIFO_EMPTY 0x00 R 0x312 SYNCB_GEN_1 RESERVED SYNCB_ERR_DUR RESERVED 0x00 R/W 0x314 SERDES_SPI_REG SERDES_SPI_CONFIG 0x00 R/W 0x315 PHY_PRBS_TEST_ EN PHY_TEST_EN 0x00 R/W

Rev. C | Page 86 of 117 Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W 0x316 PHY_PRBS_TEST_ CTRL RESERVED PHY_SRC_ERR_CNT PHY_PRBS_PAT_SEL PHY_TEST_ START PHY_TEST_ RESET 0x00 R/W 0x317 PHY_PRBS_TEST_ THRESHOLD_ LOBITS PHY_PRBS_THRESHOLD[7:0] 0x00 R/W 0x318 PHY_PRBS_TEST_ THRESHOLD_ MIDBITS PHY_PRBS_THRESHOLD[15:8] 0x00 R/W 0x319 PHY_PRBS_TEST_ THRESHOLD_ HIBITS PHY_PRBS_THRESHOLD[23:16] 0x00 R/W 0x31A PHY_PRBS_TEST_ ERRCNT_LOBITS PHY_PRBS_ERR_CNT[7:0] 0x00 R 0x31B PHY_PRBS_TEST_ ERRCNT_MIDBITS PHY_PRBS_ERR_CNT[15:8] 0x00 R 0x31C PHY_PRBS_TEST_ ERRCNT_HIBITS PHY_PRBS_ERR_CNT[23:16] 0x00 R 0x31D PHY_PRBS_TEST_ STATUS PHY_PRBS_PASS 0xFF R 0x32C SHORT_TPL_ TEST_0 RESERVED SHORT_TPL_SP_SEL SHORT_TPL_DAC_SEL SHORT_TPL_ TEST_RESET SHORT_TPL_ TEST_EN 0x00 R/W 0x32D SHORT_TPL_ TEST_1 SHORT_TPL_REF_SP_LSB 0x00 R/W 0x32E SHORT_TPL_ TEST_2 SHORT_TPL_REF_SP_MSB 0x00 R/W 0x32F SHORT_TPL_ TEST_3 RESERVED SHORT_ TPL_FAIL 0x00 R 0x333 DEVICE_CONFIG_ REG_13 DEVICE_CONFIG_13 0x00 R/W 0x334 JESD_BIT_ INVERSE_CTRL JESD_BIT_INVERSE 0x00 R/W 0x400 DID_REG DID_RD 0x00 R 0x401 BID_REG ADJCNT_RD BID_RD 0x00 R 0x402 LID0_REG RESERVED ADJDIR_RD PHADJ_RD LID0_RD 0x00 R 0x403 SCR_L_REG SCR_RD RESERVED L-1_RD 0x00 R 0x404 F_REG F-1_RD 0x00 R 0x405 K_REG RESERVED K-1_RD 0x00 R 0x406 M_REG M-1_RD 0x00 R 0x407 CS_N_REG CS_RD RESERVED N-1_RD 0x00 R 0x408 NP_REG SUBCLASSV_RD NP-1_RD 0x00 R 0x409 S_REG JESDV_RD S-1_RD 0x00 R 0x40A HD_CF_REG HD_RD RESERVED CF_RD 0x00 R 0x40B RES1_REG RES1_RD 0x00 R 0x40C RES2_REG RES2_RD 0x00 R 0x40D CHECKSUM_REG FCHK0_RD 0x00 R 0x40E COMPSUM0_REG FCMP0_RD 0x00 R 0x412 LID1_REG RESERVED LID1_RD 0x00 R 0x415 CHECKSUM1_REG FCHK1_RD 0x00 R 0x416 COMPSUM1_REG FCMP1_RD 0x00 R 0x41A LID2_REG RESERVED LID2_RD 0x00 R 0x41D CHECKSUM2_REG FCHK2_RD 0x00 R 0x41E COMPSUM2_REG FCMP2_RD 0x00 R 0x422 LID3_REG RESERVED LID3_RD 0x00 R 0x425 CHECKSUM3_REG FCHK3_RD 0x00 R

Rev. C | Page 87 of 117 Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W 0x426 COMPSUM3_REG FCMP3_RD 0x00 R 0x42A LID4_REG RESERVED LID4_RD 0x00 R 0x42D CHECKSUM4_REG FCHK4_RD 0x00 R 0x42E COMPSUM4_REG FCMP4_RD 0x00 R 0x432 LID5_REG RESERVED LID5_RD 0x00 R 0x435 CHECKSUM5_REG FCHK5_RD 0x00 R 0x436 COMPSUM5_REG FCMP5_RD 0x00 R 0x43A LID6_REG RESERVED LID6_RD 0x00 R 0x43D CHECKSUM6_REG FCHK6_RD 0x00 R 0x43E COMPSUM6_REG FCMP6_RD 0x00 R 0x442 LID7_REG RESERVED LID7_RD 0x00 R 0x445 CHECKSUM7_REG FCHK7_RD 0x00 R 0x446 COMPSUM7_REG FCMP7_RD 0x00 R 0x450 ILS_DID DID 0x00 R/W 0x451 ILS_BID ADJCNT BID 0x00 R/W 0x452 ILS_LID0 RESERVED ADJDIR PHADJ LID0 0x00 R/W 0x453 ILS_SCR_L SCR RESERVED L-1 0x83 R/W 0x454 ILS_F F-1 0x00 R/W 0x455 ILS_K RESERVED K-1 0x1F R/W 0x456 ILS_M M-1 0x01 R/W 0x457 ILS_CS_N CS RESERVED N-1 0x0F R/W 0x458 ILS_NP SUBCLASSV NP-1 0x2F R/W 0x459 ILS_S JESDV S-1 0x20 R/W 0x45A ILS_HD_CF HD RESERVED CF 0x80 R/W 0x45B ILS_RES1 RES1 0x00 R/W 0x45C ILS_RES2 RES2 0x00 R/W 0x45D ILS_CHECKSUM FCHK0 0x45 R/W 0x46B ERRCNTRMON_RB READERRORCNTR 0x00 R 0x46B ERRCNTRMON RESERVED LANESEL RESERVED CNTRSEL 0x00 R/W 0x46C LANEDESKEW LANEDESKEW 0x0F R/W 0x46D BADDISPARITY_RB BADDIS 0x00 R 0x46D BADDISPARITY RST_IRQ_ DIS DISABLE_ ERR_CNTR_ DIS RST_ERR_ CNTR_DIS RESERVED LANE_ADDR_DIS 0x00 R/W 0x46E NIT_RB NIT 0x00 R 0x46E NIT_W RST_IRQ_ NIT DISABLE_ ERR_CNTR_ NIT RST_ERR_ CNTR_NIT RESERVED LANE_ADDR_NIT 0x00 R/W 0x46F UNEXPECTED- CONTROL_RB UCC 0x00 R 0x46F UNEXPECTED- CONTROL_W RST_IRQ_ UCC DISABLE_ ERR_CNTR_ UCC RST_ERR_ CNTR_UCC RESERVED LANE_ADDR_UCC 0x00 R/W 0x470 CODEGRPSYNCFLG CODEGRPSYNC 0x00 R/W 0x471 FRAMESYNCFLG FRAMESYNC 0x00 R/W 0x472 GOODCHKSUMFLG GOODCHECKSUM 0x00 R/W 0x473 INITLANESYNCFLG INITIALLANESYNC 0x00 R/W 0x476 CTRLREG1 F 0x01 R/W 0x477 CTRLREG2 ILAS_ MODE RESERVED THRESHOLD_ MASK_EN RESERVED 0x00 R/W 0x478 KVAL KSYNC 0x01 R/W

Table 85. Device Configuration Register Descriptions during multibyte data transfers.

1 Addresses are incremented during multibyte

0 Addresses are decremented during

data are oriented as LSB first or MSB first.

1 Shift LSB in first

0 Shift MSB in first

0 SOFTRESET Soft Reset. Setting this bit initiates a reset.

1 Assert soft reset

is represented by a code of 0x04. Register 0x135 to Register 0x14C.

Rev. C | Page 89 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x00A SCRATCH_PAD [7:0] SCRATCHPAD This register does not affect any functions in the part and can be used for testing SPI communication with the part. Any value written to this register will be read back to reflect the change unless a reset or power- cycle occurs. 0x00 R/W 0x011 PWRCNTRL0 7 PD_BG Reference Power-Down. Powers down the band gap reference for the entire chip. Circuits will not be provided with bias currents. 0x0 R/W

1 Power down reference

6 PD_DAC_0 Powers Down DAC0. Powers down the I-channel DAC. 0x1 R/W

1 Powers down DAC0

5 RESERVED Reserved. 0x0 R 4 PD_DAC_1 Powers Down DAC1. Powers down the Q-channel DAC. 0x1 R/W

1 Powers down DAC1

3 RESERVED Reserved. 0x0 R 2 PD_DACM Powers Down the DAC Master Bias. The master bias cell provides currents and DAC full-scale adjustments to the four DACs. With the DAC master bias powered down, the DACs are inoperative. 0x1 R/W

1 Powers down the DAC master bias

[1:0] RESERVED Reserved. 0x0 R 0x012 TXENMASK [7:2] RESERVED Reserved. 0x0 R 1 D AC1_MASK DAC1 TXEN1 Mask. Power down DAC1 on a falling edge of TXEN1. 0x0 R/W

1 If TXEN1 is low, power down DAC1

0 DAC0_MASK DAC0 TXEN0 Mask. Power down DAC0 on a falling edge of TXEN0. 0x0 R/W

1 If TXEN0 is low, power down DAC0

0x013 PWRCNTRL3 [7 :6] RESERVED Reserved. 0x0 R 5 TX_PROTECT_OUT 1 TX_PROTECT triggers PROTECT_OUTx. 0x1 R/W 4 RESERVED Reserved. 0x0 R

3 SPI_PROTECT_

1 SPI_PROTECT triggers PROTECT_OUTx. 0x0 R/W

2 SPI_PROTECT SPI_PROTECT 0x0 R/W

[1:0] RESERVED Reserved. 0x0 R 0x014 GROUP_DLY [7:4] RESERVED Reserved. 0x8 R [3:0] GROUP_DLY Group Delay Control. Delays the selected DAC channel output per the paging register. 0 = minimum delay. 15 = maximum delay. The range of the delay is −4 to +3.5 DAC clock periods, and the resolution is 1/2 DAC clock period. 0x8 R/W 0x01F IRQEN_ STATUSMODE0

7 IRQEN_SMODE_

Calibration Pass Detection Status Mode. 0x0 R/W

1 If CALPASS goes high, it latches and pulls IRQ

0 CALPASS shows current status

6 IRQEN_SMODE_

Calibration Fail Detection Status Mode. 0x0 R/W

1 If CALFAIL goes high, it latches and pulls IRQ

0 CALFAIL shows current status

5 IRQEN_SMODE_

DAC PLL Lost Detection Status Mode. 0x0 R/W

1 If DACPLLLOST goes high, it latches and

0 DACPLLLOST shows current status

Rev. C | Page 90 of 117 Address Name Bit No. Bit Name Settings Description Reset Access

4 IRQEN_SMODE_

DAC PLL Lock Detection Status Mode. 0x0 R/W

1 If DACPLLLOCK goes high, it latches and

0 DACPLLLOCK shows current status

3 IRQEN_SMODE_

SERDES PLL Lost Detection Status Mode. 0x0 R/W

1 If SERPLLLOST goes high, it latches and

0 SERPLLLOST shows current status

2 IRQEN_SMODE_

SERDES PLL Lock Detection Status Mode. 0x0 R/W

1 If SERPLLLOCK goes high, it latches and

0 SERPLLLOCK shows current status

1 IRQEN_SMODE_

Lane FIFO Error Detection Status Mode. 0x0 R/W

1 If LANEFIFOERR goes high, latches and

0 LANEFIFOERR shows current status

0 RESERVED Reserved. 0x0 R 0x020 IRQEN_ STATUSMODE1 [7:3] RESERVED Reserved. 0x0 R DAC1 PRBS Error Status Mode. 0x0 R/W

1 If PRBS1 goes high, it latches and pulls IRQ

0 PRBS1 shows current status

1 RESERVED 0x0 R/W

0 IRQEN_SMODE_

DAC0 PRBS Error Status Mode. 0x0 R/W

1 If PRBS0 goes high, it latches and pulls IRQ

0 PRBS0 shows current status

0x021 IRQEN_ STATUSMODE2 DAC0 PDP Error. 0x0 R/W

1 If PDPERR0 goes high, it latches and pulls IRQ

0 PDPERR0 shows current status

6 RESERVED Reserved. 0x0 R DAC0 Blanking Done Status Mode. 0x0 R/W

1 If BLNKDONE0 goes high, it latches and

0 BLNKDONE0 shows current status

4 RESERVED Reserved. 0x0 R SYNC_LOCK0 DAC0 Alignment Locked Status Mode. 0x0 R/W

1 If SYNC_LOCK0 goes high, it latches and

0 SYNC_LOCK0 shows current status

SYNC_ROTATE0 DAC0 Alignment Rotate Status Mode. 0x0 R/W

1 If SYNC_ROTATE0 goes high, it latches and

0 SYNC_ROTATE0 shows current status

SYNC_WLIM0 DAC0 Outside Window Status Mode. 0x0 R/W

1 If SYNC_WLIM0 goes high, it latches and

0 SYNC_WLIM0 shows current status

SYNC_TRIP0 DAC0 Alignment Tripped Status Mode. 0x0 R/W

1 If SYNC_TRIP0 goes high, it latches and

0 SYNC_TRIP0 shows current status

Rev. C | Page 91 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x022 IRQEN_ STATUSMODE3 DAC1 PDP Error. 0x0 R/W

1 If PDPERR1 goes high, it latches and pulls IRQ

0 PDPERR1 shows current status

6 RESERVED Reserved. 0x0 R DAC1 Blanking Done Status Mode. 0x0 R/W

1 If BLNKDONE1 goes high, it latches and

0 BLNKDONE1 shows current status

4 RESERVED Reserved. 0x0 R SYNC_LOCK1 DAC1 Alignment Locked Status Mode. 0x0 R/W

1 If SYNC_LOCK1 goes high, it latches and

0 SYNC_LOCK1 shows current status

SYNC_ROTATE1 DAC1 Alignment Rotate Status Mode. 0x0 R/W

1 If SYNC_ROTATE1 goes high, it latches and

0 SYNC_ROTATE1 shows current status

SYNC_WLIM1 DAC1 Outside Window Status Mode. 0x0 R/W

1 If SYNC_WLIM1 goes high, it latches and

0 SYNC_WLIM1 shows current status

SYNC_TRIP1 DAC1 Alignment Tripped Status Mode. 0x0 R/W

1 If SYNC_TRIP1 goes high, it latches and

0 SYNC_TRIP1 shows current status

0x023 IRQ_STATUS0 7 CALPASS Calibration Pass Status. If IRQEN_SMODE_CALPASS is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 Calibration passed

6 CALFAIL Calibration Fail Detection Status. If IRQEN_SMODE_CALFAIL is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 Calibration failed

5 DACPLLLOST DAC PLL Lost Status. If IRQEN_SMODE_DACPLLLOST is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC PLL lock was lost

4 DACPLLLOCK DAC PLL Lock Status. If IRQEN_SMODE_DACPLLLOCK is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC PLL locked

3 SERPLLLOST SERDES PLL Lost Status. If IRQEN_SMODE_SERPLLLOST is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 SERDES PLL lock was lost

Rev. C | Page 92 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 2 SERPLLLOCK SERDES PLL Lock Status. If IRQEN_SMODE_SERPLLLOCK is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 SERDES PLL locked

1 LANEFIFOERR Lane FIFO Error Status. If IRQEN_SMODE_LANEFIFOERR is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. A lane FIFO error occurs when there is a full or empty condition on any of the FIFOs between the deserializer block and the core digital. This error requires a link disable and reenable to remove it. The status of the lane FIFOs can be found in Register 0x30C (FIFO full), and Register 0x30D (FIFO empty). 0x0 R

1 Lane FIFO error

0 RESERVED Reserved. 0x0 R 0x024 IRQ_STATUS1 [7:3] RESERVED Reserved. 0x0 R 2 PRBS1 DAC1 PRBS Error Status. If IRQEN_SMODE_PRBS1 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC1 failed PRBS

1 RESERVED Reserved. 0x0 R 0 PRBS0 DAC0 PRBS Error Status. If IRQEN_SMODE_PRBS0 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC0 failed PRBS

0x025 IRQ_STATUS2 7 PDPERR0 DAC0 PDP Error. If IRQEN_SMODE_PAERR0 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 Data into DAC0 over power threshold

6 RESERVED Reserved. 0x0 R 5 BLNKDONE0 DAC0 Blanking Done Status. If IRQEN_SMODE_BLNKDONE0 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC0 blanking done

4 RESERVED Reserved 0x0 R

3 SYNC_LOCK0 DAC0 LMFC Alignment Locked Status. If IRQEN_SMODE_SYNC_LOCK0 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC0 LMFC alignment locked

2 SYNC_ROTATE0 DAC0 LMFC Alignment Rotate Status. If IRQEN_SMODE_SYNC_ROTATE0 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC0 LMFC alignment rotated

Rev. C | Page 93 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 1 SYNC_WLIM0 DAC0 Outside Window Status. If IRQEN_SMODE_SYNC_WLIM0 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC0 LMFC phase outside of window

0 SYNC_TRIP0 DAC0 LMFC Alignment Tripped Status. If IRQEN_SMODE_SYNC_TRIP0 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC0 LMFC alignment tripped

0x026 IRQ_STATUS3 7 PDPERR1 DAC1 PDP Error. If IRQ_SMODE_PDPERR1 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 Data into DAC1 over power threshold

6 RESERVED Reserved. 0x0 R 5 BLNKDONE1 DAC1 Blanking Done Status. If IRQEN_SMODE_BLNKDONE1 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC1 blanking done

4 RESERVED Reserved. 0x0 R 3 SYNC_LOCK1 DAC1 LMFC Alignment Locked Status. If IRQEN_SMODE_SYNC_LOCK1 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC1 LMFC alignment locked

2 SYNC_ROTATE1 DAC1 LMFC Alignment Rotate Status. If IRQEN_SMODE_SYNC_ROTATE1 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC1 LMFC alignment rotated

1 SYNC_WLIM1 DAC1 Outside Window Status. If IRQEN_SMODE_SYNC_WLIM1 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC1 LMFC phase outside of window

0 SYNC_TRIP1 DAC1 LMFC Alignment Tripped Status. If IRQEN_SMODE_SYNC_TRIP1 is low, this bit shows current status. If not, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. 0x0 R

1 DAC1 LMFC alignment tripped

0x030 JESD_CHECKS [7:6] RESERVED Reserved. 0x0 R 5 ERR_DLYOVER Error: LMFC_Delay > JESD_K Parameter. 0x0 R

1 LMFC_Delay > JESD_K

4 ERR_WINLIMIT Unsupported Window Limit. 0x0 R

1 Unsupported SYSREF window limit

3 ERR_JESDBAD Unsupported M/L/S/F Selection. 0x0 R

1 This JESD combination is not supported

2 ERR_KUNSUPP Unsupported K Values. 16 and 32 are supported. 0x0 R

1 K value unsupported

Rev. C | Page 94 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 1 ERR_SUBCLASS Unsupported Subclass Value. 0 and 1 are supported. 0x0 R

1 Unsupported subclass value

0 ERR_INTSUPP Unsupported Interpolation Rate Factor. 1, 2, 4, 8 are supported. 0x0 R

1 Unsupported interpolation rate factor

0x034 SYNC_ERRWINDOW [7:2] RESERVED Reserved. 0x0 R [1:0] ERRWINDOW LMFC Sync Error Window. The error window allows the SYSREF sample phase to vary within the confines of the window without triggering a clock adjustment. This is useful if SYSREF cannot be guaranteed to always arrive in the same period of the device clock associated with the target phase. Error window tolerance = ± ERRWINDOW 0x0 R/W 0x038 SYNC_LASTERR_L [7:4] RESERVED Reserved. 0x0 R [3:0] LASTERROR LMFC Sync Last Alignment Error. 4-bit twos complement value that represents the phase error (in number of DAC clock cycles) when the clocks were last adjusted. R 0x039 SYNC_LASTERR_H 7 LASTUNDER LMFC Sync Last Error Under Flag. 0x0 R

1 Last phase error was beyond lower window

6 LASTOVER LMFC Sync Last Error Over Flag. 0x0 R

1 Last phase error was beyond upper window

[5:0] RESERVED Reserved. 0x0 R 0x03A SYNC_CONTROL 7 SYNCENABLE LMFC Sync Logic Enable. 0x0 R/W

1 Enable sync logic

0 Disable sync logic

6 SYNCARM LMFC Sync Arming Strobe. 0x0 R/W

1 Sync one-shot armed

5 SYNCCLRSTKY LMFC Sync Sticky Bit Clear. On a rising edge, this bit clears SYNC_ROTATE and SYNC_TRIP. 0x0 R/W 4 SYNCCLRLAST LMFC Sync Clear Last Error. On a rising edge, this bit clears LASTERROR, LASTUNDER, LASTOVER. 0x0 R/W [3:0] SYNCMODE LMFC Sync Mode. 0x0 R/W 0b0001 Sync one-shot mode 0b0010 Sync continuous mode 0b1000 Sync monitor only mode 0b1001 Sync one-shot, then monitor 0x03B SYNC_STATUS 7 SYNC_BUSY LMFC Sync Machine Busy. 0x0 R

1 Sync logic SM is busy

[6:4] RESERVED Reserved. 0x0 R 3 SYNC_LOCK LMFC Sync Alignment Locked. 0x0 R

1 Sync logic aligned within window

2 SYNC_ROTATE LMFC Sync Rotated. 0x0 R

1 Sync logic rotated with SYSREF (sticky)

1 SYNC_WLIM LMFC Sync Alignment Limit Range. 0x0 R

1 Phase error outside window threshold

0 SYNC_TRIP LMFC Sync Tripped After Arming. 0x0 R

1 Sync received SYSREF pulse (sticky)

Rev. C | Page 95 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x03C SYNC_CURRERR_L [7:4] RESERVED Reserved. 0x0 R [3:0] CURRERROR LMFC Sync Alignment Error. 4-bit twos complement value that represents the phase error in number of DAC clock cycles (that is, number of DAC clocks between LMFC edge and SYSREF edge). When an adjustment of the clocks is made on any given SYSREF, the value of the phase error is placed into SYNC_ LASTERR, and SYNC_CURRERR is forced to 0. 0x0 R 0x03D SYNC_CURRERR_H 7 CURRUNDER LMFC Sync Current Error Under Flag. 0x0 R

1 Current phase error is beyond lower window

6 CURROVER LMFC Sync Current Error Over Flag. 0x0 R

1 Current phase error is beyond upper window

[5:0] RESERVED Reserved. 0x0 R 0x040 DACGAIN0_1 [7:2] RESERVED Reserved. 0x0 R [1:0] DACFSC_0[9:8] 2 MSBs of I-Channel DAC Gain DAC0. A 10-bit twos complement value that is mapped to analog full-scale current for DAC0 as shown: 0x0 R/W 01111111111 = 27.0 mA 0000000000 = 20.48 mA 1000000000 = 13.9 mA 0x041 DACGAIN0_0 [7:0] DACFSC_0[7:0] 8 LSBs of I-Channel DAC Gain DAC0. 0x0 R/W 0x044 DACGAIN1_1 [7:2] RESERVED Reserved. 0x0 R [1:0] DACFSC_1[9:8] 2 MSBs of Q-Channel DAC Gain DAC1. A 10-bit twos complement value that is mapped to analog full-scale current for DAC as shown in Register 0x040. 0x0 R/W 01111111111 = 27.0 mA 0000000000 = 20.48 mA 1000000000 = 13.9 mA 0x045 DACGAIN1_0 [7:0] DACFSC_1[7:0] 8 LSBs of Q-Channel DAC Gain DAC1. 0x0 R/W 0x080 CLKCFG0 7 PD_CLK0 Power-Down Clock for DAC0. This bit disables the digital and analog clocks for DAC0. 0x1 R/W 6 PD_CLK1 Power-Down Clock for DAC1. This bit disables the digital and analog clocks for DAC1. 0x1 R/W 5 PD_CLK_DIG Power-Down Clocks to all DACs. This bit disables the digital and analog clocks for both duals. This includes all reference clocks, PCLK, DAC clocks, and digital clocks. 0x1 R/W 4 PD_SERDES_PCLK Serdes PLL Clock Power-Down. This bit disables the reference clock to the SERDES PLL, which is needed to have an operational serial interface. 0x1 R/W 3 PD_CLK_REC Clock Receiver Power-Down. This bit powers down the analog DAC clock receiver block. With this bit set, clocks are not passed to internal nets. 0x1 R/W [2:0] RESERVED Reserved. 0x0 R

Rev. C | Page 96 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x081 SYSREF_ACTRL0 [7:5] RESERVED Reserved. 0x0 R 4 PD_SYSREF Power-Down SYSREF Buffer. This bit powers down the SYSREF receiver. For Subclass 1 operation to work, this buffer must be enabled. 0x1 R/W 3 HYS_ON Hysteresis Enabled. This bit enables the programmable hysteresis control for the SYSREF receiver. Using hysteresis gives some noise resistance, but delays the SYSREF± edge an amount depending on HYS_CNTRL and the SYSREF± edge rate. The SYSREF± KOW is not guaranteed when using hysteresis. 0x0 R/W 2 SYSREF_RISE Select DAC Clock Edge to Sample SYSREF. 0x0 R/W

0 Use falling edge of DAC clock to sample

1 Use rising edge of DAC clock to sample

[1:0] HYS_CNTRL1 Hysteresis Control Bits[9:8]. HYS_CNTRL is a 10-bit thermometer-coded number. Each bit set adds 10 mV of differential hysteresis to the SYSREF receiver. 0x0 R/W 0x082 SYSREF_ACTRL1 [7:0] HYS_CNTRL0 Hysteresis Control Bits[7:0]. 0x0 R/W 0x083 DACPLLCNTRL 7 RECAL_DACPLL Recalibrate DAC PLL. On a rising edge of this bit, recalibrate the DAC PLL. 0x0 R/W [6:5] RESERVED Reserved. 0x0 R 4 ENABLE_DACPLL Synthesizer Enable. This bit enables and calibrates the DAC PLL. 0x0 R/W [3:0] RESERVED Reserved. 0x0 R 0x084 DACPLLSTATUS 7 DACPLL_ OVERRANGE_H DAC PLL High Overrange. This bit indicates that the DAC PLL hit the upper edge of its operating band. Recalibrate. 0x0 R

6 DACPLL_

OVERRANGE_L DAC PLL Low Overrange. This bit indicates that the DAC PLL hit the lower edge of its operating band. Recalibrate. 0x0 R

5 DACPLL_CAL_

DAC PLL Calibration Valid. This bit indicates that the DAC PLL has been successfully calibrated. 0x0 R [4:2] RESERVED Reserved. 0x0 R 1 DACPLL_LOCK DAC PLL Lock Bit. This bit is set high by the PLL when it has achieved lock. 0x0 R 0 RESERVED Reserved. 0x0 R 0x085 DACINTEGERWORD0 [7:0] B_COUNT Integer Division Word. This bit controls the integer feedback divider for the DAC PLL. Determine the frequency of the DAC clock by the following equations (see the Clock Multiplication section for more details): 0x8 R/W fDAC = fREF/(REF_DIVRATE) × 2 × B_COUNT fVCO = fREF/(REF_DIVRATE) × 2 × B_COUNT × LO_DIV_MODE Minimum value is 6. 0x087 DACLOOPFILT1 [7:4] LF_C2_WORD C2 Control Word. Set this control to 0x6 for optimal performance. 0x8 R/W [3:0] LF_C1_WORD C1 Control Word. Set this control to 0x2 for optimal performance. 0x8 R/W 0x088 DACLOOPFILT2 [7:4] LF_R1_WORD R1 Control Word. Set this control to 0xC for optimal performance. 0x8 R/W [3:0] LF_C3_WORD C3 Control Word. Set this control to 0x9 for optimal performance. 0x8 R/W

Rev. C | Page 97 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x089 DACLOOPFILT3 7 LF_BYPASS_R3 Bypass R3 Resistor. When this bit is set, bypass the R3 capacitor (set to 0 pF) when R3_WORD is set to 0. Set this control to 0x0 for optimal performance. 0x0 R/W 6 LF_BYPASS_R1 Bypass R1 Resistor. When this bit is set, bypass the R1 capacitor (set to 0 pF) when R1_WORD is set to 0. Set this control to 0x0 for optimal performance. 0x0 R/W 5 LF_BYPASS_C2 Bypass C2 Capacitor. When this bit is set, bypass the C2 capacitor (set to 0 pF) when C2_WORD is set to 0. Set this control to 0x0 for optimal performance. 0x0 R/W 4 LF_BYPASS_C1 Bypass C1 Capacitor. When this bit is set, bypass the C1 capacitor (set to 0 pF) when C1_WORD is set to 0. Set this control to 0x0 for optimal performance. 0x0 R/W [3:0] LF_R3_WORD R3 Control Word. Set this control to 0xE for optimal performance. 0x8 R/W 0x08A DACCPCNTRL [7:6] RESERVED Reserved. 0x0 R [5:0] CP_CURRENT Charge Pump Current Control. Set this control to 0x12 for optimal performance. 0x20 R/W 0x08B DACLOGENCNTRL [7:2] RESERVED Reserved. 0x0 R [1:0] LO_DIV_MODE This range controls the RF clock divider between the VCO and DAC clock rates. The options are 4×, 8×, or 16× division. Choose the LO_DIV_MODE so that 6 GHz < fVCO < 12 GHz (see the Clock Multiplication section for more details): 0x2 R/W

01 DAC clock = VCO/4

10 DAC clock = VCO/8

11 DAC clock = VCO/16

0x08C DACLDOCNTRL1 [7:3] RESERVED Reserved. 0x0 R [2:0] REF_DIV_MODE Reference Clock Division Ratio. This field controls the amount of division that is done to the input clock at the CLK+/CLK− pins before it is presented to the PLL as a reference clock. The reference clock frequency must be between 35 MHz and 80 MHz, but the CLK+/CLK− input frequency can range from 35 MHz to 1 GHz. The user sets this division to achieve a 35 MHz to 80 MHz PLL reference frequency. For more details see the Clock Multiplication section. 0x1 R/W 000 1 001 2 010 4 011 8 100 16 0x08D DACLDOCNTRL2 [7:0] DAC_LDO DAC PLL LDO setting. This register must be written to 0x7B for optimal performance. 0x2B R/W 0x0E2 CAL_CTRL_GLOBAL [7:2] RESERVED Reserved. 0x0 R 1 CAL_START_AVG Averaged Calibration Start. On rising edge, calibrate the DACs. Only use if calibrating all DACs. 0x0 R/W 0 CAL_EN_AVG Averaged Calibration Enable. Set prior to starting calibration with CAL_START_AVG. While this bit is set, calibration can be performed, and the results are applied. 0x0 R/W

1 Enable averaged calibration

Rev. C | Page 98 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x0E7 CAL_CLKDIV [7:4] RESERVED Must write the default value for proper operation. 0x3 R/W 3 CAL_CLK_EN Enable Self Calibration Clock. 0x0 R/W

1 Enable calibration clock

0 Disable calibration clock

[2:0] RESERVED Reserved. 0x0 R 0x0E8 CAL_PAGE [7:4] RESERVED Reserved. 0x0 R [3:0] CAL_PAGE DAC Calibration Paging. Selects which of the DACs are being accessed for calibration or calibration readback. This paging affects Register 0x0E9 and Register 0x0ED. 0xF R/W Calibration: any number of DACs can be accessed simultaneously to write and calibrate. Write a 1 to Bit 0 to include DAC0. Write a 1 to Bit 2 to include DAC1. Readback: only one DAC at a time can be accessed when reading back CAL_CTRL (Register 0x0E9). Write a 1 to Bit 0 to read from DAC0 or write a 1 to Bit 2 to read from DAC1 (the other bits must be 0). 0x0E9 CAL_CTRL 7 CAL_FIN Calibration finished. This bit is high when the calibration has completed. If the calibration completes and either CAL_ERRHI or CAL_ ERRLO is high, then the calibration cannot be considered valid and are considered a timeout event. 0x0 R

1 Calibration ran and is finished

6 CAL_ACTIVE Calibration Active. This bit is high while the calibration is in progress. 0x0 R

1 Calibration is running

5 CAL_ERRHI SAR Data Error: Too High. This bit is set at the end of a calibration cycle if any of the calibra- tion DACs has overranged to the high side. This typically means that the algorithm adjusts the calibration preset of the calibration DACs and runs another cycle. 0x0 R

1 Data saturated high

4 CAL_ERRLO SAR Data Error: Too Low. This bit is set at the end of a calibration cycle if any of the calibra- tion DACs has overranged to the low side. This typically means that the algorithm adjusts the calibration preset of the calibration DACs and runs another cycle. 0x0 R

1 Data saturated low

[3:2] RESERVED Reserved. 0x0 R 1 CAL_START Calibration Start. The rising edge of this bit kicks off a calibration sequence for the DACs that have been selected in the CAL_INDX register. 0x0 R/W

0 Normal operation

1 Start calibration state machine

0 CAL_EN Calibration Enable. Enable the calibration DAC of the converter. Enable to calibration engine and machines. Prepare for a calibration start. For calibration coefficients to be applied to the calibrated DACs, this bit must be high. 0x0 R/W

0 Do not use calibration DACs

1 Use calibration DACs

Rev. C | Page 99 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x0ED CAL_INIT [7:0] CAL_INIT Initialize Calibration. Must be written to 0xA2 before starting calibration or averaged calibration. 0xA6 R/W 0x110 DATA_FORMAT 7 BINARY_FORMAT Binary or Twos Complementary Format on the Data Bus. 0x0 R/W

0 Input data is twos complement

1 Input data is offset binary

[6:0] RESERVED Reserved. 0x0 R 0x111 DATAPATH_CTRL 7 INVSINC_ENABLE Enable Inverse Sinc Filter. 0x1 R/W

1 Enable inverse sinc filter

0 Disable inverse sinc filter

6 RESERVED Reserved. 0x0 R 5 DIG_GAIN_ENABLE Enable Digital Gain. 0x1 R/W

1 Enable digital gain function

0 Disable digital gain function

[4:0] RESERVED Reserved 0x0 R 0x112 INTERP_MODE [7:3] RESERVED Reserved. 0x0 R [2:0] INTERP_MODE Interpolation Mode. 0x1 R/W 000 1× mode 001 2× mode 011 4× mode 100 8× mode 0x11F TXEN_SM_0 [7:6] FALL_COUNTERS Fall Counters. The number of counters to use to delay TX_PROTECT fall from TXENx falling edge. Must be set to 1 or 2. 0x2 R/W [5:4] RISE_COUNTERS Rise Counters. The number of counters to use to delay TX_PROTECT rise from TXENx rising edge. 0x0 R/W 3 RESERVED Reserved. 0x0 R

2 PROTECT_OUT_

PROTECT_OUTx Invert. 0x0 R/W 0 PROTECT_OUTx is high when output is valid. Suitable for enabling downstream components during transmission

1 PROTECT_OUTx is high when output is

invalid. Suitable for disabling downstream components when not transmitting [1:0] RESERVED Must write the default value for proper operation. 0x3 R/W 0x121 TXEN_RISE_COUNT_0 [7:0] RISE_COUNT_0 First counter used to delay TX_PROTECT rise from TXENx rising edge. Delays by 32 × RISE_COUNT_0 DAC clock cycles. 0xF R/W 0x122 TXEN_RISE_COUNT_1 [7:0] RISE_COUNT_1 Second counter used to delay TX_PROTECT rise from TXENx rising edge. Delays by 32 × RISE_COUNT_1 DAC clock cycles. 0x0 R/W 0x123 TXEN_FALL_ COUNT_0 [7:0] FALL_COUNT_0 First counter used to delay TX_PROTECT fall from TXENx falling edge. Delays by 32 × FALL_COUNT_0 DAC clock cycles. Must be set to a minimum of 0x12. 0xFF R/W 0x124 TXEN_FALL_ COUNT_1 [7:0] FALL_COUNT_1 Second counter used to delay TX_PROTECT fall from TXENx falling edge. Delays by 32 × FALL_COUNT_1 DAC clock cycles. 0xFF R/W 0x12D DEVICE_CONFIG_ REG_0 [7:0] DEVICE_CONFIG_0 Must be set to 0x8B for proper digital datapath configuration. 0x46 R/W 0x12F DIE_TEMP_CTRL0 [7:1] RESERVED Must write the default value for proper operation. 0x10 R/W 0 AUXADC_ENABLE Enables the AUX ADC Block. 0x0 R/W

0 AUX ADC disable

1 AUX ADC enable

Rev. C | Page 100 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x132 DIE_TEMP0 [7:0] DIE_TEMP[7:0] Aux ADC Readback Value. 0x0 R 0x133 DIE_TEMP1 [7:0] DIE_TEMP[15:8] Aux ADC Readback Value. 0x0 R 0x134 DIE_TEMP_UPDATE [7:1] RESERVED Reserved. 0x0 R

0 DIE_TEMP_

Die Temperature Update. On a rising edge, a new temperature code is generated. 0x0 R/W 0x135 DC_OFFSET_CTRL [7:1] RESERVED Reserved. 0x0 R 0 DC_OFFSET_ON DC Offset On. 0x0 R/W

1 Enables dc offset module

0x136 DAC_DC_OFFSET_1 PART0 [7:0] LSB_OFFSET[7:0] 8 LSBs of DC Offset. LSB_OFFSET is a 16-bit twos complement number that is added to incoming data. Applies to the DAC selected by DAC_PAGE (Register 0x008 [1:0]). 0x0 R/W 0x137 DAC_DC_OFFSET_ 1PART1 [7:0] LSB_OFFSET[15:8] 8 MSBs of DC Offset. LSB_OFFSET is a 16-bit twos complement number that is added to incoming data. Applies to the DAC selected by DAC_PAGE (Register 0x008 [1:0]). 0x0 R/W 0x13A DAC_DC_OFFSET_ 2PART [7:5] RESERVED Reserved. 0x0 R [4:0] SIXTEENTH_ OFFSET SIXTEENTH_OFFSET is a 5-bit twos complement number in 16ths of an LSB that is added to incoming I data. 0x0 R/W x x/16 LSB DC offset 0x13C DAC_DIG_GAIN0 [7:0] DAC_DIG_ GAIN[7:0] 8 LSBs of DAC Digital Gain. DAC_DIG_GAIN is the digital gain of the DAC selected by DAC_PAGE (Register 0x008 [1:0]). The digital gain is a multiplier from 0 to 4095/2048 in steps of 1/2048. 0xEA R/W 0x13D DAC_DIG_GAIN1 [7:4] RESERVED Reserved. 0x0 R [3:0] DAC_DIG_ GAIN[11:8]

4 MSBs of DAC Digital Gain 0xA R/W

0x140 GAIN_RAMP_UP_ STEP0 [7:0] GAIN_RAMP_UP_ STEP[7:0] 8 LSBs of Gain Ramp Up Step. GAIN_RAMP_UP_STEP controls the amplitude step size of the BSM’s ramping feature when the gain is being ramped to its assigned value. 0x4 R/W 0x0 Smallest ramp up step size 0xFFF Largest ramp up step size 0x141 GAIN_RAMP_UP_ STEP1 [7:4] RESERVED Reserved. 0x0 R [3:0] GAIN_RAMP_UP_ STEP[11:8] 4 MSBs of Gain Ramp Up Step. See Register 0x140 for description. 0x0 R/W 0x142 GAIN_RAMP_DOWN_ STEP0 [7:0] GAIN_RAMP_ DOWN_STEP[7:0] 8 LSBs of Gain Ramp Down Step. GAIN_RAMP_DOWN_STEP controls the amplitude step size of the BSM’s ramping feature when the gain is being ramped to zero. 0x9 R/W

0 Smallest ramp down step size

0xFFF Largest ramp down step size 0x143 GAIN_RAMP_ DOWN_STEP1 [7:4] RESERVED Reserved. 0x0 R [3:0] GAIN_RAMP_ DOWN_STEP[11:8] 4 MSBs of Gain Ramp Down Step. See Register 0x142 for description. 0x0 R/W 0x146 DEVICE_CONFIG_ REG_1 [7:0] DEVICE_CONFIG_1 Must be set to 0x01 for proper digital datapath configuration. 0x0 R/W 0x147 BSM_STAT [7:6] SOFTBLANKRB Blanking State. 0x0 R

00 Data is fully blanked

01 Ramping from data process to full blanking

10 Ramping from fully blanked to data process

11 Data is being processed

[5:0] RESERVED Reserved. 0x0 R

Rev. C | Page 101 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x14B PRBS 7 RESERVED Reserved. 0x0 R 6 PRBS_GOOD Good Data Indicator. 0x0 R

0 Incorrect sequence detected

1 Correct PRBS sequence detected

[5:3] RESERVED Reserved. 0x0 R

2 PRBS_MODE Polynomial Select 0x0 R/W

0 7- bit: x7 + x6 + 1 1 15-bit: x15 + x14 + 1 1 PRBS_RESET Reset Error Counters. 0x0 R/W

1 Reset counters

0 PRBS_EN Enable PRBS Checker. 0x0 R/W

0 Disable

1 Enable

0x14C PRBS_ERROR [7:0] PRBS_COUNT Error Count Value. 0x0 R 0x1B0 DACPLLT0 [7:0] DAC_PLL_PWR DAC PLL PD settings. This register must be written to 0x00 for optimal performance. 0xFA R/W 0x1B5 DACPLLT5 [7:4] RESERVED Must write the default value for proper operation. 0x8 R/W [3:0] VCO_VAR Varactor KVO Setting. See Table 73 for optimal settings based on the fVCO being used. 0x3 R/W 0x1B9 DACPLLT9 [7:0] DAC_PLL_CP1 DAC PLL Charge Pump settings. This register must be written to 0x24 for optimal performance. 0x34 R/W 0x1BB DACPLLTB [7:5] RESERVED Reserved. 0x0 R [4:3] VCO_BIAS_TCF Temperature Coefficient for VCO Bias. See Table 73 for optimal settings based on the fVCO being used. 0x1 R/W [2:0] VCO_BIAS_REF VCO Bias Control. See Table 73 for optimal settings based on the fVCO being used. 0x4 R/W 0x1BC DACPLLTC [7:0] DAC_PLL_VCO_ CTRL DAC PLL VCO control settings. This register must be written to 0x0D for optimal performance. 0x00 R/W 0x1BE DACPLLTE [7:0] DAC_PLL_VCO_ PWR DAC PLL VCO power control settings. This register must be written to 0x02 for optimal performance. 0x00 R/W 0x1BF DACPLLTF [7:0] DAC_PLL_VCOCAL DAC PLL VCO calibration settings. This register must be written to 0x8E for optimal performance. 0x8D R/W 0x1C0 DACPLLT10 [7:0] DAC_PLL_LOCK_ CNTR This register must be written to 0x2A for optimal performance. 0x2E R/W 0x1C1 DACPLLT11 [7:0] DAC_PLL_CP2 This register must be written to0x2A for optimal performance. 0x24 R/W 0x1C4 DACPLLT17 [7:0] DAC_PLL_VAR1 DAC PLL Varactor setting. Must be set to 0x7E for proper DAC PLL configuration. 0x33 R/W 0x1C5 DACPLLT18 [7:0] DAC_PLL_VAR2 DAC PLL Varactor setting. See Table 73 for optimal settings based on the fVCO being used. 0x08 R/W 0x200 MASTER_PD [7:1] RESERVED Reserved. 0x0 R

0 SPI_PD_MASTER Power Down the Entire JESD Receiver Analog

(All Eight Channels Plus Bias). 0x1 R/W 0x201 PHY_PD [7:0] SPI_PD_PHY SPI Override to Power Down the Individual PHYs. 0x0 R/W Set Bit x to power down the corresponding SERDINx± PHY

Rev. C | Page 102 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x203 GENERIC_PD [7:2] RESERVED Reserved. 0x0 R 1 SPI_SYNC1_PD Power down LVDS buffer for SYNCOUT0±. 0x0 R/W 0 SPI_SYNC2_PD Power down LVDS buffer for SYNCOUT1±. 0x0 R/W 0x206 CDR_RESET [7:1] RESERVED Reserved. 0x0 R 0 SPI_CDR_RESETN Resets the Digital Control Logic for All PHYs. 0x1 R/W

0 Hold CDR in reset

1 Enable CDR

0x230 CDR_OPERATING_ MODE_REG_0 [7:6] RESERVED Reserved. 0x0 R 5 ENHALFRATE Enables Half-Rate CDR Operation. Set to 1 when 5.75 Gbps ≤ lane rate ≤ 12.4 Gbps. 0x1 R/W [4:2] RESERVED Must write the default value for proper operation. 0x2 R/W 1 CDR_OVERSAMP Enables Oversampling of the Input Data. Set to 1 when 1.44 Gbps ≤ lane rate ≤ 3.1 Gbps. 0x0 R/W 0 RESERVED Reserved. 0x0 R 0x232 DEVICE_CONFIG_ REG_3 [7:0] DEVICE_CONFIG_3 Must be set to 0xFF for proper JESD interface configuration. 0x0 R/W 0x268 EQ_BIAS_REG [7:6] EQ_POWER_ MODE Control the Equalizer Power/Insertion Loss Capability. 0x1 R/W

00 Normal mode

01 Low power mode

[5:0] RESERVED Must write the default value for proper operation. 0x22 R/W 0x280 SERDESPLL_ ENABLE_CNTRL [7:3] RESERVED Reserved. 0x0 R 2 RECAL_SERDESPLL Recalibrate SERDES PLL. On a rising edge, recalibrate the SERDES PLL. 0x0 R/W 1 RESERVED Reserved. 0x0 R

0 ENABLE_

Enable the SERDES PLL. Setting this bit enables and calibrates the SERDES PLL. 0x0 R/W 0x281 PLL_STATUS [7:6] RESERVED Reserved. 0x0 R

5 SERDES_PLL_

OVERRANGE_H SERDES PLL High Overrange. This bit indicates that the SERDES PLL hit the lower edge of its operating band. Recalibrate. 0x0 R

4 SERDES_PLL_

OVERRANGE_L SERDES PLL Low Overrange. This bit indicates that the SERDES PLL hit the lower edge of its operating band. Recalibrate. 0x0 R

3 SERDES_PLL_CAL_

VALID_RB SERDES PLL Calibration Valid. This bit indicates that the SERDES PLL has been successfully calibrated. 0x0 R [2:1] RESERVED Reserved. 0x0 R

0 SERDES_PLL_

LOCK_RB SERDES PLL Lock. This bit is set high by the PLL when it has achieved lock. 0x0 R 0x284 LOOP_FILTER_1 [7:0] LOOP_FILTER_1 S ERDES PLL loop filter setting. This register must be written to 0x62 for optimal performance. 0x77 R/W 0x285 LOOP_FILTER_2 [7:0] LOOP_FILTER_2 SERDES PLL loop filter setting. This register must be written to 0xC9 for optimal performance. 0x87 R/W 0x286 LOOP_FILTER_3 [7:0] LOOP_FILTER_3 SERDES PLL loop filter setting. This register must be written to 0x0E for optimal performance. 0x08 R/W 0x287 SERDES_PLL_CP1 [7:0] SERDES_PLL_CP1 SERDES PLL charge pump setting. This register must be written to 0x12 for optimal performance. 0x3F R/W

Rev. C | Page 103 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x289 REF_CLK_DIVIDER_ LDO [7:3] RESERVED Reserved. 0x0 R

2 DEVICE_CONFIG_4 Must be set to 1 for proper SERDES PLL

configuration. 0x0 R/W [1:0] SERDES_PLL_DIV_ MODE SERDES PLL Reference Clock Division Factor. This field controls the division of the SERDES PLL reference clock before it is fed into the SERDES PLL Phase Frequency Detector (PFD). It must be set so fREF/DivFactor is between 35 MHz and 80 MHz. 0x0 R/W 00 Divide by 4 for 5.75 Gbps to 12.4 Gbps lane rate 01 Divide by 2 for 2.88 Gbps to 6.2 Gbps lane rate 10 Divide by 1 for 1.44 Gbps to 3.1 Gbps lane rate 0x28A VCO_LDO [7:0] SERDES_PLL_ VCO_LDO SERDES PLL VCO LDO setting. This register must be written to 0x7B for optimal performance. 0x2B R/W 0x28B SERDES_PLL_PD1 [7:0] SERDES_PLL_PD1 SERDES PLL PD setting. This register must be written to 0x00 for optimal performance. 0x7F R/W 0x290 SERDESPLL_VAR1 [7:0] SERDES_PLL_VAR1 SERDES PLL Varactor setting. This register must be written to 0x89 for optimal performance. 0x83 R/W 0x294 SERDES_PLL_CP2 [7:0] SERDES_PLL_CP2 SERDES PLL Charge Pump setting. This register must be set to 0x24 for optimal performance. 0xB0 R/W 0x296 SERDESPLL_VCO1 [7:0] SERDES_PLL_ VCO1 SERDES PLL VCO setting. This register must be set to 0x03 for optimal performance. 0x0C R/W 0x297 SERDESPLL_VCO2 [7:0] SERDES_PLL_ VCO2 SERDES PLL VCO setting. This register must be set to 0x0D for optimal performance. 0x00 R/W 0x299 SERDES_PLL_PD2 [7:0] SERDES_PLL_PD2 SERDES PLL PD setting. This register must be set to 0x02 for optimal performance. 0x00 R/W 0x29A SERDESPLL_VAR2 [7:0] SERDES_PLL_VAR2 SERDES PLL Varactor setting. This register must be set to 0x8E for optimal performance. 0xFE R/W 0x29C SERDES_PLL_CP3 [7:0] SERDES_PLL_CP3 SERDES PLL Charge Pump setting. Must be set to 0x2A for proper SERDES PLL configuration. 0x17 R/W 0x29F SERDESPLL_VAR3 [7:0] SERDES_PLL_VAR3 SERDES PLL Varactor setting. Must be set to 0x78 for proper SERDES PLL configuration. 0x33 R/W 0x2A0 SERDESPLL_VAR4 [7:0] SERDES_PLL_VAR4 SERDES PLL Varactor setting. This register must be set to 0x06 for optimal performance. 0x08 R/W 0x2A4 DEVICE_CONFIG_ REG_8 [7:0] DEVICE_CONFIG_8 Must be set to 0xFF for proper clock configuration. 0x4B R/W 0x2A5 SYNCOUTB_SWING [7:1] RESERVED Reserved. 0x0 R

0 SYNCOUTB_

SWING_MD SYNCOUTx± Swing Mode. Sets the output differential swing mode for the SYNCOUTx± pins. See Table 8 for details. 0x0 R/W

0 Normal Swing Mode

1 High Swing Mode

0x2A7 TERM_BLK1_ CTRLREG0 [7:1] RESERVED Reserved. 0x0 R 0 RCAL_TERMBLK1 Termination Calibration. The rising edge of this bit calibrates PHY0, PHY1, PHY6, and PHY7 terminations to 50 Ω. 0x0 R/W 0x2AA DEVICE_CONFIG_ REG_9 [7:0] DEVICE_CONFIG_ Must be set to 0xB7 for proper JESD interface termination configuration. 0xC3 R/W 0x2AB DEVICE_CONFIG_ REG_10 [7:0] DEVICE_CONFIG_ Must be set to 0x87 for proper JESD interface termination configuration. 0x93 R/W

Rev. C | Page 104 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x2AE TERM_BLK2_ CTRLREG0 [7:1] RESERVED Reserved. 0x0 R 0 RCAL_TERMBLK2 Terminal Calibration. The rising edge of this bit calibrates PHY2, PHY3, PHY4 and PHY5 terminations to 50 Ω . 0x0 R/W 0x2B1 DEVICE_CONFIG_ REG_11 [7:0] DEVICE_CONFIG_ Must be set to 0xB7 for proper JESD interface termination configuration. 0xC3 R/W 0x2B2 DEVICE_CONFIG_ REG_12 [7:0] DEVICE_CONFIG_ Must be set to 0x87 for proper JESD interface termination configuration. 0x93 R/W 0x300 GENERAL_JRX_ CTRL_0 7 RESERVED Reserved. 0x0 R 6 CHECKSUM_MODE Checksum Mode. This bit controls the locally generated JESD204B link parameter checksum method. The value is stored in the FCMP registers (Register 0x40E, Register 0x416, Register 0x41E, Register 0x426, Register 0x42E, Register 0x436, Register 0x43E, and Register 0x446). 0x0 R/W

0 Checksum is calculated by summing the

individual fields in the link configuration table as defined in Section 8.3, Table 20 of the JESD204B standard

1 Checksum is calculated by summing the regis-

ters containing the packed link configuration fields (Σ[0x400:0x40A] modulo 256). [5:4] RESERVED Reserved. 0x0 R 3 LINK_MODE Link Mode. This register selects either single- link or dual-link mode. 0x0 R/W

0 Single-link mode

1 Dual-link mode

2 LINK_PAGE Link Paging. Selects which link’s register map is used. This paging affects Registers 0x401 to 0x47E. 0x0 R/W

0 Use Link 0 register map

1 Use Link 1 register map

[1:0] LINK_EN Link Enable. These bits bring up the JESD204B receiver digital circuitry: Bit 0 for Link 0 and Bit 1 for Link 1. Enable the link only after the following has occurred: all JESD204B para- meters are set, the DAC PLL is enabled and locked (Register 0x084[1] = 1), and the JESD204B PHY is enabled (Register 0x200 = 0x00) and calibrated (Register 0x281[2] = 0). 0x0 R/W 0b00 Disable both JESD Link 1 and JESD Link 0 0b01 Disable JESD Link 1, enable JESD Link 0 0b10 Enable JESD Link 1, disable JESD Link 0 0b11 Enable both JESD Link 1 and JESD Link 0 0x301 GENERAL_JRX_CTRL_1 [7:3] RESERVED Reserved. 0x0 R [2:0] SUBCLASSV_ LOCAL JESD204B Subclass. 0x1 R/W

000 Subclass 0

001 Subclass 1

0x302 DYN_LINK_LATENCY_0 [7:5] RESERVED Reserved. 0x0 R [4:0] DYN_LINK_ LATENCY_0 Dynamic Link Latency: Link 0. Latency between the LMFCRx for Link 0 and the last arriving LMFC boundary in units of PCLK cycles. See the Deterministic Latency section. 0x0 R 0x303 DYN_LINK_LATENCY_1 [7:5] RESERVED Reserved. 0x0 R [4:0] DYN_LINK_ LATENCY_1 Dynamic Link Latency: Link 1. Latency between the LMFCRx for Link 1 and the last arriving LMFC boundary in units of PCLK cycles. See the Deterministic Latency section. 0x0 R

Rev. C | Page 105 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x304 LMFC_DELAY_0 [7:5] RESERVED Reserved. 0x0 R [4:0] LMFC_DELAY_0 LMFC Delay: Link 0 Delay from the LMFC to LMFCRx for Link 0. In units of frame clock cycles for subclass 1 and PCLK cycles for subclass 0. See the Deterministic Latency section. 0x0 R/W 0x305 LMFC_DELAY_1 [7:5] RESERVED Reserved. 0x0 R [4:0] LMFC_DELAY_1 LMFC Delay: Link 1. Delay from the LMFC to LMFCRx for Link 1. In units of frame clock cycles for subclass 1 and PCLK cycles for subclass 0. See the Deterministic Latency section. 0x0 R/W 0x306 LMFC_VAR_0 [7:5] RESERVED Reserved. 0x0 R [4:0] LMFC_VAR_0 Variable Delay Buffer: Link 0. Sets when data is read from a buffer to be consistent across links and power cycles. In units of PCLK cycles. See the Deterministic Latency section. This setting must not be more than 10. 0x6 R/W 0x307 LMFC_VAR_1 [7:5] RESERVED Reserved. 0x0 R [4:0] LMFC_VAR_1 Variable Delay Buffer: Link 1. Sets when data is read from a buffer to be consistent across links and power cycles. In units of PCLK cycles. See the Deterministic Latency section. This setting must not be more than 10. 0x6 R/W 0x308 XBAR_LN_0_1 [7:6] RESERVED Reserved. 0x0 R [5:3] LOGICAL_LANE1_ SRC Logical Lane 1 Source. Selects a physical lane to be mapped onto Logical Lane 1. 0x1 R/W x Data is from SERDINx [2:0] LOGICAL_LANE0_ SRC Logical Lane 0 Source. Selects a physical lane to be mapped onto Logical Lane 0. 0x0 R/W x Data is from SERDINx 0x309 XBAR_LN_2_3 [7:6] RESERVED Reserved. 0x0 R [5:3] LOGICAL_LANE3_ SRC Logical Lane 3 Source. Selects a physical lane to be mapped onto Logical Lane 3. 0x3 R/W x Data is from SERDINx [2:0] LOGICAL_LANE2_ SRC Logical Lane 2 source. Selects a physical lane to be mapped onto Logical Lane 2. 0x2 R/W x Data is from SERDINx 0x30A XBAR_LN_4_5 [7:6] RESERVED Reserved. 0x0 R [5:3] LOGICAL_LANE5_ SRC Logical Lane 5 Source. Selects a physical lane to be mapped onto Logical Lane 5. 0x5 R/W x Data is from SERDINx [2:0] LOGICAL_LANE4_ SRC Logical Lane 4 Source. Selects a physical lane to be mapped onto Logical Lane 4. 0x4 R/W x Data is from SERDINx 0x30B XBAR_LN_6_7 [7:6] RESERVED Reserved. 0x0 R [5:3] LOGICAL_LANE7_ SRC Logical Lane 7 Source. Selects a physical lane to be mapped onto Logical Lane 7. 0x7 R/W x Data is from SERDINx [2:0] LOGICAL_LANE6_ SRC Logical Lane 6 Source. Selects a physical lane to be mapped onto Logical Lane 6. 0x6 R/W x Data is from SERDINx 0x30C FIFO_STATUS_REG_0 [7:0] LANE_FIFO_FULL FIFO Full Flags for Each Logical Lane. A full FIFO indicates an error in the JESD204B configuration or with a system clock. 0x0 R If the FIFO for Lane x is full, Bit x in this register will be high.

Rev. C | Page 106 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x30D FIFO_STATUS_REG_1 [7:0] LANE_FIFO_EMPTY FIFO Empty Flags for Each Logical Lane. An empty FIFO indicates an error in the JESD204B configuration or with a system clock. 0x0 R If the FIFO for Logical Lane x is empty, Bit x in this register will be high. 0x312 SYNCB_GEN_1 [7:6] RESERVED Reserved. 0x0 R/W [5:4] SYNCB_ERR_DUR Duration of SYNCOUTx± Low for Error. The duration applies to both SYNCOUT0 and SYNCOUT1. A sync error is asserted at the end of a multiframe whenever one or more disparity, not in table or unexpected control character errors are encountered. 0 ½ PCLK cycle 1 1 PCLK cycle 2 2 PCLK cycles [3:0] RESERVED Reserved. 0x0 R/W 0x314 SERDES_SPI_REG [7:0] SERDES_SPI_ CONFIG SERDES SPI Configuration. Must be written to 0x01 as part of the Physical Layer setup step. 0x0 R/W 0x315 PHY_PRBS_TEST_EN [7:0] PHY_TEST_EN PHY Test Enable. Enables the PHY BER test. 0x0 R/W Set Bit x to enable the PHY test for Lane x. 0x316 PHY_PRBS_TEST_CTRL 7 RESERVED Reserved. 0x0 R [6:4] PHY_SRC_ERR_CNT PHY Error Count Source. Selects which PHY errors are being reported in Register 0x31A to Register 0x31C. 0x0 R/W x Report Lane x error count [3:2] PHY_PRBS_PAT_SEL PHY PRBS Pattern Select. Selects the PRBS pattern for PHY BER test. 0x0 R/W

00 PRBS7

01 PRBS15

10 PRBS31

1 PHY_TEST_START PHY PRBS Test Start. Starts and stops the PHY PRBS test. 0x0 R/W

0 Test stopped

1 Test in progress

0 PHY_TEST_RESET PHY PRBS Test Reset. Resets the PHY PRBS test state machine and error counters. 0x0 R/W

0 Enable PHY PRBS test state machine

1 Hold PHY PRBS test state machine in reset

0x317 PHY_PRBS_TEST_ THRESHOLD_LOBITS [7:0] PHY_PRBS_ THRESHOLD[7:0] 8 LSBs of PHY PRBS Error Threshold. 0x0 R/W 0x318 PHY_PRBS_TEST_ THRESHOLD_ MIDBITS [7:0] PHY_PRBS_ THRESHOLD[15:8] 8 ISBs of PHY PRBS Error Threshold. 0x0 R/W 0x319 PHY_PRBS_TEST_ THRESHOLD_HIBITS [7:0] PHY_PRBS_ THRESHOLD[23:16] 8 MSBs of PHY PRBS Error Threshold. 0x0 R/W 0x31A PHY_PRBS_TEST_ ERRCNT_LOBITS [7:0] PHY_PRBS_ERR_ CNT[7:0] 8 LSBs of PHY PRBS Error Count. Reported PHY BERT error count from lane selected using Register 0x316[6:4]. 0x0 R 0x31B PHY_PRBS_TEST_ ERRCNT_MIDBITS [7:0] PHY_PRBS_ERR_ CNT[15:8] 8 ISBs of PHY PRBS Error Count. 0x0 R 0x31C PHY_PRBS_TEST_ ERRCNT_HIBITS [7:0] PHY_PRBS_ERR_ CNT[23:16] 8 MSBs of PHY PRBS Error Count. 0x0 R 0x31D PHY_PRBS_TEST_ STATUS [7:0] PHY_PRBS_PASS PHY PRBS Test Pass/Fail. 0xFF R Bit x corresponds to PHY PRBS pass/fail for Physical Lane x. The bit is set to 1 while the error count for Physical Lane x is less than PHY_PRBS_THRESHOLD.

Rev. C | Page 107 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x32C SHORT_TPL_TEST_0 [7:6] RESERVED Reserved. 0x0 R [5:4] SHORT_TPL_SP_ SEL Short Transport Layer Sample Select. Selects which sample to check from the DAC selected via Bits[3:2]. 0x0 R/W x Sample x [3:2] SHORT_TPL_DAC_ SEL Short Transport Layer Test DAC Select. Selects which DAC to sample. 0x0 R/W

0 Sample from DAC0

2 Sample from DAC1

1 SHORT_TPL_TEST_

Short Transport Layer Test Reset. Resets the result of short transport layer test. 0x0 R/W

0 Not reset

1 Reset

0 SHORT_TPL_TEST_

Short Transport Layer Test Enable. See the Subclass 0 section for details on how to perform this test. 0x0 R/W 0x32D SHORT_TPL_TEST_1 [7:0] SHORT_TPL_REF_ SP_LSB Short Transport Layer Test Reference, Sample LSB. This is the lower eight bits of the expected DAC sample. It is used to compare with the received DAC sample at the output of the JESD204B receiver. 0x0 R/W 0x32E SHORT_TPL_TEST_2 [7:0] SHORT_TPL_REF_ SP_MSB Short Transport Layer Test Reference, Sample MSB. This is the upper eight bits of the expected DAC sample. It is used to compare with the received DAC sample at the output of the JESD204B receiver. 0x0 R/W 0x32F SHORT_TPL_TEST_3 [7:1] RESERVED Reserved. 0x0 R 0 SHORT_TPL_FAIL Short Transport Layer Test Fail. This bit shows whether the selected DAC sample matches the reference sample. If they match, it is a test pass, otherwise it is a test fail. 0x0 R

0 Test pass

1 Test fail

0x333 DEVICE_CONFIG_ REG_13 [7:0] DEVICE_CONFIG_ Must be set to 0x01 for proper JESD interface configuration.

00 R/W

0x334 JESD_BIT_INVERSE_ CTRL [7:0] JESD_BIT_INVERSE Logical Lane Invert. Set Bit x high to invert the JESD deserialized data on Logical Lane x. 0x0 R/W 0x400 DID_REG [7:0] DID_RD Device Identification Number. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x401 BID_REG [7:4] ADJCNT_RD Adjustment Resolution to DAC LMFC. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. 0x0 R [3:0] BID_RD Bank Identification: Extension to DID. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x402 LID0_REG 7 RESERVED Reserved. 0x0 R 6 ADJDIR_RD Direction to Adjust DAC LMFC. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. 0x0 R

5 PHADJ_RD Phase Adjustment Request to DAC Link

information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. 0x0 R [4:0] LID0_RD Lane Identification for Lane 0. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R

Rev. C | Page 108 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x403 SCR_L_REG 7 SCR_RD Transmit Scrambling Status. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R

0 Scrambling is disabled

1 Scrambling is enabled

[6:5] RESERVED Reserved. 0x0 R [4:0] L- 1_RD Number of Lanes per Converter Device. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R

0 One lane per converter

1 Two lanes per converter

3 Four lanes per converter

7 Eight lanes per converter (single link only)

0x404 F_REG [7:0] F- 1_RD Number of Octets per Frame. Settings of 1, 2 and 4 octets per frame are valid. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0 (One octet per frame) per lane 1 (Two octets per frame) per lane 3 (Four octets per frame) per lane 0x405 K_REG [7:5] RESERVED Reserved. 0x0 R [4:0] K- 1_RD Number of Frames per Multiframe. Settings of 16 or 32 are valid. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x0F 16 frames per multiframe 0x1F 32 frames per multiframe 0x406 M_REG [7:0] M- 1_RD Number of converters per device. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0 or 1. 0x0 R

0 One converter per device

1 Two converters per device

0x407 CS_N_REG [7:6] CS_RD Number of Control Bits per Sample. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. CS must be 0. 0x0 R 5 RESERVED Reserved. 0x0 R [4:0] N-1_RD Converter Resolution. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Converter resolution must be 16. 0x0 R 0x0F Converter resolution of 16 0x408 NP_REG [7:5] SUBCLASSV_RD Device Subclass Version. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R [4:0] NP-1_RD Total Number of Bits per Sample. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 16 bits per sample. 0x0 R 0x0F 16 bits per sample.

Rev. C | Page 109 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x409 S_REG [7:5] JESDV_RD JESD204 Version. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R

000 JESD204A

001 JESD204B

[4:0] S- 1_RD Number of Samples per Converter per Frame Cycle. Settings of one and two are valid. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R

0 One sample per converter per frame

1 Two samples per converter per frame

0x40A HD_CF_REG 7 HD_RD High Density Format. See Section 5.1.3 of the JESD294B standard. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R

0 Low density mode

1 High density mode: link information received

on Lane 0 as specified in Section 8.3 of JESD204B [6:5] RESERVED Reserved. 0x0 R [4:0] CF_RD Number of Control Words per Frame Clock Period per Link. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Bits[4:0] must be 0. 0x0 R 0x40B RES1_REG [7:0] RES1_RD Reserved Field 1. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x40C RES2_REG [7:0] RES2_RD Reserved Field 2. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x40D CHECKSUM_REG [7:0] FCHK0_RD Checksum for Link Lane 0. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x40E COMPSUM0_REG [7:0] FCMP0_RD Computed Checksum for Link Lane 0. The JESD204B receiver computes the checksum of the link information received on Lane 0 as specified in Section 8.3 of JESD204B. The computation method is set by the CHECKSUM_MODE bit (Address 0x300[6]) and must match the likewise calculated checksum in Register 0x40D. 0x0 R 0x412 LID1_REG [7:5] RESERVED Reserved. 0x0 R [4:0] LID1_RD Lane Identification for Link Lane 1.Link information received on Lane 0 as specified in section 8.3 of JESD204B. 0x0 R 0x415 CHECKSUM1_REG [7:0] FCHK1_RD Checksum for Link Lane 1. Link information received on Lane 0 as specified in Section 8.3 of JESD204B. 0x0 R 0x416 COMPSUM1_REG [7:0] FCMP1_RD Computed Checksum for Link Lane 1. See the description for Register 0x40E. 0x0 R 0x41A LID2_REG [7:5] RESERVED Reserved. 0x0 R [4:0] LID2_RD Lane Identification for Link Lane 2. 0x0 R 0x41D CHECKSUM2_REG [7:0] FCHK2_RD Checksum for Link Lane 2. 0x0 R 0x41E COMPSUM2_REG [7:0] FCMP2_RD Computed Checksum for Link Lane 2 (see the description for Register 0x40E). 0x0 R 0x422 LID3_REG [7:5] RESERVED Reserved. 0x0 R [4:0] LID3_RD Lane Identification for Link Lane 3. 0x0 R 0x425 CHECKSUM3_REG [7:0] FCHK3_RD Checksum for Link Lane 3. 0x0 R 0x426 COMPSUM3_REG [7:0] FCMP3_RD Computed Checksum for Link Lane 3 (see the description for Register 0x40E). 0x0 R

Rev. C | Page 110 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x42A LID4_REG [7:5] RESERVED Reserved. 0x0 R [4:0] LID4_RD Lane Identification for Link Lane 4. 0x0 R 0x42D CHECKSUM4_REG [7:0] FCHK4_RD Checksum for Link Lane 4. 0x0 R 0x42E COMPSUM4_REG [7:0] FCMP4_RD Computed Checksum for Link Lane 4 (see the description for Register 0x40E). 0x0 R 0x432 LID5_REG [7:5] RESERVED Reserved. 0x0 R [4:0] LID5_RD Lane Identification for Link Lane 5. 0x0 R 0x435 CHECKSUM5_REG [7:0] FCHK5_RD Checksum for Link Lane 5. 0x0 R 0x436 COMPSUM5_REG [7:0] FCMP5_RD Computed Checksum for Link Lane 5 (see the description for Register 0x40E). 0x0 R 0x43A LID6_REG [7:5] RESERVED Reserved. 0x0 R [4:0] LID6_RD Lane Identification for Link Lane 6. 0x0 R 0x43D CHECKSUM6_REG [7:0] FCHK6_RD Checksum for Link Lane 6. 0x0 R 0x43E COMPSUM6_REG [7:0] FCMP6_RD Computed Checksum for Link Lane 6 (see the description for Register 0x40E). 0x0 R 0x442 LID7_REG [7:5] RESERVED Reserved. 0x0 R [4:0] LID7_RD Lane Identification for Link Lane 7. 0x0 R 0x445 CHECKSUM7_REG [7:0] FCHK7_RD Checksum for Link Lane 7. 0x0 R 0x446 COMPSUM7_REG [7:0] FCMP7_RD Computed Checksum for Link Lane 7 (see the description for Register 0x40E). 0x0 R 0x450 ILS_DID [7:0] DID Device Identification Number. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be set to value read in Register 0x400. 0x0 R/W 0x451 ILS_BID [7:4] ADJCNT Adjustment Resolution to DAC LMFC Must be set to 0. 0x0 R/W [3:0] BID Bank Identification: Extension to DID Must be set to value read in Register 0x401[3:0]. 0x0 R/W 0x452 ILS_LID0 7 RESERVED Reserved. 0x0 R 6 ADJDIR Direction to Adjust DAC LMFC. Must be set to 0. 0x0 R/W 5 PHADJ Phase Adjustment Request to DAC. Must be set to 0. 0x0 R/W [4:0] LID0 Lane Identification for Link Lane 0. Must be set to the value read in Register 0x402[4:0]. 0x0 R/W 0x453 ILS_SCR_L 7 SCR Receiver Descrambling Enable. 0x1 R/W

0 Descrambling is disabled

1 Descrambling is enabled

[6:5] RESERVED Reserved. 0x0 R [4:0] L-1 Number of Lanes per Converter Device. See Table 34 and Table 35. 0x3 R/W 0x454 ILS_F [7:0] F-1 Number of Octets per Lane per Frame. Settings of 1, 2, and 4 (octets per lane) per frame are valid. See Table 34 and Table 35. 0x0 R/W 0 (One octet per lane) per frame 1 (Two octets per lane) per frame 3 (Four octets per lane) per frame 0x455 ILS_K [7:5] RESERVED Reserved. 0x0 R [4:0] K-1 Number of Frames per Multiframe. Settings of 16 or 32 are valid. Must be set to 32 when F = 1 (Register 0x476). 0x1F R/W 0x0F 16 frames per multiframe 0x1F 32 frames per multiframe

Rev. C | Page 111 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x456 ILS_M [7:0] M-1 Number of Converters per Device. See Table 34 and Table 35. 0x1 R/W

0 One converter per link

1 Two converters per link

0x457 ILS_CS_N [7:6] CS Number of Control Bits per Sample. Must be set to 0. Control bits are not supported. 0x0 R/W

0 Zero control bits per sample

5 RESERVED Reserved. 0x0 R [4:0] N-1 Converter Resolution. Must be set to 16 bits of resolution. 0xF R/W 0x0F Converter resolution of 16. 0x458 ILS_NP [7:5] SUBCLASSV Device Subclass Version. 0x1 R/W

0 Subclass 0

1 Subclass 1

[4:0] NP-1 Total Number of Bits per Sample. Must be set to 16 bits per sample. 0xF R/W 0xF 16 bits per sample. 0x459 ILS_S [7:5] JESDV JESD204 Version. 0x1 R/W [4:0] S-1 Number of Samples per Converter per Frame Cycle. Settings of one and two are valid. 0x0 R/W 0x45A ILS_HD_CF 7 HD High Density Format. If F = 1, HD must be set to 1. Otherwise, HD must be set to 0. See Section 5.1.3 of JESD204B standard. 0x1 R/W

1 High density mode

[6:5] RESERVED Reserved. 0x0 R [4:0] CF Number of Control Words per Frame Clock Period per Link. Must be set to 0. Control bits are not supported. 0x0 R/W 0x45B ILS_RES1 [7:0] RES1 Reserved Field 1. 0x0 R/W 0x45C ILS_RES2 [7:0] RES2 Reserved Field 2. 0x0 R/W 0x45D ILS_CHECKSUM [7:0] FCHK0 Checksum for Link Lane 0. Calculated checksum. Calculation depends on 0x300[6]. 0x45 R/W 0x46B ERRCNTRMON_RB [7:0] READERRORCNTR Read JESD204B Error Counter. After selecting the lane and error counter by writing to LANESEL and CNTRSEL (both in this same register), the selected error counter is read back here. 0x0 R 0x46B ERRCNTRMON 7 RESERVED Reserved. 0x0 R [6:4] LANESEL Link Lane select for JESD204B error counter. Selects the lane whose errors are read back in this register. 0x0 W x Selects Link Lane x [3:2] RESERVED Reserved. 0x0 R [1:0] CNTRSEL JESD204B Error Counter Select. Selects the type of error that are read back in this register. 0x0 W

00 BADDISCNTR: bad running disparity counter

01 NITCNTR: not in table error counter

10 UCCCNTR: Unexpected control character counter

0x46C LANEDESKEW [7:0] LANEDESKEW Lane Deskew. Setting Bit x deskews Link Lane x 0xF R/W 0x46D BADDISPARITY_RB [7:0] BADDIS Bad Disparity Character Error (BADDIS). Bit x is set when the bad disparity error count for Link Lane x reaches the threshold in Register 0x47C. 0x0 R

Rev. C | Page 112 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x46D BADDISPARITY 7 RST_IRQ_DIS BADDIS IRQ Reset. Reset BADDIS IRQ for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W

6 DISABLE_ERR_

CNTR_DIS BADDIS Error Counter Disable. Disable the BADDIS error counter for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W 5 RST_ERR_CNTR_DIS BADDIS Error Counter Reset. Reset BADDIS error counter for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W [4:3] RESERVED Reserved. 0x0 R [2:0] LANE_ADDR_DIS Link Lane Address for Functions Described in Bits[7:5]. 0x0 W 0x46E NIT_RB [7:0] NIT Not in table Character Error (NIT). Bit x is set when Link Lane x’s NIT error count reaches the threshold in Register 0x47C. 0x0 R 0x46E NIT_W 7 RST_IRQ_NIT IRQ Reset. Reset IRQ for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W CNTR_NIT Disable Error Counter. Disable the error counter for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W 5 RST_ERR_CNTR_NIT Reset Error Counter. Reset error counter for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W [4:3] RESERVED Reserved. 0x0 R [2:0] LANE_ADDR_NIT Link Lane Address for Functions Described in Bits[7:5]. 0x0 W 0x46F UNEXPECTED- CONTROL_RB [7:0] UCC Unexpected Control Character Error (UCC). Bit x is set when Link Lane x’s UCC error count reaches the threshold in Register 0x47C. 0x0 R 0x46F UNEXPECTED- CONTROL_W 7 RST_IRQ_UCC IRQ Reset. Reset IRQ for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W CNTR_UCC Disable Error Counter. Disable the error counter for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W

5 RST_ERR_CNTR_

Reset Error Counter. Reset error counter for lane selected via Bits[2:0] by writing 1 to this bit. 0x0 W [4:3] RESERVED Reserved. 0x0 R [2:0] LANE_ADDR_UCC Link Lane Address for Functions Described in Bits[7:5]. 0x0 W 0x470 CODEGRPSYNCFLG [7:0] CODEGRPSYNC C ode Group Sync Flag (from Each Instantiated Lane). Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[0]. A loss of CODEGRPSYNC triggers sync request assertion. See the SYNCOUTx± SYSREF±, and CLK± Signals section and the Deterministic Latency section. 0x0 R/W

0 Synchronization is lost

1 Synchronization is achieved

0x471 FRAMESYNCFLG [7:0] FRAMESYNC Frame Sync Flag (from Each Instantiated Lane). This register indicates the live status for each lane. Writing 1 to Bit 7 resets the IRQ. A loss of frame sync automatically initiates a synchronization sequence. 0x0 R/W 0x472 GOODCHKSUMFLG [7:0] GOODCHECKSUM Good Checksum Flag (from Each Instantiated Lane). Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[2]. 0x0 R/W

0 Last computed checksum is not correct

1 Last computed checksum is correct

Rev. C | Page 113 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x473 INITLANESYNCFLG [7:0] INITIALLANESYNC Initial Lane Sync Flag (from Each Instantiated Lane). Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[3]. Loss of synchronization is also reported on SYNCOUT1± or SYNCOUT0±. See the SYNCOUTx±, SYSREF±, and CLK± Signals section and the Deterministic Latency section. 0x0 R/W 0x476 CTRLREG1 [7:0] F Number of Octets per Frame. Settings of 1, 2, and 4 are valid. See Table 34 and Table 35. 0x1 R/W

1 One octet per frame

2 Two octets per frame

4 Four octets per frame

0x477 CTRLREG2 7 ILAS_MODE ILAS Test Mode. Defined in Section 5.3.3.8 of JESD204B specification. 0x0 R/W

1 JESD204B receiver is constantly receiving

0 Normal link operation

[6:4] RESERVED Reserved. 0x0 R

3 THRESHOLD_

MASK_EN Threshold Mask Enable. Set this bit if using SYNC_ASSERTION_MASK (Register 0x47B[7:5]). 0x0 R/W [2:0] RESERVED Reserved. 0x0 R 0x478 KVAL [7:0] KSYNC Number of K Multiframes During ILAS (Divided by Four). Sets the number of multiframes to send initial lane alignment sequence. Cannot be set to 0. 0x1 R/W x 4× multiframes during ILAS 0x47A IRQVECTOR_MASK 7 BADDIS_MASK Bad Disparity Mask. 0x0 W

1 If the bad disparity count reaches

ERRORTHRESH on any lane, IRQ is pulled low. 6 NIT_MASK Not in table Mask. 0x0 W

1 If the not in table character count reaches

ERRORTHRESH on any lane, IRQ is pulled low. 5 UCC_MASK Unexpected Control Character Mask. 0x0 W

1 If the unexpected control character count

reaches ERRORTHRESH on any lane, IRQ is pulled low. 4 RESERVED Reserved. 0x0 R

3 INITIALLANESYNC_

Initial Lane Sync Mask. 0x0 W

1 If initial lane sync (0x473) fails on any

lane, IRQ is pulled low.

2 BADCHECKSUM_

Bad Checksum Mask. 0x0 W

1 If there is a bad checksum (0x472) on any

lane, IRQ is pulled low.

1 FRAMESYNC_

1 If frame sync (0x471) fails on any lane, IRQ is

pulled low.

0 CODEGRPSYNC_

Code Group Sync Machine Mask. 0x0 W

1 If code group sync (0x470) fails on any

lane, IRQ is pulled low. 0x47A IRQVECTOR_FLAG 7 BADDIS_FLAG Bad Disparity Error Count. 0x0 R

1 Bad disparity character count reached

ERRORTHRESH (0x47C) on at least one lane. Read Register 0x46D to determine which lanes are in error.

6 NIT_FLAG Not in table Error Count 0x0 R

1 Not in table character count reached

ERRORTHRESH (0x47C) on at least one lane. Read Register 0x46E to determine which lanes are in error.

Rev. C | Page 114 of 117 Address Name Bit No. Bit Name Settings Description Reset Access

5 UCC_FLAG Unexpected Control Character Error Count 0x0 R

1 Unexpected control character count reached

ERRORTHRESH (0x47C) on at least one lane. Read Register 0x46F to determine which lanes are in error. 4 RESERVED Reserved. 0x0 R Initial Lane Sync Flag. 0x0 R 1 Initial lane sync failed on at least one lane. Read Register 0x473 to determine which lanes are in error Bad Checksum Flag. 0x0 R 1 Bad checksum on at least one lane. Read Register 0x472 to determine which lanes are in error. Frame Sync Flag. 0x0 R 1 Frame sync failed on at least one lane. Read Register 0x471 to determine which lanes are in error. Code Group Sync Flag. 0x0 R 1 Code group sync failed on at least one lane. Read Register 0x470 to determine which lanes are in error 0x47B SYNCASSERTIONMASK 7 BADDIS_S Bad Disparity Error on Sync. 0x0 R/W

1 Asserts a sync request on SYNCOUTx± when

the bad disparity character count reaches the threshold in Register 0x47C 6 NIT_S Not in table Error on Sync. 0x0 R/W the not in table character count reaches the threshold in Register 0x47C 5 UCC_S Unexpected Control Character Error on Sync. 0x0 R/W the unexpected control character count reaches the threshold in Register 0x47C 4 CMM Configuration Mismatch IRQ. If CMM_ENABLE is high, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. If CMM_ENABLE is low, this bit is non-functional. 0x0 R/W

1 Link Lane 0 configuration registers (Register

0x450 to Register 0x45D) do not match the JESD204B transmit settings (Register 0x400 to Register 0x40D) 3 CMM_ENABLE Configuration Mismatch IRQ Enable. 0x1 R/W

1 Enables IRQ generation if a configuration

0 Configuration mismatch IRQ disabled

[2:0] RESERVED Reserved. 0x0 R 0x47C ERRORTHRES [7:0] ETH Error Threshold. Bad disparity, not in table, and unexpected control character errors are counted and compared to the error threshold value. When the count reaches the threshold, either an IRQ is generated or the SYNCOUTx± signal is asserted per the mask register settings, or both. Function is performed in all lanes. 0xFF R/W 0x47D LANEENABLE [7:0] LANE_ENA Lane Enable. Setting Bit x enables Link Lane x. This register must be programmed before receiving the code group pattern for proper operation. 0xF R/W

Rev. C | Page 115 of 117 Address Name Bit No. Bit Name Settings Description Reset Access 0x47E RAMP_ENA [7:1] RESERVED Reserved. 0x0 R

0 ENA_RAMP_

Enable Ramp Checking at the Beginning of ILAS. 0x0 W

0 Disable ramp checking at beginning of ILAS;

ILAS data need not be a ramp

1 Enable ramp checking; ILAS data needs to be

a ramp starting at 00-01-02; otherwise, the ramp ILAS fails and the device does not start up 0x520 DIG_TEST0 [7:2] RESERVED Must write default value for proper operation. 0x7 R/W

1 DC_TEST_MODE DC Test Mode 0x0 R/W

0 RESERVED Reserved. 0x0 R/W 0x521 DC_TEST_VALUE0 [7:0] DC_TEST_ VALUE[7:0] DC Value LSB of DC Test Mode for DAC0 and DAC1. 0x0 R/W 0x522 DC_TEST_VALUE1 [7:0] DC_TEST_ VALUE[15:8] DC value MSB of DC Test Mode for DAC0 and DAC1. 0x0 R/W

Figure 91. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Figure 92. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] (Variable Lead Length)

0.60 MAX

0.20 REF

Rev. C | Page 117 of 117 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9135BCPZ −40°C to +85°C 88- Lead LFCSP_VQ CP-88-6 AD9135BCPZRL −40°C to +85°C 88-Lead LFCSP_VQ CP-88-6 AD9135BCPAZ −40°C to +85°C 88- Lead LFCSP_VQ (Variable Lead Length) CP-88-9 AD9135BCPAZRL −40°C to +85°C 88- Lead LFCSP_VQ (Variable Lead Length) CP-88-9 AD9136BCPZ −40°C to +85°C 88-Lead LFCSP_VQ CP-88-6 AD9136BCPZRL −40°C to +85°C 88- Lead LFCSP_VQ CP-88-6 AD9136BCPAZ −40°C to +85°C 88- Lead LFCSP_VQ (Variable Lead Length) CP-88-9 AD9136BCPAZRL −40°C to +85°C 88- Lead LFCSP_VQ (Variable Lead Length) CP-88-9 AD9136-EBZ DPG3 Evaluation Board AD9136-FMC-EBZ FMC Evaluation Board AD9135-EBZ DPG3 Evaluation Board AD9135-FMC-EBZ FMC Evaluation Board 1 Z = RoHS Compliant Part. ©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12578-0-5/17(C)