AD9125BCPZRL

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Dual, 16-Bit, 1000 MSPS, TxDAC+ Digital-to-Analog Converter AD9125 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

Flexible CMOS interface allows dual-word, word, or byte load Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, R L = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Gain and phase adjustment for sideband suppression Multichip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter Low power: 900 mW at 500 MSPS, full operating conditions 72-lead, exposed paddle LFCSP

APPLICATIONS

W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, L TE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point Cable modem termination systems GENERAL DESCRIPTION The AD9125 is a dual, 16-bit, high dynamic range TxDAC+® digital-to-analog converter (DAC) that provides a sample rate of

1000 MSPS, permitting a multicarrier generation up to the Nyquist

frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface allows programming/readback of many inter- nal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9125 comes in a 72-lead LFCSP . PRODUCT HIGHLIGHTS 1. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. 2. A proprietary DAC output switching technique enhances dynamic performance. 3. The current outputs are easily configured for various single-ended or differential circuit topologies. 4. The flexible CMOS digital interface allows the standard 32-wire bus to be reduced to a 16-wire bus. TYPICAL SIGNAL CHAIN NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. COMPLEX BASEBAND DC COMPLEX IF fIF RF LO – fIF DIGITAL BASEBAND PROCESSOR PA I DAC Q DAC2 ANTIALIASING FILTER AQM LO SIN COS 09016-001 Figure 1.

Rev. 0 | Page 2 of 56 TABLE OF CONTENTS

REVISION HISTORY

6/10—Revision 0: Initial Version

Figure 2. AD9125 Functional Block Diagram

Rev. 0 | Page 4 of 56 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 % FSR Gain Error (with Internal Reference) −3.6 ±2 +3.6 % FSR Full-Scale Output Current1 8.66 19.6 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES DVDD18 1.71 1.8 1.89 V IOVDD 1.71 1.8/3.3 3.47 V POWER CONSUMPTION 2× Mode, fDAC = 491.52 MSPS, IF = 10 MHz, PLL Off 834 mW 2× Mode, fDAC = 491.52 MSPS, IF = 10 MHz, PLL On 913 mW 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off 1114 1227 mW AVDD33 55 58 mA CVDD18 78 85 mA DVDD18 440 490 mA Power-Down Mode 1.5 2.7 mW Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V OPERATING RANGE −40 +25 +85 °C 1 Based on a 10 kΩ external resistor.

Rev. 0 | Page 5 of 56 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V , IOVDD = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit CMOS DATA INPUTS Input VIN Logic High 1.2 V Input VIN Logic Low 0.6 V Maximum Bus Speed 250 MHz SERIAL PORT OUTPUT LOGIC LEVELS Output VOUT Logic High IOVDD = 1.8 V 1.4 V IOVDD = 2.5 V 1.8 V IOVDD = 3.3 V 2.0 V Output VOUT Logic Low IOVDD = 1.8 V 0.4 IOVDD = 2.5 V 0.4 V IOVDD = 3.3 V 0.4 V SERIAL PORT INPUT LOGIC LEVELS Input VIN Logic High IOVDD = 1.8 V 1.2 V IOVDD = 2.5 V 1.6 V IOVDD = 3.3 V 2.4 V Input VIN Logic Low IOVDD = 1.8 V 0.6 V IOVDD = 2.5 V 0.8 V IOVDD = 3.3V 0.8 V DACCLK INPUT (DACCLKP , DACCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage Self biased input, ac couple 1.25 V Maximum Clock Rate 1000 MHz REFCLK INPUT (REFCLKP , REFCLKN) Differential Peak-to-Peak Voltage 100 500 2000 mV Common-Mode Voltage 1.25 V REFCLKx Frequency, PLL Mode 1 GHz ≤ fVCO ≤ 2.1 GHz 15.625 600 MHz REFCLKx Frequency, SYNC Mode See the Multichip Synchronization section for conditions 0 600 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 40 MHz Minimum Pulse Width High (tPWH) 12.5 ns Minimum Pulse Width Low (tPWOL) 12.5 ns Setup Time, SDI to SCLK (tDS) 1.9 ns Hold Time, SDI to SCLK (tDH) 0.2 ns Data Valid, SDO to SCLK (tDV) 2.3 ns Setup Time, CS to SCLK (tDCS) 1.4 ns LATENCY AND POWER-UP TIMING SPECIFICATIONS Table 3. Parameter Min Typ Max Unit LATENCY (DACCLK Cycles) 1× Interpolation (with or Without Modulation) 64 Cycles 2× Interpolation (with or Without Modulation) 135 Cycles 4× Interpolation (with or Without Modulation) 292 Cycles 8× Interpolation (with or Without Modulation) 608 Cycles Inverse Sinc 20 Cycles Fine Modulation 8 Cycles Power-Up Time 260 ms

TMIN to TMAX, AVDD33 = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 5. Interface Speeds

electrical and thermal connection to the board. Table 7. Thermal Resistance

1. EXPOSED PAD MUST BE CONNECTED TO AVSS.

Figure 3. Pin Configuration Table 8. Pin Function Descriptions 1 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 2 DACCLKP DAC Clock Input, Positive. 3 DACCLKN DAC Clock Input, Negative.

6 NC No Connect

7 IRQ (INT) Interrupt Request. Open Drain, Active Low Output. Connect external pull-up to IOVDD. 11 IOVDD Supply for Serial Port Pin, RESET Pin, and IRQ Pin. 1.8 V to 3.3 V can be applied to this pin. 12 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports.

Rev. 0 | Page 9 of 56 Pin No. Mnemonic Description 28 NC No Connect. 29 DVDD18 1.8 V Digital Supply. 30 DVSS Digital Common. 31 D15 Data Bit 15. 32 D14 Data Bit 14. 33 D13 Data Bit 13. 34 D12 Data Bit 12. 35 D11 Data Bit 11. 36 D10 Data Bit 10. 37 D9 Data Bit 9. 38 D8 Data Bit 8. 39 D7 Data Bit 7. 40 D6 Data Bit 6. 41 D5 Data Bit 5. 42 D4 Data Bit 4. 43 DVDD18 1.8 V Digital Supply. 44 DVSS Digital Supply Common. 45 D3 Data Bit 3. 46 D2 Data Bit 2. 47 D1 Data Bit 1. 48 D0 Data Bit 0. 49 DVDD18 1.8 V Digital Supply. 50 SDO Serial Port Data Output (CMOS levels with respect to IOVDD). 51 SDIO Serial Port Data Input/Output (CMOS levels with respect to IOVDD). 52 SCLK Serial Port Clock Input (CMOS levels with respect to IOVDD). 53 CS Serial Port Chip Select. Active Low (CMOS levels with respect to IOVDD). 54 RESET Reset. Active Low (CMOS levels with respect to IOVDD). 55 NC No Connect. 56 AVSS Analog Supply Common. 57 AVDD33 3.3 V Analog Supply. 58 IOUT2P Q DAC Positive Current Output. 59 IOUT2N Q DAC Negative Current Output. 60 AVDD33 3.3 V Analog Supply. 61 AVSS Analog Supply Common. 62 REFIO Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common. 63 FSADJ Full-Scale Current Output Adjust. Place a 10 kΩ resistor on the analog common. 64 AVSS Analog Common. 65 AVDD33 3.3 V Analog Supply. 66 IOUT1N I DAC Negative Current Output. 67 IOUT1P I DAC Positive Current Output. 68 AVDD33 3.3 V Analog Supply. 69 REFCLKN PLL Reference Clock Input, Negative. This pin has a secondary function as the SYNC input. 70 REFCLKP PLL Reference Clock Input, Positive. This pin has a secondary function as the SYNC input. 71 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 72 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. EPAD Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection to the PCB.

Figure 34. Four-Carrier W-CDMA ACLR Performance, IF ≈150 MHz Figure 35. One-Carrier W-CDMA ACLR Performance, IF ≈150 MHz

from zero scale to full scale. to full scale, associated with a 1 LSB change in digital input code. when all inputs are set to 1. when all inputs are set to 1 vs. when all inputs are set to 0. drift is reported in ppm per degree Celsius. are varied from minimum to maximum specified voltages. the start of the output transition. other parasitic coupling paths to the DAC output. for SNR is expressed in decibels. appear around fDAC (output data rate) can be greatly suppressed. measured power within a channel and that of its adjacent channel. image near the second IF can be rejected. Figure 36. Defining Data Rates

the ease of frequency placement. optimization in SSB transmitters). read/write access to all registers that configure the AD9125. pins for input/output (SDIO/SDO). Figure 37. Serial Port Interface Pins transfer cycle, which is Phase 2 of the communication cycle. instruction byte into the device. serial port timing to the initial state of the instruction cycle. instruction bits of the current I/O operation. when the frequency update bit (Register 0x36, Bit 0) is set. The instruction byte contains the information shown in Table 9. Table 9. Serial Port Instruction Byte the device based on the LSB_FIRST bit (Register 0x00, Bit 6). edge of SCLK. All data is driven out on the falling edge of SCLK. An active low input starts and gates a communication cycle. communication cycle, the CS pin should stay low. Logic 0, configuring the SDIO pin as unidirectional. output data and is set to a high impedance state.

Table 10. Device Configuration Register Map

Rev. 0 | Page 20 of 56 Register Name Addr (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default FTW 1 (LSB) 0x30 FTW[7:0] 0x00 FTW 2 0x31 FTW[15:8] 0x00 FTW 3 0x32 FTW[23:16] 0x00 FTW 4 (MSB) 0x33 FTW[31:24] 0x00 NCO Phase Offset LSB 0x34 NCO phase offset[7:0] 0x00 NCO Phase Offset MSB 0x35 NCO phase offset[15:8] 0x00 NCO FTW Update 0x36 Frame FTW ack Frame FTW request Update FTW ack Update FTW request 0x00 I Phase Adj LSB 0x38 I phase adjust[7:0] 0x00 I Phase Adj MSB 0x39 I phase adjust[9:8] 0x00 Q Phase Adj LSB 0x3A Q phase adjust[7:0] 0x00 Q Phase Adj MSB 0x3B Q phase adjust[9:8] 0x00 I DAC Offset LSB 0x3C I DAC offset[7:0] 0x00 I DAC Offset MSB 0x3D I DAC offset[15:8] 0x00 Q DAC Offset LSB 0x3E Q DAC offset[7:0] 0x00 Q DAC Offset MSB 0x3F Q DAC offset[15:8] 0x00 I DAC FS Adjust 0x40 I DAC FS adjust[7:0] 0xF9 I DAC Control 0x41 I DAC sleep I DAC FS adjust[9:8] 0x01 Aux DAC I Data 0x42 I aux DAC[7:0] 0x00 I Aux DAC Control 0x43 I Aux DAC sign I Aux DAC current direction I aux DAC sleep I aux DAC[9:8] 0x00 Q DAC FS Adjust 0x44 Q DAC FS adjust[7:0] 0xF9 Q DAC Control 0x45 Q DAC sleep Q DAC FS adjust[9:8] 0x01 Aux DAC Q Data 0x46 Q aux DAC[7:0] 0x00 Q Aux DAC Control 0x47 Q Aux DAC sign Q Aux DAC current direction Q aux DAC sleep Q aux DAC[9:8] 0x00 Die Temperature Range Control 0x48 FS current[2:0] Reference current[2:0] Capacitor value 0x02 Die Temperature LSB 0x49 Die temperature[7:0] N/A Die Temperature MSB 0x4A Die temperature[15:8] N/A SED Control 0x67 SED compare enable Sample error detected Auto- clear enable Compare fail Compare pass 0x00 Compare I0 LSBs 0x68 Compare Value I0[7:0] 0xB6 Compare I0 MSBs 0x69 Compare Value I0[15:8] 0x7A Compare Q0 LSBs 0x6A Compare Value Q0[7:0] 0x45 Compare Q0 MSBs 0x6B Compare Value Q0[15:8] 0xEA Compare I1 LSBs 0x6C Compare Value I1[7:0] 0x16 Compare I1 MSBs 0x6D Compare Value I1[15:8] 0x1A Compare Q1 LSBs 0x6E Compare Value Q1[7:0] 0xC6

Table 11. Device Configuration Register Descriptions 0 = SDIO operates as an input only. 1 = SDIO operates as a bidirectional input/output.

5 Reset 1 = device is held in reset when this bit is written high

and is held there until the bit is written low.

5 Power-down data

4 Power-down auxiliary

1 = input data is in binary format. 0 = I data sent to data receiver first. 1 = Q data sent to data receiver first. become the least significant bits. 00 = dual-word mode; 32-bit interface bus width. 01 = word mode; 16-bit interleaved interface bus width. 10 = byte mode; 8-bit interleaved interface bus width. the operation of the different interface modes.

3 Enable sync phase

Rev. 0 | Page 22 of 56 Register Name Address (Hex) Bits Name Description Default 1 Enable FIFO Warning 1 1 = enables interrupt for FIFO Warning 1. 0 0 Enable FIFO Warning 2 1 = enables interrupt for FIFO Warning 2. 0 Interrupt Enable 2 0x05 7 Set to 0 Set this bit to 0. 0 6 Set to 0 Set this bit to 0. 0 5 Set to 0 Set this bit to 0. 0

4 Enable AED comparison

1 = enables interrupt for AED comparison pass. 0

3 Enable AED comparison

1 = enables interrupt for AED comparison fail. 0

2 Enable SED comparison

1 = enables interrupt for SED comparison fail. 0 1 Set to 0 Set this bit to 0. 0 0 Set to 0 Set this bit to 0. 0 Event Flag 11 0x06 7 PLL lock lost 1 = indicates that the PLL, which had been previously locked, has unlocked from the reference signal. This is a latched signal.

6 PLL locked 1 = indicates that the PLL has locked to the reference

clock input.

5 Sync signal lost 1 = indicates that the sync logic, which had been

previously locked, has lost alignment. This is a latched signal.

4 Sync signal locked 1 = indicates that the sync logic did achieve sync

alignment. This is indicated when no phase changes were requested for at least a few full averaging cycles.

3 Sync phase locked 1 = indicates that the internal digital clock generation logic

is ready. This occurs when internal clocks are present and stable.

2 Soft FIFO sync 1 = indicates that a FIFO reset originating from a serial

port-based request has successfully completed. This is a latched signal.

1 FIFO Warning 1 1 = indicates that the difference between the FIFO read

and write pointers is 1.

0 FIFO Warning 2 1 = indicates that the difference between the FIFO read

and write pointers is 2. Event Flag 21 0x07 4 AED comparison pass 1 = indicates that the SED logic detected a valid input data pattern compared with the preprogrammed expected values. This is a latched signal.

3 AED comparison fail 1 = indicates that the SED logic detected an invalid

input data pattern compared with the preprogrammed expected values. This is a latched signal that auto- matically clears when eight valid I/Q data pairs are received.

2 SED comparison fail 1 = indicates that the SED logic detected an invalid

input data pattern compared with the preprogrammed expected values. This is a latched signal. Clock Receiver Control 0x08 7 DACCLK duty correction 1 = enables duty-cycle correction on the DACCLK input. 0 6 REFCLK duty correction 1 = enables duty-cycle correction on the REFCLK input. 0

5 DACCLK cross-correction 1 = enables differential crossing correction on the DACCLK

input.

4 REFCLK cross-correction 1 = enables differential crossing correction on the

REFCLK input.

Rev. 0 | Page 23 of 56 Register Name Address (Hex) Bits Name Description Default PLL Control 1 0x0A 7 PLL enable 1 = enables the PLL clock multiplier. REFCLK input is used as the PLL reference clock signal. 6 PLL manual enable Enables the manual selection of the VCO band. 1 1 = manual mode; the correct VCO band must be determined by the user. [5:0] Manual VCO band Selects the VCO band to be used. 0 PLL Control 2 0x0C [7:5] PLL loop bandwidth[2:0] Selects the PLL loop filter bandwidth. 110 000 = loop bandwidth is nominally 200 kHz 010 = loop bandwidth is nominally 450 kHz 100 = loop bandwidth is nominally 950 kHz 110 = loop bandwidth is nominally 2 MHz [4:0] PLL charge pump current[4:0] Sets the nominal PLL charge-pump current. 10001 00000 = lowest current setting. 11111 = highest current setting. PLL Control 3 0x0D [7:6] N2[1:0] PLL control clock divider. These bits determine the ratio of the DACCLK rate to the PLL controller clock rate. f PC_CLK must always be less than 80 MHz. 00 = fDACCLK/fPC_CLK = 2. 01 = fDACCLK/fPC_CLK = 4. 10 = fDACCLK/fPC_CLK = 8. 11 = fDACCLK/fPC_CLK = 16. 4 PLL cross control enable Enables PLL cross-point controller. 1 [3:2] N0[1:0] PLL VCO divider. These bits determine the ratio of the VCO output to the DACCLK frequencies. 00 = fVCO/fDACCLK = 1. 01 = fVCO/fDACCLK = 2. 10 = fVCO/fDACCLK = 4. 11 = fVCO/fDACCLK = 4. [1:0] N1[1:0] PLL loop divider. These bits determine the ratio of the DACCLK to the REFCLK frequencies. 00 = fDACCLK/fREFCLK = 2. 01 = fDACCLK/fREFCLK = 4. 10 = fDACCLK/fREFCLK = 8. 11 = fDACCLK/fREFCLK = 16. PLL Status 1 0x0E 7 PLL lock The PLL generated clock is tracking the REFCLK input signal. R [3:0] VCO control voltage[3:0] VCO control voltage readback (see Table 25). R PLL Status 2 0x0F [5:0] VCO band readback[5:0] Indicates the VCO band currently selected. R Sync Control 1 0x10 7 Sync enable 1 = enables the synchronization logic. 0 6 Data/FIFO rate toggle 0 = operates the synchronization at the FIFO reset rate. 1 1 = operates the synchronization at the data rate. 3 Rising edge sync 0 = sync is initiated on the falling edge of the sync input. 1 1 = sync is initiated on the rising edge of the sync input. [2:0] Sync averaging[2:0] Sets the number of input samples that are averaged for determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32.

Rev. 0 | Page 24 of 56 Register Name Address (Hex) Bits Name Description Default 110 = 64. 111 = 128. Sync Control 2 0x11 5:0 Sync phase request[5:0] This sets the requested clock phase offset after sync. The offset unit is in DACCLK cycles. This enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. 111111 = 63 DACCLK cycles. Sync Status 1 0x12 7 Sync lost 1 = indicates that synchronization had been attained but was subsequently lost. R 6 Sync locked 1 = indicates that synchronization has been attained. R Sync Status 2 0x13 [7:0] Sync phase readback[7:0] Indicates the averaged sync phase offset (6.2 format). If the value differs from the requested sync phase value, this indicates sync timing errors. R 00000000 = 0.0. 00000001 = 0.25. 11111110 = 63.50. 11111111 = 63.75. FIFO Control 0x17 [2:0] FIFO phase offset[2:0] FIFO write pointer phase offset following FIFO reset. This is the difference between the read pointer and the write pointer values upon FIFO reset. The optimal value is nominally 4. 000 = 0. 001 = 1. 111 = 7. FIFO Status 1 0x18 7 FIFO Warning 1 FIFO read and write pointers within ±1. 0 6 FIFO Warning 2 FIFO read and write pointers within ±2. 0

2 FIFO soft align

FIFO read and write pointers are aligned after a serial port initiated FIFO reset.

1 FIFO soft align request Request FIFO read and write pointers alignment via the

serial port.

0 FIFO reset aligned FIFO read and write pointers aligned after a hardware

reset. FIFO Status 2 0x19 [7:0] FIFO level[7:0] Thermometer encoded measure of the FIFO level. 0 Datapath Control 0x1B 7 Bypass premod 1 = bypasses fS/2 premodulator. 1 6 Bypass sinc−1 1 = bypasses inverse sinc filter. 1 5 Bypass NCO 1 = bypasses NCO. 1 3 NCO gain 0 = default. No gain scaling is applied to the NCO input to the internal digital modulator. 1 = gain scaling of 0.5 is applied to the NCO input to the internal digital modulator. This can eliminate saturation of the modulator output for some combinations of data inputs and NCO signals.

2 Bypass phase compen-

1 = bypasses phase compensation and dc offset. 1

Rev. 0 | Page 25 of 56 Register Name Address (Hex) Bits Name Description Default 1 Select sideband 0 = the modulator outputs high-side image. 0 1 = the modulator outputs low-side image. The image is spectrally inverted compared with the input data.

0 Send I data to Q data 1 = ignores Q data from the interface and disables the

clocks to the Q datapath. Sends I data to both the I and Q DACs. HB1 Control 0x1C [2:1] HB1[1:0] 00 = input signal is not modulated; filter pass band is from −0.4 to +0.4 of f IN1. 01 = input signal is not modulated; filter pass band is from 0.1 to 0.9 of f IN1. 10 = input signal is modulated by fIN1; filter pass band is from 0.6 to 1.4 of fIN1. 11 = input signal is modulated by fIN1; filter pass band is from 1.1 to 1.9 of fIN1. 0 Bypass HB1 1 = bypasses first-stage interpolation filter. 0 HB2 Control 0x1D [6:1] HB2[5:0] Modulation mode for I Side Half-Band Filter 2. 0 000000 = input signal is not modulated; filter pass band is from −0.25 to +0.25 of f IN2. 001001 = input signal is not modulated; filter pass band is from 0.0 to 0.5 of f IN2. 010010 = input signal is not modulated; filter pass band is from 0.25 to 0.75 of f IN2. 011011 = input signal is not modulated; filter pass band is from 0.5 to 1.0 of f IN2. 100100 = input signal is modulated by fIN2; filter pass band is from 0.75 to 1.25 of fIN2. 101101 = input signal is modulated by fIN2; filter pass band is from 1.0 to 1.5 of fIN2. 110110 = input signal is modulated by fIN2; filter pass band is from 1.25 to 1.75 of fIN2. 111111 = input signal is modulated by fIN2; filter pass band is from 1.5 to 2.0 of fIN2. 0 Bypass HB2 1 = bypasses second stage interpolation filter. 0 HB3 Control 0x1E [6:1] HB3[5:0] Modulation mode for I Side Half-Band Filter 3. 0 000000 = input signal is not modulated; filter pass band is from −0.2 to +0.2 of f IN3. 001001 = input signal is not modulated; filter pass band is from 0.05 to 0.45 of fIN3. 010010 = input signal is not modulated; filter pass band is from 0.3 to 0.7 of fIN3. 011011 = input signal is not modulated; filter pass band is from 0.55 to 0.95 of fIN3. 100100 = input signal is modulated by fIN3; filter pass band is from 0.8 to 1.2 of fIN3. 101101 = input signal is modulated by fIN3; filter pass band is from 1.05 to 1.45 of fIN3. 110110 = input signal is modulated by fIN3; filter pass band is from 1.3 to 1.7 of fIN3. 111111 = input signal is modulated by fIN3; filter pass band is from 1.55 to 1.95 of fIN3. 0 Bypass HB3 1 = bypasses third-stage interpolation filter. 0 Chip ID 0x1F [7:0] Chip ID[7:0] This register identifies the device as an AD9125. 8

Rev. 0 | Page 26 of 56 Register Name Address (Hex) Bits Name Description Default FTW 1 (LSB) 0x30 [7:0] FTW[7:0] FTW[31:0] is the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Bit 0 of Register 0x36 transitions from 0 to 1. FTW 2 0x31 [7:0] FTW[15:8] See Register 0x30. 0 FTW 3 0x32 [7:0] FTW[23:16] See Register 0x30. 0 FTW 4 (MSB) 0x33 [7:0] FTW[31:24] See Register 0x30. 0 NCO Phase Offset LSB 0x34 [7:0] NCO phase offset[7:0] NCO phase offset[15:0] sets the phase of the complex carrier signal when the NCO is reset. The phase offset spans between 0° and 360°. Each bit represents an offset of 0.0055°. The value is in twos complement format. NCO Phase Offset MSB 0x35 [7:0] NCO phase offset[15:8] See Register 0x34. 0 NCO FTW Update 0x36 5 FRAME FTW acknowledge 1 = indicates that the NCO has been reset due to an extended FRAME pulse signal.

4 FRAME FTW request 0 → 1 = the NCO is reset on the first extended FRAME

pulse after this bit transitions from 0 to 1.

1 Update FTW

1 = indicates that the FTW has been updated. 0 0 Update FTW request 0 → 1 = the FTW is updated on 0-to-1 transition of this bit. 0 I Phase Adj LSB 0x38 [7:0] I phase adjust[7:0] I phase adjust[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. I Phase Adj MSB 0x39 [1:0] I phase adjust[9:8] Register 0x38. 0 Q Phase Adj LSB 0x3A [7:0] Q phase adjust[7:0] Q phase adjust[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. Q Phase Adj MSB 0x3B [1:0] Q phase adjust[9:8] See Register 0x3A. 0 I DAC Offset LSB 0x3C [7:0] I DAC offset[7:0] I DAC offset[15:0] is a value added directly to the samples written to the I DAC. I DAC Offset MSB 0x3D [7:0] I DAC offset[15:8] See Register 0x3C. 0 Q DAC Offset LSB 0x3E [7:0] Q DAC offset[7:0] Q DAC offset[15:0] is a value added directly to the samples written to the Q DAC. Q DAC Offset MSB 0x3F [7:0] Q DAC offset[15:8] See Register 0x3E. 0 I DAC FS Adjust 0x40 [7:0] I DAC FS adjust[7:0] I DAC FS adjust[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. 0x200 = 20.14 mA. 0x3FF = 31.66 mA. I DAC Control 0x41 7 I DAC sleep 1 = puts the I-channel DAC into sleep mode (fast wake- up mode). [1:0] I DAC FS adjust[9:8] See Register 0x40. 1 Aux DAC I Data 0x42 [7:0] I aux DAC[7:0] I aux DAC[9:0] sets the magnitude of the auxiliary DAC current. The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. 0x3FF = 2.046 mA.

Rev. 0 | Page 27 of 56 Register Name Address (Hex) Bits Name Description Default I Aux DAC Control 0x43 7 I aux DAC sign 0 = the auxiliary DAC I sign is positive, and the current is directed to the IOUT1P pin (Pin 67). 1 = the auxiliary DAC I sign is negative, and the current is directed to the IOUT1N pin (Pin 66).

6 I aux DAC current

0 = the auxiliary DAC I sources current. 0 1 = the auxiliary DAC I sinks current. 5 I aux DAC sleep I channel auxiliary DAC sleep. 0 [1:0] I Aux DAC[9:8] See Register 0x42. 0 Q DAC FS Adjust 0x44 [7:0] Q DAC FS adjust[7:0] Q DAC FS adjust[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. 0x200 = 20.14 mA. 0x3FF = 31.66 mA. Q DAC Control 0x45 7 Q DAC sleep 1 = puts the Q-channel DAC into sleep mode (fast wake- up mode). [1:0] Q DAC FS adjust[9:8] See Register 0x44. 1 Aux DAC Q Data 0x46 [7:0] Q aux DAC[7:0] Q aux DAC[9:0] sets the magnitude of the aux DAC current. The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. 0x3FF = 2.046 mA. Q Aux DAC Control 0x47 7 Q aux DAC sign 0 = the auxiliary DAC Q sign is positive, and the current is directed to the IOUT2P pin (Pin 58). 1 = the auxiliary DAC Q sign is negative, and the current is directed to the IOUT2N pin (Pin 59).

6 Q aux DAC current

0 = the auxiliary DAC Q sources current. 0 1 = the auxiliary DAC Q sinks current.

5 Q aux DAC sleep Q-channel auxiliary DAC sleep 0

[1:0] Q aux DAC[9:8] See Register 0x46. 0 Die Temp Range Control 0x48 [6:4] FS current[2:0] Auxiliary ADC full-scale current. 0 000 = lowest current. 111 = highest current. [3:1] Reference current[2:0] Auxiliary ADC reference current. 1 000 = lowest current. 111 = highest current. 0 Capacitor value Auxiliary ADC internal capacitor value. 0 0 = 5 pF. 1 = 10 pF. Die Temp LSB 0x49 [7:0] Die temp[7:0] Die Temp[15:0] indicates the approximate die temperature. R 0xADCC = −39.9°C. 0xC422 = 25.1°C. 0xD8A8 = 84.8°C (see the Temperature Sensor section for details). Die Temp MSB 0x4A [7:0] Die temp[15:8] See Register 0x49. R

Rev. 0 | Page 28 of 56 Register Name Address (Hex) Bits Name Description Default SED Control 0x67 7 SED compare enable 1 = enables the SED circuitry. None of the flags in this register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled. 5 Sample error detected 1 = indicates an error is detected. The bit remains set until cleared. Any write to this register clears this bit to 0. 3 Autoclear enable 1 = enables autoclear mode. This activates Bit 1 and Bit 0 of this register and causes Register 0x70 through Register 0x73 to be autocleared whenever eight consecutive error-free sample data sets are received. 1 Compare fail 1 = indicates an error has been detected. This bit remains high until it is autocleared by the reception of eight consecutive error-free comparisons or until it is cleared by writing to this register. 0 Compare pass 1 = indicates that the last sample comparison was error free. 0 Compare I0 LSBs 0x68 [7:0] Compare Value I0[7:0] Compare Value I0[15:0] is the word that is compared with the I0 input sample captured at the input interface. Compare I0 MSBs 0x69 [7:0] Compare Value I0[15:8] See Register 0x68. 7A Compare Q0 LSBs 0x6A [7:0] Compare Value Q0[7:0] Compare Value Q0[15:0] is the word that is compared with the Q0 input sample captured at the input interface. Compare Q0 MSBs 0x6B [7:0] Compare Value Q0[15:8] See Register 0x6A EA Compare I1 LSBs 0x6C [7:0] Compare Value I1[7:0] Compare Value I1[15:0] is the word that is compared with the I1 input sample captured at the input interface. Compare I1 MSBs 0x6D [7:0] Compare Value I1[15:8] See Register 0x6C. 1A Compare Q1 LSBs 0x6E [7:0] Compare Value Q1[7:0] Compare Value Q1[15:0] is the word that is compared with the Q1 input sample captured at the input interface. Compare Q1 MSBs 0x6F [7:0] Compare Value Q1[15:8] See Register 0x6E. AA SED I LSBs 0x70 [7:0] Errors Detected I_BITS[7:0] Errors detected I_BITS[15:0] indicates which bits were received in error. SED I MSBs 0x71 [7:0] Errors detected I_BITS[15:8] See Register 0x70. 0 SED Q LSBs 0x72 [7:0] Errors detected Q_BITS[7:0] Errors detected Q_BITS[15:0] indicates which bits were received in error. SED Q MSBs 0x73 [7:0] Errors detected Q_BITS[15:8] See Register 0x72. 0 Die Revision 0x7F [5:2] Revision[3:0] Corresponds to device die revision. 3 1 All bit event flags are cleared by writing the respective bit high.

Figure 45. The sampling point of the data bus occurs on the Figure 45. Timing Diagram for Input Data Ports Table 13. Data Port Setup and Hold Times Figure 46. Timing Diagram for Frame input Table 14. FRAME Setup and Hold Times Validation section for details. timing budget of the interface. updated every time data is read into the datapath from the FIFO. unreliable data transfer through the FIFO and must be avoided. read from the FIFO, which keeps the data level in the FIFO constant. the write pointer and read pointer values.

32 BITS

32 BITS ÷ INTDCI DACCLK

Figure 47. Block Diagram of Datapath Through FIFO

block, and an inverse sinc filter. Figure 50. Block Diagram of Digital Datapath be used when the input data stream is represented as complex data. filter modes (see the Premodulation section for more details). bandwidths and operating modes.

• Bandwidth of HB1 = 0.8 × f IN1
• Bandwidth of HB2 = 0.5 × fIN2
• Bandwidth of HB3 = 0.4 × fIN3 The usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than +85 dB. As is discussed in the Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. The half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. The HB1 filter has four modes of operation, and the HB2 and HB3 filters each have eight modes of operation. Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 51. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors: the filter center frequency and whether the input signal is modulated by the filter. –20 –40 –60 –80 –100 GAIN (dB) NORMALIZED FREQUENCY (× fIN1) MODE 0 MODE 1 MODE 3MODE 2 09016-021

Figure 51. HB1 Filter Modes complex. Table 16 summarizes the HB1 modes. Table 16. HB1 Filter Mode Summary

0 DC None Real or complex

Table 18 summarizes the HB2 and HB3 modes. Table 18. HB2 and HB3 Filter Mode Summary Figure 55. Pass-Band Detail of HB2 Table 19. HB2 Pass-Band Flatness and Stop-Band Rejection Figure 56. Pass-Band Detail of HB3 Table 20. HB3 Pass-Band Flatness and Stop-Band Rejection

Figure 59. Signal Bandwidth vs. Center Frequency of the Output Signal, Table 21. Recommended Interpolation Filter Modes (Register 0x1C through Register 0x1E) input signal in the filter pass band. 2 This configuration was used in the 8× interpolation without NCO example. In addition, see the 8× Interpolation Without NCO section.

• fDATA = 100 MSPS
• 8× interpolation
• fBW = 75 MHz
• fCENTER = 100 MHz In this case, the ratio of fOUT/fDATA = 100/100 = 1.0. From Figure 59, the bandwidth supported at fDATA is 0.8, which verifies that the AD9125 supports the bandwidth required in this configuration. The signal center frequency is fDATA, and assuming the input signal is at baseband, the frequency shift required is also fDATA. Using the settings detailed in the third row of the IF column from Table 21 (these settings use the configuration in the 8× interpolation without NCO example) selects filter modes that result in a center frequency of fDATA and a frequency translation of fDATA. The selected modes for the three half-band filters are HB1, Mode 2; HB2, Mode 2; and HB3, Mode 1. Figure 60 shows how the signal propagates through the interpolation filters. Because 2 × fIN1 = fIN2 and 2 × fIN2 = fIN3, the signal appears frequency scaled by ½ into each consecutive stage. The output signal band spans 0.15 to 0.35 of fIN3 (400 MHz). Therefore, the output frequency supported is 60 MHz to 140 MHz, which covers the 75 MHz bandwidth centered at 100 MHz, as desired. 4× Interpolation with NCO Given the following conditions, the desired 140 MHz of bandwidth is 56% of f DATA:
• fDATA = 250 MSPS
• 4× interpolation
• fBW = 140 MHz
• fCENTER = 175 MHz As shown in Figure 58, the value at 0.7 × fDATA is 0.6. This is supports a bandwidth of 60% of fDATA, which exceeds the required 56%. The signal center frequency is 0.7 × fDATA, and assuming the input signal is at baseband, the frequency shift required is also 0.7 × fDATA. Using the settings detailed in the second row in the IF column in the 4× interpolation section in Table 21 selects the filter modes that give a center frequency of fDATA/2 and no frequency translation. The selected modes for the three half- band filters are HB1, Mode 1; HB2, Mode 1; and HB3, bypassed. Because Mode 1 of HB1 was selected, the premodulation block should be enabled. This provides fDATA/2 modulation, which centers the baseband input data at the center frequency of HB1. The digital modulator can be used to provide the final frequency translation of 0.2 × f DATA to place the output signal at 0.7 × fDATA, as desired. The formula for calculating the FTW of the NCO is 322× = NCO CARRIER f fFTW where: fCARRIER = 0.2 × fDATA. fNCO = 2 × fDATA. Therefore, FTW = 232/10. 1 2 3 0 –0.5 0.5 HB1 0.1 0.4 0.6 1.5 2.0 × fIN11.00 –0.5 0.5 HB3 0.2–0.2 0.3 0.7 0.15 0.35 1.5 2.0 × fIN31.00 753 –0.5 0.5 HB2 0.25 0.75 0.3 0.7 1.25 1.75 1.5 2.0 × fIN21.00 753 640 1 09016-030

Figure 60. Signal Propagation for 8× Interpolation (fDATA Modulation)

DAC) in any mode is 1000 MHz. twice the real signal bandwidth. and 4× interpolation is best supported enabling HB1 and HB2. supported by using HB2 and HB3. spectrum of the incoming data by the frequency offset selected. Table 22. Modulation Mixing Sequences result in cross coupling samples between the I and Q channels. The I and Q channels only operate independently in fS/2 mode. Table 23. Summary of Data Rates and Bandwidths vs. Interpolation Modes

recommended PLL settings for these parameters. Table 24. PLL Settings 1.0 GHz to 2.1 GHz, covered in 63 overlapping frequency bands. The device has an automatic VCO band select feature on chip. Figure 65. PLL Lock Range over Temperature for a Typical Device Put the device in manual band select mode.

1. Sweep the VCO band over a range of bands that result in
2. For each band, verify that the PLL is locked and read the

manual VCO band (Register 0x0A, Bits[5:0]) value. the PLL VCO control voltage (Register 0x0E, Bits[3:0]) value. Table 25. VCO Control Voltage Range Indications

1111 Move to a higher VCO band

1101 VCO is operating in the higher end of

1001 VCO is operating within an optimal

0101 VCO is operating in the lower end of

0001 Move to a lower VCO band

more DACs to be synchronized with a system-level reference clock. from the FIFO, and a particular clock edge of the system clock. synchronized to each other or to a system clock. relative to the DACCLK or REFCLK input. resulting in keep-out widows repeating at the input data rate. modes and for querying the status of the synchronization logic. with low skew to all of the devices that need to be synchronized. directly as a timing mismatch at the DAC outputs. configuration is shown in Figure 81. Figure 81. Typical Circuit Diagram for Synchronizing Devices procedure must be carried out on each individual device.

1. Configure the device for data rate mode and periodic

time required to write two complete input data-words. the input signals is shown in Figure 82. This example shows a REFCLK frequency equal to the data rate. 200 MHz, and fSYNC_I = 100 MHz is a viable solution.

the Sync Status Bits and Timing Optimization sections. latched and remains set until cleared by overwriting the register. is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾). data rate synchronization mode. Table 27. Synchronization Setup and Hold Times

Rev. 0 | Page 54 of 56 EXAMPLE START-UP ROUTINE There are certain sequences that should be followed to ensure reliable startup of the AD9125. The example start-up routine assumes the following device configuration:

• fDATA = 122.88 MSPS
• Interpolation = 4×, using HB1 = 10 and HB2 = 010010
• Input data = baseband data
• fOUT = 140 MHz
• fREFCLK = 122.88 MHz
• PLL = enabled
• Fine NCO = enabled
• Inverse SINC filter = enabled
• Synchronization = enabled The following PLL settings can be derived from the device configuration:
• fDACCLK = fDATA × Interpolation = 491.52 MHz
• fVCO = 4 × fDACCLK = 1966.08 MHz (1 GHz < fVCO < 2.1 GHz)
• N1 = fDACCLK/fREFCLK = 4
• N2 = fVCO/fDACCLK = 4 The following NCO settings can be derived from the device configuration:
• fNCO = 2 × fDATA
• fCARRIER = fOUT − fMODHB1 = 140 − 122.88 = 17.12 MHz
• FTW = 17.12/(2 × 122.88) × 232 = 0x11D55555 Start-Up Sequence The following procedure sets the power clock and register write sequencing for reliable device start-up: 1. Power up the device (no specific power supply sequence is required). 2. Apply stable REFCLK input signal. 3. Apply stable DCI input signal. 4. Issue a hardware reset (optional). As a result, the device configuration register write sequence is 0x00 Æ 0x20 /* Issue software reset */ 0x00 Æ 0x00 0x0C Æ 0xD1 /* Start PLL */ 0x0D Æ 0xD9 0x0A Æ 0xC0 0x0A Æ 0x80 /* ??Verify PLL is locked?? */ Read 0x0E, expect Bit 7 = 1, Bit 6 = 0 Read 0x06, expect 0x5C 0x10 Æ 0x48 /* Choose data rate mode */ 0x17 Æ 0x04 /* Issue software FIFO reset */ 0x18 Æ 0x02 0x18 Æ 0x00 Read 0x18, expect 0x05 Read 0x19, expect 0x07 0x1B Æ 0x84 /* Configure interpolation filters */ 0x1C Æ 0x04 0x1D Æ 0x24 0x1E Æ 0x01 /* Configure NCO */ 0x30 Æ 0x55 0x31 Æ 0x55 0x32 Æ 0xD5 0x33 Æ 0x11 0x36 Æ 0x01 /* Update frequency tuning word */ 0x36 Æ 0x00

0.20 REF

0.80 MAX

0.05 MAX

0.02 NOM

8.50 REF

Figure 89. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 56 of 56 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D09016-0-6/10(0)