AD9119

AD9119/AD9129 (Rev. B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 66

Technical content

11-/14-Bit, 5.7 GSPS, RF Digital-to-Analog Converter Data Sheet AD9119/AD9129 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 2013-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

DAC update rate: up to 5.7 GSPS Direct RF synthesis at 2.85 GSPS data rate DC to 1.425 GHz in baseband mode DC to 1.0 GHz in 2× interpolation mode 1.425 GHz to 4.2 GHz in Mix-Mode Bypassable 2× interpolation Excellent dynamic performance Supports DOCSIS 3.0 wideband ACLR/harmonic performance

8 QAM carriers: ACLR > 65 dBc

Industry-leading single/multicarrier IF or RF synthesis 4-carrier W-CDMA ACLR at 2457.6 MSPS f OUT = 900 MHz, ACLR = 71 dBc (baseband mode) fOUT = 2100 MHz, ACLR = 68 dBc (Mix-Mode) fOUT = 2700 MHz, ACLR = 67 dBc (Mix-Mode) Dual-port LVDS and DHSTL data interface Up to 1.425 GSPS operation Source synchronous DDR clocking with parity bit Low power: 1.0 W at 2.85 GSPS (1.3 W at 5.7 GSPS)

APPLICATIONS

Broadband communications systems CMTS/VOD Wireless infrastructure: W-CDMA, L TE, point-to-point Instrumentation, automatic test equipment (ATE) Radar, jammers FUNCTIONAL BLOCK DIAGRAM SDO SDIO SCLK CS DCI_x DATA ASSEMBLER SPI RESET Tx DAC CORE DATA LATCH IOUTP IOUTN IRQ 4× FIFO 2× BASEBAND MODE MIX- MODE FRM_x (FRAME/ PARITY) AD9129 CLOCK DISTRIBUTION VREFI250U LVDS DDR RECEIVER LVDS DDR RECEIVER P1_D[13:0]P, P1_D[13:0]N P0_D[13:0]P, P0_D[13:0]N DLL 1.2V PLL DCO_x NORMAL 11149-001DACCLK_x DCR F igure 1. GENERAL DESCRIPTION The AD9119/AD9129 are high performance, 11-/14-bit RF digital- to-analog converters (DACs) supporting data rates up to 2.85 GSPS. The DAC core is based on a quad-switch architecture that enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode™ or 2× interpolation. The high dynamic range and bandwidth enable multicarrier generation up to 4.2 GHz. In baseband mode, wide bandwidth capability combines with high dynamic range to support from 1 to 158 contiguous carriers for CATV infrastructure applications. A choice of two optional 2× interpolation filters is available to simplify the postreconstruction filter by effectively increasing the DAC update rate by a factor of 2. In Mix-Mode operation, the AD9119/AD9129 can reconstruct RF carriers in the second and third Nyquist zone while still maintaining exceptional dynamic range up to 4.2 GHz. The high performance NMOS DAC core features a quad-switch architecture that enables industry-leading direct RF synthesis performance with minimal loss in output power. The output current can be programmed over a range of 9.5 mA to 34.4 mA. The AD9119/AD9129 include several features that may further simplify system integration. A dual-port, source synchronous LVDS interface simplifies the data interface to a host FPGA/ASIC. A differential frame/parity bit is also included to monitor the integrity of the interface. On-chip delay locked loops (DLLs) optimize timing between different clock domains. A serial peripheral interface (SPI) configures the AD9119/ AD9129 and monitors the status of readback registers. The AD9119/AD9129 are manufactured on a 0.18 µm CMOS process and operates from +1.8 V and −1.5 V supplies. It is supplied in a 160-ball chip scale package ball grid array. PRODUCT HIGHLIGHTS 1. High dynamic range and signal reconstruction bandwidth support RF signal synthesis of up to 4.2 GHz. 2. Dual-port interface with double data rate (DDR) LVDS data receivers supports 2850 MSPS maximum conversion rate. 3. Manufactured on a CMOS process; a proprietary switching technique enhances dynamic performance.

Rev. B | Page 2 of 66 TABLE OF CONTENTS

REVISION HISTORY

6/2017—Rev. A to Rev. B 9/2013—Re v. 0 to Rev. A Changes to Table 53, Table 54, Table 55, Table 56, and Table 57 ... 64 1/2013—R evision 0: Initial Version

Rev. B | Page 3 of 66 SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD = 1.8 V, VSSA = −1.5 V , IOUTFS = 33 mA, TA = −40°C to +85°C. Table 1. AD9119 AD9129 Parameter Min Typ Max Min Typ Max Unit RESOLUTION 11 14 Bits ACCURACY Integral Nonlinearity (INL) 0.2 1.4 LSB Differential Nonlinearity (DNL) 0.15 1.1 LSB ANALOG OUTPUTS Gain Error (with Internal Reference) +2.5 +2.5 % Output Compliance Range 1.5 2.5 1.5 2.5 V Output Impedance1 DAC CLOCK INPUT (DACCLK_P, DACCLK_N) Differential Peak-to-Peak Voltage 0.4 1 2 0.4 1 2 V Common-Mode Voltage 1.2 1.2 V TEMPERATURE DRIFT Gain 60 60 ppm/°C Reference Voltage 20 20 ppm/°C REFERENCE Internal Reference Voltage 1.0 1.0 V Output Resistance 5 5 kΩ ANALOG SUPPLY VOLTAGES DIGITAL SUPPLY VOLTAGES SUPPLY CURRENTS AND POWER DISSIPATION, 2.3 GSPS (NORMAL MODE) IVDDA 202 209 202 209 mA IVSSA 53 54 53 54 mA IDVDD 307 327 307 327 mA Power Dissipation Normal Mode 1.0 1.05 1.0 1.05 W FIR25 Enabled 1.17 1.24 1.17 1.24 W FIR40 Enabled 1.3 1.4 1.3 1.4 W Reduced Power Mode, Power-Down Enabled (Register 0x01 = 0xEF) IVDDA 7.6 7.6 mA IVSSA 6 6 µA IVDD 0.4 0.4 mA SUPPLY CURRENTS AND POWER DISSIPATION, 2.8 GSPS (NORMAL MODE) IVDDA 230 230 mA IVSSA 53 53 mA IDVDD 336 336 mA Power Dissipation (Normal Mode) 1.1 1.1 W 1 For more information about output impedance, see the Output Stage Configuration section.

Rev. B | Page 4 of 66 LVDS DIGITAL SPECIFICATIONS VDDA = VDD = 1.8 V , VSSA = −1.5 V , IOUTFS = 33 mA, TA = −40°C to +85°C. LVDS drivers and receivers are compatible with the IEEE Standard 1596.3-1996, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit LVDS DATA INPUTS (P1_D[13:0]P , P1_D[13:0]N, P0_D[13:0]P , P0_D[13:0]N, FRM_P , FRM_N) P x_DxP = VIA, Px_DxN = VIB Input Voltage Range VIA, VIB 825 157 5 mV Input Differential Threshold VIDTH − 100 + 100 mV Input Differential Hysteresis VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance RIN 80 120 Ω LVDS Input Rate 14 25 MS PS Input Capacitance 1. 2 pF LVDS CLOCK INPUTS (DCI_P , DCI_N) DC I_P = VIA, DCI_N = VIB Input Voltage Range VIA, VIB 825 157 5 mV Input Differential Threshold VIDTH − 225 + 225 mV Input Differential Hysteresis VIDTHH − VIDTHL 20 m V Receiver Differential Input Impedance RIN 80 120 Ω Maximum Clock Rate 712. 5 MH z LVDS CLOCK OUTPUTS (DCO_P , DCO_N) D CO_P = VOA, DCO_N = VOB, 100 Ω termination Output Voltage High VOA, VOB 137 5 mV Output Voltage Low VOA, VOB 102 5 m V Output Differential Voltage |VOA|, |VOB| Register 0x7C[7:6] = 01b (default) 200 225 250 mV Output Offset Voltage VOS 115 0 125 0 mV Output Impedance, Single-Ended RO 80 100 120 Ω RO Mismatch Between A and B ∆RO 10 % Change in |VOD| Between Setting 0 and Setting 1 |∆VOD| 25 m V Change in VOS Between Setting 0 and Setting 1 ∆VOS 25 m V Output Current Driver Shorted to Ground ISA, ISB 20 m A Drivers Shorted Together ISAB 4 m A Power-Off Output Leakage |IXA|, |IXB| 10 µA Maximum Clock Rate 712. 5 MH z HSTL DIGITAL SPECIFICATIONS VDDA = VDD = 1.8 V , VSSA = −1.5 V, IOUTFS = 33 mA, TA = −40°C to +85°C. HSTL receiver levels are compatible with the EIA/JEDEC JESD8-6 standard, unless otherwise noted. Table 3. Parameter Symbol Test Comments/Conditions Min Typ Max Unit HSTL DATA INPUTS (P1_D[13:0]P , P1_D[13:0]N, P0_D[13:0]P , P0_D[13:0]N, FRM_P , FRM_N) P x_DxP = VIA, Px_DxN = VIB Common-Mode Input Voltage Range VIA, VIB 0. 68 0. 9 V Differential Input Voltage 200 m V Receiver Differential Input Impedance RIN 80 120 Ω HSTL Input Rate 142 5 MS PS Input Capacitance 1. 2 pF HSTL CLOCK INPUT (DCI_P , DCI_N) DC I_P = VIA, DCI_N = VIB Common-Mode Input Voltage Range VIA, VIB 0. 68 0. 9 mV Differential Input Voltage 450 m V Receiver Differential Input Impedance RIN 80 120 Ω Maximum Clock Rate 712. 5 MH z

Rev. B | Page 5 of 66 SERIAL PORT AND CMOS PIN SPECIFICATIONS VDDA = VDD = 1.8 V , VSSA = −1.5 V , IOUTFS = 33 mA, TA = −40°C to +85°C. Table 4. Parameter Symbol Test Comments/Conditions Min Typ Max Unit WRITE OPERATION S ee Figure 126 SCLK Clock Rate fSCLK, 1/tSCLK 20 MH z SCLK Clock High tHIGH 20 n s SCLK Clock Low tLOW 20 n s SDIO to SCLK Setup Time tDS 10 ns SCLK to SDIO Hold Time tDH 5 ns CS to SCLK Setup Time tS 10 ns SCLK to CS Hold Time tH 5 ns READ OPERATION S ee Figure 127 SCLK Clock Rate fSCLK, 1/tSCLK 20 MH z SCLK Clock High tHIGH 20 n s SCLK Clock Low tLOW 20 ns SDIO to SCLK Setup Time tDS 10 ns SCLK to SDIO Hold Time tDH 5 ns CS to SCLK Setup Time tS 10 ns SCLK to SDIO (or SDO) Data Valid Time tDV 10 ns CS to SDIO (or SDO) Output Valid to High-Z tEZ 2 INPUTS (SDI, SDIO, SCLK, CS) Voltage In High VIH 1. 2 1.8 V Voltage In Low VIL 0 0. 4 V Current In High IIH + 75 µA Current In Low IIL − 150 µA OUTPUTS (SDIO, SYNC) Voltage Out High VOH 1. 3 2. 0 V Voltage Out Low VOL 0 0. 3 V Current Out High IOH 4 mA Current Out Low IOL 4 mA

Rev. B | Page 6 of 66 AC SPECIFICATIONS VDDA = VDD = 1.8 V , VSSA = −1.5 V , IOUTFS = 33 mA, TA = −40°C to +85°C, unless otherwise noted. Table 5. AD 9119 AD9129 Parameter Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE DAC Update Rate (DACCLK_x Inputs) Normal Mode, FIR25 Enabled, or FIR40 Enabled with VDD = 1.9 V 1400 2850 1400 2850 MS PS FIR40 Filter Enabled, VDD = 1.8 V 1400 2600 140 0 2600 MS PS Adjusted DAC Update Rate1 1400 2850 140 0 2850 MS PS Output Settling Time to 0.1% 13 13 ns SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 2600 MSPS fOUT = 100 MHz −76 −76 dBc fOUT = 350 MHz −65 −65 dBc fOUT = 550 MHz −63 −64 dBc fOUT = 950 MHz −55 −55 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 2600 MSPS, fOUT2 = fOUT1 + 1.4 MHz fOUT = 100 MHz −82 −86 dBc fOUT = 350 MHz −78 −85 dBc fOUT = 550 MHz −73 −83 dBc fOUT = 950 MHz −67 −76 dBc NOISE SPECTRAL DENSITY (NSD) Single Tone, fDAC = 2800 MSPS fOUT = 100 MHz −157 −166 dBm /Hz fOUT = 350MHz −157 −162 dBm /Hz fOUT = 550 MHz −155 −158 dBm /Hz fOUT = 850 MHz −154 −157 dBm /Hz DOCSIS ACLR PERFORMANCE (50 MHz to 1000 MHz) at ≥6 MHz OFFSET fDAC = 2782 MSPS

8 Contiguous Carriers 64 64 dBc

16 Contiguous Carriers 62 63 dBc

32 Contiguous Carriers 60 61 dBc

W-CDMA ACLR (SINGLE CARRIER) Adjacent Channel fDAC = 2605.056 MSPS, fOUT = 750 MHz 75 75 dBc fDAC= 2605.056 MSPS, fOUT = 950 MHz 74 74 dBc fDAC = 2605.056 MSPS, fOUT = 1700 MHz (Mix-Mode) 73.5 73.5 dBc fDAC = 2605.056 MSPS, fOUT = 2100 MHz (Mix-Mode) 69 69 dBc Alternate Adjacent Channel fDAC = 2605.056 MSPS, fOUT = 750 MHz 80 80 dBc fDAC = 2605.056 MSPS, fOUT = 950 MHz 78 78 dBc fDAC = 2605.056 MSPS, fOUT = 1700 MHz (Mix-Mode) 74 74 dBc fDAC = 2605.056 MSPS, fOUT = 2100 MHz (Mix-Mode) 72 72 dBc 1 Adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9119/AD9129, the minimum interpolation factor is 1. Thus, with fDAC = 2850 MSPS, fDAC adjusted = 2850 MSPS.

soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Table 8. AD9119 Pin Function Descriptions A2 VREF Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor. A3, A4, B3, B4, B5, C4, C5, C6 VSSA −1.5 V Analog Supply Voltage Input. A5, A8, B6, B7 VDDA SH +1.8 V Analog Supply Shield. Tie these pins to VDDA at the DAC. VDDA +1.8 V Analog Supply Voltage Input.

Rev. B | Page 9 of 66 Pin No. Mnemonic Description G12, G13, G14, H11, H12, H13, H14, J3, J4, J11, J12, J13, J14 VDD +1.8 V Digital Supply Voltage Input. C13, C14, D12, D13, D14, E11, E12, E13, E14, F11, F12, F13, F14, G1, G2, G3, G11, H3, H4 VSS +1.8 V Digital Supply Return. A12, A13, A14, B12, B13, C11, C12, D5, D6, D8, D9, D10, D11, E3, E4, F1, F2, F3, F4, G4 VSSC Analog Supply Return. A6 IOUTP DAC Positive Current Output Source. A7 IOUTN DAC Negative Current Output Source. B14 SYNC Synchronization Signal Output. C1, D1 DACCLK_N, DACCLK_P Negative/Positive DAC Clock Input. H1 RESET Reset Input. Active high. If unused, tie this pin to VSS. H2 IRQ Interrupt Request Open Drain Output. Active high. Pull up this pin to VDD with a 1 kΩ resistor. J1 SDIO Serial Port Data Input/Output. J2 SDO Serial Port Data Output. K1 SCLK Serial Port Clock Input. K2 CS Serial Port Enable Input. K3, K4 DCI_P , DCI_N Positive, Negative Data Clock Input (DCI). K11, K12 D C O _ P, DCO_N Positive, Negative Data Clock Output (DCO). K13, K14 FRM_P , FRM_N Positive, Negative Data Frame/Parity Signal (FRAME/PARITY). L1, M1 NC, NC No Connect. Do not connect to this pin. L2, M2 NC, NC No Connect. Do not connect to this pin. L3, M3 NC, NC No Connect. Do not connect to this pin. L4, M4 P1_D0P , P1_D0N Data Port 1 Positive/Negative Data Input Bit 0. LSB. L5, M5 P1_D1P , P1_D1N Data Port 1 Positive/Negative Data Input Bit 1. L6, M6 P1_D2P , P1_D2N Data Port 1 Positive/Negative Data Input Bit 2. L7, M7 P1_D3P , P1_D3N Data Port 1 Positive/Negative Data Input Bit 3. L8, M8 P1_D4P , P1_D4N Data Port 1 Positive/Negative Data Input Bit 4. L9, M9 P1_D5P , P1_D5N Data Port 1 Positive/Negative Data Input Bit 5. L10, M10 P1_D6P , P1_D6N Data Port 1 Positive/Negative Data Input Bit 6. L11, M11 P1_D7P , P1_D7N Data Port 1 Positive/Negative Data Input Bit 7. L12,M12 P1_D8P , P1_D8N Data Port 1 Positive/Negative Data Input Bit 8. L13, M13 P1_D9P , P1_D9N Data Port 1 Positive/Negative Data Input Bit 9. L14, M14 P1_D10P , P1_D10N Data Port 1 Positive/Negative Data Input Bit 10. MSB. N1, P1 NC, NC No Connect. Do not connect to this pin. N2, P2 NC, NC No Connect. Do not connect to this pin. N3, P3 NC, NC No Connect. Do not connect to this pin. N4, P4 P0_D0P , P0_D0N Data Port 0 Positive/Negative Data Input Bit 0. LSB. N5, P5 P0_D1P , P0_D1N Data Port 0 Positive/Negative Data Input Bit 1. N6, P6 P0_D2P , P0_D2N Data Port 0 Positive/Negative Data Input Bit 2. N7, P7 P0_D3P , P0_D3N Data Port 0 Positive/Negative Data Input Bit 3. N8, P8 P0_D4P , P0_D4N Data Port 0 Positive/Negative Data Input Bit 4. N9, P9 P0_D5P , P0_D5N Data Port 0 Positive/Negative Data Input Bit 5. N10, P10 P0_D6P , P0_D6N Data Port 0 Positive/Negative Data Input Bit 6. N11, P11 P0_D7P , P0_D7N Data Port 0 Positive/Negative Data Input Bit 7. N12, P12 P0_D8P , P0_D8N Data Port 0 Positive/Negative Data Input Bit 8. N13, P13 P0_D9P , P0_D9N Data Port 0 Positive/Negative Data Input Bit 9. N14, P14 P0_D10P , P0_D10N Data Port 0 Positive/Negative Data Input Bit 10. MSB.

Table 9. AD9129 Pin Function Descriptions A2 VREF Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor. A3, A4, B3, B4, B5, C4, C5, C6 VSSA −1.5 V Analog Supply Voltage Input. A5, A8, B6, B7 VDDA SH +1.8 V Analog Supply Shield. Tie these pins to VDDA at the DAC. VDDA +1.8 V Analog Supply Voltage Input. VDD +1.8 V Digital Supply Voltage Input. VSS +1.8 V Digital Supply Return.

Rev. B | Page 11 of 66 Pin No. Mnemonic Description A12, A13, A14, B12, B13, C11, C12, D5, D6, D8, D9, D10, D11, E3, E4, F1, F2, F3, F4, G4 VSSC Analog Supply Return. A6 IOUTP DAC Positive Current Output Source. A7 IOUTN DAC Negative Current Output Source. B14 SYNC Synchronization Signal Output. C1, D1 DACCLK_N, DACCLK_P Negative/Positive DAC Clock Input. H1 RESET Reset Input. Active high. If unused, tie this pin to VSS. H2 IRQ Interrupt Request Open-Drain Output. Active high. Pull up this pin to VDD with a 1 kΩ resistor. J1 SDIO Serial Port Data Input/Output. J2 SDO Serial Port Data Output. K1 SCLK Serial Port Clock Input. K2 CS Serial Port Enable Input. K3, K4 DCI_P , DCI_N Positive, Negative Data Clock Input (DCI). K11, K12 D C O _ P, DCO_N Positive, Negative Data Clock Output (DCO). K13, K14 FRM_P , FRM_N Positive, Negative Data Frame/Parity Signal (FRAME/PARITY). L1, M1 P1_D0P , P1_D0N Data Port 1 Positive/Negative Data Input Bit 0. LSB. L2, M2 P1_D1P , P1_D1N Data Port 1 Positive/Negative Data Input Bit 1. L3, M3 P1_D2P , P1_D2N Data Port 1 Positive/Negative Data Input Bit 2. L4, M4 P1_D3P , P1_D3N Data Port 1 Positive/Negative Data Input Bit 3. L5, M5 P1_D4P , P1_D4N Data Port 1 Positive/Negative Data Input Bit 4. L6, M6 P1_D5P , P1_D5N Data Port 1 Positive/Negative Data Input Bit 5. L7, M7 P1_D6P , P1_D6N Data Port 1 Positive/Negative Data Input Bit 6. L8, M8 P1_D7P , P1_D7N Data Port 1 Positive/Negative Data Input Bit 7. L9, M9 P1_D8P , P1_D8N Data Port 1 Positive/Negative Data Input Bit 8. L10, M10 P1_D9P , P1_D9N Data Port 1 Positive/Negative Data Input Bit 9. L11, M11 P1_D10P , P1_D10N Data Port 1 Positive/Negative Data Input Bit 10. L12,M12 P1_D11P , P1_D11N Data Port 1 Positive/Negative Data Input Bit 11. L13, M13 P1_D12P , P1_D12N Data Port 1 Positive/Negative Data Input Bit 12. L14, M14 P1_D13P , P1_D13N Data Port 1 Positive/Negative Data Input Bit 13. MSB. N1, P1 P0_D0P , P0_D0N Data Port 0 Positive/Negative Data Input Bit 0. LSB. N2, P2 P0_D1P , P0_D1N Data Port 0 Positive/Negative Data Input Bit 1. N3, P3 P0_D2P , P0_D2N Data Port 0 Positive/Negative Data Input Bit 2. N4, P4 P0_D3P , P0_D3N Data Port 0 Positive/Negative Data Input Bit 3. N5, P5 P0_D4P , P0_D4N Data Port 0 Positive/Negative Data Input Bit 4. N6, P6 P0_D5P , P0_D5N Data Port 0 Positive/Negative Data Input Bit 5. N7, P7 P0_D6P , P0_D6N Data Port 0 Positive/Negative Data Input Bit 6. N8, P8 P0_D7P , P0_D7N Data Port 0 Positive/Negative Data Input Bit 7. N9, P9 P0_D8P , P0_D8N Data Port 0 Positive/Negative Data Input Bit 8. N10, P10 P0_D9P , P0_D9N Data Port 0 Positive/Negative Data Input Bit 9. N11, P11 P0_D10P , P0_D10N Data Port 0 Positive/Negative Data Input Bit 10. N12, P12 P0_D11P , P0_D11N Data Port 0 Positive/Negative Data Input Bit 11. N13, P13 P0_D12P , P0_D12N Data Port 0 Positive/Negative Data Input Bit 12. N14, P14 P0_D13P , P0_D13N Data Port 0 Positive/Negative Data Input Bit 13. MSB.

IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. Figure 20. Single-Tone NSD vs. fOUT over Temperature

Rev. B | Page 28 of 66 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –70 1000 20001500 2500 3500 fOUT (MHz) SFDR (dBc) 40003000 –50 –55 –65 –60 –45 –40 –35 –30 –25 SECOND NYQUIST ZONE THIRD NYQUIST ZONE –16dBFS –12dBFS –6dBFS 0dBFS 11149-099 F igure 90. SFDR vs. fOUT over Digital Full Scale –80 1000 20001500 2500 35003000 fOUT (MHz) IMD (dBc) 4000 –60 –65 –70 –75 –50 –55 –45 SECOND NYQUIST ZONE THIRD NYQUIST ZONE –16dBFS –12dBFS –6dBFS 0dBFS 11149-100 F igure 91. IMD vs. fOUT over Digital Full Scale –90 1000 1500 25002000 3000 3500 fOUT (MHz) SFDR (dBc) 4000 –10 –20 –30 –40 –50 –60 –70 –80 SECOND NYQUIST ZONE THIRD NYQUIST ZONE 11mA 22mA 33mA 11149-101 F igure 92. SFDR vs. fOUT over DAC IOUTFS –90 1000 20001500 2500 35003000 fOUT (MHz) IMD (dBc) 4000 –60 –70 –80 –50 –40 –30 11149-193 SECOND NYQUIST ZONE THIRD NYQUIST ZONE 11mA 22mA 33mA F igure 93. IMD vs. fOUT over DAC IOUTFS

Rev. B | Page 29 of 66 IOUTFS = 28 mA, fDAC = 2.6 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –170 1000 20001500 2500 35003000 fOUT (MHz) NSD (dBm/Hz) 4000 –160 –165 –150 –155 –145 11149-105 –40°C +25°C +85°C F igure 94. Single-Tone NSD vs. fOUT over Temperature CENTER 1.888GHz VBW 3kHz 10dB/DIV SPAN 53.84MHz SWEEP 1.485s –20 –30 –50 –40 –80 –70 –60 –90 –120 –110 –100 OFFSET FREQ 5MHz 10MHz 15MHz 20MHz 25MHz INTEG BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz 3.84MHz dBc –73.71 –77.40 –78.04 –78.13 –78.01 dBm –83.15 –86.84 –87.48 –87.57 –87.46 dBc –74.00 –77.31 –77.85 –78.51 –78.43 dBm –83.45 –86.75 –87.30 –87.96 –87.87 FILTER OFF OFF OFF OFF OFF TOTAL CARRIER POWER –9.445dBm/3.84MHz 11149-107 UPPERLOWER F igure 95. Single-Carrier W-CDMA at 1887.5 MHz –165 1500 25002000 3000 3500 fOUT (MHz) NSD (dBm/Hz) –150 –155 –160 –145 –40°C +25°C +85°C 11149-106 F igure 96. W-CDMA NSD vs. fOUT over Temperature CENTER 1.98GHz VBW 3kHz 10dB/DIV SPAN 58.84MHz SWEEP 1.623s –20 –30 –50 –40 –80 –70 –60 –90 –120 –110 –100 OFFSET FREQ 5MHz 10MHz 15MHz 20MHz INTEG BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz dBc –69.05 –69.86 –70.81 –71.03 dBm –85.24 –86.05 –87.00 –87.22 dBc –69.03 –69.71 –70.52 –70.91 dBm –85.22 –85.90 –86.71 –87.10 FILTER OFF OFF OFF OFF UPPERLOWER TOTAL CARRIER POWER –10.211dBm/15.36MHz 11149-108 F igure 97. Four-Carrier W-CDMA at 1980 MHz

IOUTFS = 33 mA, fDAC = 2.782 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. Figure 120. Gap Channel ACLR vs. fOUT

Rev. B | Page 35 of 66 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero. For IOUTP , 0 mA output is expected when the inputs are all 0s. For IOUTN, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Specified as the maximum change from the ambient (25°C) value to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius (°C). For reference drift, the drift is reported in ppm per °C. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Spurious-Free Dynamic Range The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Noise Spectral Density (NSD) The converter noise power per unit of bandwidth. This is usually specified in dBm/Hz in the presence of a 0 dBm full- scale signal. Adjacent Channel Leakage Ratio (ACLR) The ratio, in dBc, between the measured power within a channel relative to its adjacent channels. Adjacent Channel Power Ratio (ACPR) The ratio, in dBc, between the total power of an adjacent channel (intermodulation signal) to the main channel's power (useful signal). Modulation Error Ratio (MER) A measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol. Modulated signals create a discrete set of output values referred to as a constellation, and each symbol creates an output signal corresponding to one point on the constellation. Intermodulation Distortion (IMD) The result of two or more signals at different frequencies mixing together. Many products are created according to the formula aF1 ± bF2, where a and b are integer values.

Rev. B | Page 36 of 66 SERIAL COMMUNICATIONS PORT OVERVIEW The AD9119/AD9129 are 11-bit/14-bit DACs that operate at an update rate of up to 2.85 GSPS. Due to internal timing requirements, the minimum allowable sample rate is 1400 MSPS. Input data is sampled through two 11-/14-bit LVDS ports that are internally multiplexed. Each port has its own data inputs, but both ports share a common data clock input (DCI). The LVDS inputs meet the IEEE-1596 specification with the exception of input hysteresis, which is not guaranteed over all process corners. Each DCI input runs at one-quarter the input data rate in a double data rate (DDR) format. Each edge of the DCI is used to transfer data into the AD9119/AD9129. The DACCLK_N and DACCLK_P inputs directly drive the DAC core to minimize clock jitter. The DACCLK signal is divided by 4 and then output as the DCO for each port. The DCO signal can be used to clock the data source. The DAC expects DDR LVDS data (P0_D[13:0]x, P1_D[13:0]x), with each channel aligned with the single DDR DCI signal. Control of the AD9119/AD9129 functions is via a SPI. SERIAL PERIPHERAL INTERFACE (SPI) The AD9119/AD9129 SPI is a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including the Motorola® SPI and the Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9119/AD9129. Most significant bit first (MSB-first) or least significant bit first (LSB-first) transfer formats are supported. The AD9119/AD9129 serial interface port can be configured as a single I/O pin (SDIO) or two unidirectional pins for input/ output (SDIO and SDO). SDO (PIN J2) SDIO (PIN J1) SCLK (PIN K1) CS (PIN K2) AD9119/ AD9129 SPI PORT 11149-126 F igure 121. AD9119/AD9129 SPI Port GENERAL OPERATION OF THE SPI There are two phases to a communication cycle with the AD9119/ AD9129. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9119/AD9129, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9119/AD9129 serial port controller with information about the data transfer cycle, which is Phase 2 of the communi- cation cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9119/AD9129. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9119/ AD9129 and the system controller. Phase 2 of the communication cycle is a transfer of one byte only. Single-byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. CS (chip select) can be raised after each sequence of eight bits (except the last byte) to stall the bus. The serial transfer resumes when CS is lowered. Stalling on nonbyte boundaries resets the SPI. INSTRUCTION MODE (8-BIT INSTRUCTION) The instruction byte is shown in the following table. MSB LS B I7 I6 I5 I4 I3 I2 I1 I0 R/W A6 A5 A4 A3 A2 A1 A0 R/W , Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation, the data transfer cycle. A6 to A0 (Bit 6 through Bit 0 of the instruction byte) determine which register is accessed during the data transfer portion of the communications cycle. SERIAL PERIPHERAL INTERFACE PIN DESCRIPTIONS SCLK—Serial Clock The serial clock pin is used to synchronize data to and from the AD9119/AD9129 and to run the internal state machines. The maximum frequency of SCLK is 20 MHz. All data input to the AD9119/AD9129 is registered on the rising edge of SCLK. All data is driven out of the AD9119/AD9129 on the rising edge of SCLK. CS—Chip Select Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communi- cations lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SDIO—Serial Data I/O Data is always written into the AD9119/AD9129 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7 (SDIO_DIR). The default is Logic 1, which configures the SDIO pin as bidirectional. SDO—Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data. When the AD9119/AD9129 are operating in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state.

significant bit to the least significant bit.

1. Serial Register Interface Timing, MSB-First Write
2. Serial Register Interface Timing, MSB-First Read

Figure 124. Serial Register Interface Timing, LSB-First Write

1. Serial Register Interface Timing, LSB-First Read
2. Timing Diagram for an SPI Register Write
3. Timing Diagram for an SPI Register Read

AD9119/ AD9129 devices cannot be daisy-chained on the SPI bus.

Rev. B | Page 38 of 66 THEORY OF OPERATION The AD9119/AD9129 are 11-bit/14-bit DACs that are capable of reconstructing signal bandwidths up to 1.425 GHz while operating with an input data rate up to 2.85 GSPS. Figure 128 shows a top level functional diagram of the AD9119/AD9129. A high perfor-mance NMOS DAC delivers a signal dependent, differential current to a balanced external load referenced a nominal 1.8 V analog supply. The current source array of the DAC is referenced to an external −1.5 V supply, and its full-scale current, IOUTFS, can be adjusted over a 9.5 mA to 34.4 mA span. 11149-133 SDO SDIO SCLK CS DCI_x DATA ASSEMBLER SPI RESET Tx DAC CORE DATA LATCH IOUTP IOUTN IRQ 4× FIFO 2× BASEBAND MODE MIX- MODE FRM_x (FRAME/ PARITY) AD9129 CLOCK DISTRIBUTION VREFI250U LVDS DDR RECEIVER LVDS DDR RECEIVER P1_D[13:0]P, P1_D[13:0]N P0_D[13:0]P, P0_D[13:0]N DLL 1.2V PLL DCO_x NORMAL DACCLK_x DCR F igure 128. Functional Block Diagram of the AD9119/AD9129 A low jitter differential clock receiver is used to square up the signal appearing at the DACCLK_x input that sets the update rate of the DAC. The differential clock receiver can accept sinusoidal signals with negligible noise spectral density degra- dation if the input signal level is maintained above 0 dBm. A +1 dB degradation occurs at a −5 dBm input, and degradation increases as the signal approaches −10 dBm and its associated +2 dB additional degradation. A duty cycle restorer (DCR), following the clock receiver, ensures near 50% duty-cycle to the subsequent circuitry. The output of the DCR serves as the master clock and is routed directly to the DAC, as well as to a clock distribution block that generates all critical internal and external clocks. The clock source quality, as defined by its phase noise characteristics, jitter, and drive capability, is an important consideration in maintaining optimum ac performance. The AD9119/AD9129 supports a source synchronous, LVDS double data-rate (DDR) data interface to the host processor. Two 11-bit/14-bit LVDS data ports (P0_DxP , P0_DxN and P1_Dx P, P 1 _ D x N) are used to sample de-interleaved data from the host on the rising and falling edge of the host DCI clock. This effectively reduces the bus interface speed to ½ the data rate (for example, f DATA/2) with the DCI clock operating at fDATA/4. An optional parity bit can also be sent along with the data to enhance the robustness of the interface. In this case, a counter is available to count parity errors and generate an interrupt request (IRQ) when a programmable threshold is exceeded. The AD9119/AD9129 provide the host with a DCO clock that is equal to the DCI clock frequency to establish synchronous opera- tion. A delay locked loop (DLL) with programmable phase offset is used to generate an internal sampling clock with optimum edge placement for the input data latches of the LVDS DDR receivers. When data is latched into the AD9119/AD9129, an eight-sample- deep FIFO is used to hand off the data between the host and the AD9119/AD9129 clock domains. The FIFO can be reset with an external synchronization signal, fSYNC, to ensure consistent pipeline latency. The pipeline delay, from a sample being latched into the data port to when it appears at the DAC output, varies depending on the chosen configuration (see the Pipeline Delay (Latency) section). The de-interleaved data is reassembled into its original data stream after passing into the internal clock domain of the AD9119/ AD9129. Because the quad-switch architecture of the DAC updates its output on both the rising and falling edge (for example, dual edge clocking) of the DACCLK signal, the following two additional modes of operation are available:

• A 2× interpolation filter can be selected to increase th e ef fective DAC update rate (fDAC) to be 2× the input data rate, hence simplifying the analog postfiltering require- ments and reducing the effects of alias harmonics in the desired baseband region.
• A Mix-Mode option essentially generates the complement sample on the falling edge such that the original Nyquist spectrum is shifted to f DACCLK, with the sinc null of the DAC falling at 2 × fDACCLK. The digital handoff between the digital domain and mixed signal domain of a high speed DAC is critical in preserving its output dynamic range. A phase locked loop (PLL) with programmable phase offset is used to optimize the timing handoff between these two clock domains. State machines are used to initialize both the DLL and the PLL during the initial boot sequence after receiving a stable DACCLK signal. Following initialization of the two loops, they maintain optimum timing alignment over temperature, time, and power supply variation. The AD9119/AD9129 also provide IRQ capability to monitor the DLL, the PLL, and other internal circuitry.

Rev. B | Page 39 of 66 LVDS DATA PORT INTERFACE The AD9119/AD9129 can operate with input data rates of up to 2.85 GSPS. A source synchronous LVDS interface is used between the host and the AD9119/AD9129 to achieve these high data rates, while simplifying the interface. As shown in Figure 129, the host feeds the AD9119/AD9129 with de-interleaved input data into two 11-bit/14-bit LVDS data ports (P0_DxP , P0_DxN and P1_DxP , P1_DxN) at ½ the DAC clock rate (that is, fDACCLK/2). Along with the input data, the host provides an embedded DDR data clock input (DCI_x) at fDACCLK/4. A DLL circuit that is designed to operate with DCI clock rates of between 350 MHz and 712.5 MHz is used to generate a phase shifted version of DCI, called the data sampling clock (DSC), to register the input data on both the rising and falling edges. As shown in Figure 130, the DCI clock edges must be coincident with the data bit transitions with minimum skew and jitter. The nominal sampling point of the input data occurs in the middle of the DCI clock edges because this point corresponds to the center of the data eye. This is also equivalent to a nominal phase shift of 90°of the DCI clock. Th e data timing requirements are defined by a minimum data valid margin that is dependent on the data clock input skew, input data jitter, and the variations of the DLL delay line across delay settings. This margin is defined by subtracting from the data period any data skew, data jitter, and the keep-out window (KOW) that is defined by the sum of the set and hold times, as follows: t DATA VALID MARGIN = tDATA PERIOD − tDATA SKEW − tDATA JITTER − (tH + tS) The keep-out window, which is the sum of the set and hold times, is the area where data transitions should not occur. The timing margin allows tuning of the DLL delay setting, either automatically or in manual mode (see Figure 130). Figure 130 shows that the ideal location for the DSC signal is 90° out of phase from the DCI input. However, due to skew of the DCI relative to the data, it may be necessary to change the DSC phase offset to sample the data at the center of its eye diagram. The sampling instance can be varied in discrete increments by offsetting the nominal DLL phase shift value of 90° via Register 0x0A, Bits[3:0]. The following equation defines the phase offset relationship: Phase Offset = 90° ± n × 11.25°, |n| < 8 LVDS DDR RECEIVER DCI DCO CLOCK DISTRIBUTION DELAY LOCK LOOP LVDS DDR RECEIVER P1_D[13:0]x P0_D[13:0]x AD9129 HOST PROCESSOR LVDS DDR DRIVER 14 × 2 14 × 2 1 × 2 1 × 2 DATA DE-INTERLEAVER fDATA = fDACCLK/2 fDCO = fDACCLK /4 fDCI = fDACCLK /4 fDACCLK EVEN DATA SAMPLES ODD DATA SAMPLES OPTIONAL PARITYCOMBINED ODD/EVEN PARITY BIT 11149-134 F igure 129. Recommended Digital Interface Between the AD9119/AD9129 and the Host Processor INPUT DATA[13:0] DCI DLL PHASE DELAY tDATA PERIOD tDATA SKEW tDSC SETUP AND HOLD tDATA JITTER DATA SAMPLE CLOCK DATA EYE 11149-135 F igure 130. LVDS Data Port Timing Requirements

the DCI signal and data signals. can be determined using Table 11. be as high as possible, up to 800 mV p-p. Table 10. Data Port Set and Hold Time Window (Guaranteed) 1 Table 11 shows characterization data for selected fDAC frequencies. Other frequencies are possible, and Table 11 can be used to estimate performance.

Rev. B | Page 41 of 66 Maximizing the opening of the eye in both the DCI and data signals improves reliability of the data port interface. Use differ- ential controlled impedance traces of equal length (that is, delay) between the host processor and the AD9119/AD9129 input. To ensure coincident transitions with the data bits, implement the DCI as an additional data line with an alternating (010101…) bit sequence from the same output drivers that are used for the data. For synchronous operation between the host and the AD9119/ AD9129, the AD9119/AD9129 provide a data clock output, DCO, to the host at the same rate as DCI (that is, f DACCLK/4). Note that the DCI signal can have arbitrary phase alignment with respect to the DCO because the DLL of the AD9119/AD9129 ensures proper data hand-off between the two clock domains (that is, the host processors and the internal digital core of the AD9119/AD9129). The default reset state of the AD9119/AD9129 is to have the DCO signal disabled. To enable it, write a 1b to Register 0x0C, Bit 6. The DCO output level is controlled in Register 0x7C, Bits[7:6]. The default setting is 01b, or 2.8 mA, but it can be increased to as high as 4 mA (11b) if higher swing is necessary. The DCI signal is ac-coupled internally; therefore, a possibility exists that removing the DCI signal can cause DAC output chatter due to randomness on the DCI input. To avoid this chatter, it is recommended that the DAC output be disabled when the DCI signal is not present. To do this, program the DAC output current power-down bit in Register 0x01, Bit 6, to 1b. When the DCI signal is again present, the DAC output can be enabled by programming Register 0x01, Bit 6, to 0b. The DAC output powers up in ~2 µs. The status of the DLL can be polled by reading the data status register at Address 0x0E. Bit 0 indicates that the DLL is running and attempting lock, and Bit 7 is set to 1b when the DLL is locked. Bit 2 is set to 1b when a valid data clock is detected. The warning bits in Address 0x0E, Bits[6:4] can be used as indicators that the DAC may be operating in a nonideal location in the delay line. Note that these bits are read at the SPI port speed, which is much slower than the actual speed of the DLL. This means that these bits can show only a snapshot of what is happening, rather than giving real-time feedback. Temperature Effects The length of the delay line varies slightly across the operating temperature range, as the amount of delay through a delay cell expands or contracts slightly due to the temperature change. This can introduce a situation where the DLL may lock at one temperature extreme and then approach an unlocked state as the temperature changes (see Figure 132). In the example shown in Figure 132, the DLL can lock at Phase Setting 0 at 90° in a cold temperature. As the temperature gets hotter, the delay line changes length, and the controller adjusts the DLL control voltage to keep the 90° offset. In this case, a voltage beyond the acceptable control voltage range is required to hold the 90° phase offset. Before losing lock, the DLL controller issues a DLL warning by setting Register 0x0E, Bit 6, to 1b and setting either Bit 5 or Bit 4 to 1b. This setting indicates that the DLL is near to losing lock. If the DLL is going to reach the beginning of the delay line soon, the controller issues a start warning by setting Register 0x0E, Bit 5 and Bit 6 to 1b. This setting indicates that the DLL is at the start of the delay line, and losing lock is imminent. D0 D1 USER DCI USER DATA DATA SAMPLE CLK 90° DELAY LINE – COLD DELAY LINE – HOT 11149-236 F igure 132. Example of DLL Length Variation Across Temperature A similar situation can happen at the end of the delay line, in which case a DLL warning and a DLL end is issued. DLL end is indicated when Register 0x0E, Bit 4 and Bit 6 are set to 1b. In case of a DLL warning, action must be taken to prevent loss of lock. On a start warning, reduce the minimum delay of the delay line by removing one or several of the delay cells. This can be accomplished by setting the bits in Registers 0x70 and Register 0x71 to 0b. Begin by setting Bit 0 of Register 0x70 to 0b, then Bit 1, and so on. In some cases, up to three delay cells may need to be disabled. It is possible to disable up to six delay cells. However, in most cases, none of the cells need to be disabled. The situation varies, depending on the temperature range needed, as well as the DACCLK signal rate used. The end warning case is a theoretical possibility, but practical conditions normally dictate that it is not reachable. If the end warning is reached, the DLL must be relocked immediately. When doing initial lock (or relock) of the DLL, all delay cells must be active, with all delay cell bits in Register 0x70 and Register 0x71 set to 1b. Parity The data interface can be continuously monitored by enabling the parity bit feature in Register 0x5C, Bit 7, and configuring the FRM_P , FRM_N pins (Pin K13 and Pin K14) as parity pins by setting Register 0x07, Bits[1:0] = 1 dec. When this pin con- figuration is used, the host sends a parity bit along with each data sample. This bit is set according to the following formulas, where n is the data sample that is being checked. For even parity on the AD9129, XOR[FRM(n), P0_D0(n), P0_D1(n), P0_D2(n), ..., P0_D13(n), P1_D0(n), P1_D1(n), P1_D2(n), …, P1_D13(n)] = 0. For odd parity on the AD9129, XOR[FRM(n), P0_D0(n), P0_D1(n), P0_D2(n), ..., P0_D13(n), P1_D0(n), P1_D1(n), P1_D2(n), …, P1_D13(n)] = 1.

Rev. B | Page 42 of 66 For the AD9119, the data port is 11-bit instead of 14-bit, so P0_D11, P0_D12, P0_D13, P1_D11, P1_D12, and P1_D13 are not used in the calculation of the parity bit. Thus, the parity bit is calculated over 29 bits (including the frame/parity bit) for the AD9129 and over 23 bits for the AD9119. If a parity error occurs, the parity error counter (Register 0x5D or Register 0x5E) is incremented. Parity errors on the bits that are sampled by the rising edge of DCI increment the parity rising edge error counter (Register 0x5D) and set the parity error rising edge bit (Register 0x5C, Bit 0). Parity errors on the bits that are sampled by the falling edge of DCI increment the parity falling edge error counter (Register 0x5E) and set the parity error falling edge bit (Register 0x5C, Bit 1). The parity counter continues to accumulate until it is cleared, or until it reaches a maximum value of 255. The count can be cleared by writing 1b to Register 0x5C, Bit 5. An IRQ can be enabled to trigger when a parity error occurs by writing 1b to Register 0x04, Bit 2 for rising edge-based parity detection or to Register 0x04, Bit 3 for falling edge-based parity. The status of IRQ can be measured via Register 0x06, Bit 2 or Register 0x06, Bit 3 or by using the IRQ pin. When using the IRQ pin and more than one IRQ is enabled, check Register 0x06, Bits[3:2] when an IRQ event occurs to determine whether the IRQ was caused by a parity error. The IRQ can also be cleared by writing 1b to Register 0x06, Bit 2 or Register 0x06, Bit 3. The parity bit feature can also be used to validate the interface timing. As described previously, the host provides a parity bit with the data samples and configures the AD9119/AD9129 to generate an IRQ. The user can then sweep the sampling instance of the AD9119/AD9129 input registers to determine at what point a sampling error occurs. DIGITAL DATAPATH DESCRIPTION Figure 133 provides a more detailed diagram of the AD9119/ AD9129 digital datapath. The 22-bit/28-bit datapath with internal DDR clocking interfaces with the dual 11-bit/14-bit input data ports. Because two 11-bit/14-bit samples are captured on each clock edge of DCI, four consecutive samples are captured per DCI clock cycle. Samples captured on the rising edge of DCI propagate through the upper section at a rate of DACCLK/2 (DDR), and those captured on the falling edge propagate through the lower section. 28PARITY/ SED LOGIC INPUT LATCH INPUT LATCH REG 0 REG 1 REG 2 REG 3 REG 4 REG 5 REG 6 REG 7 RESET LOGIC FRAME SPI FIFO ALIGN REQUEST REG 0x11[7] SPI FIFO ALIGN ACKNOWLEDGE REG 0x11[6] FIFO WRITE POINTER OFFSET REG 0x12[2:0] RD PTR RESET WR PTR RESET RD PTR RESET DACCLK/4 WR PTR RESET DACCLK/4 DIST. DACCLK/4 DLLDCI DATA FRAME/ PARITY FRAME

14 BITS

F igure 133. Digital Datapath of the AD9119/AD9129

Rev. B | Page 43 of 66 After the input data has been captured, the data is passed through a logic block that monitors and/or determines the signal integrity of the high speed digital data interface. The optional parity check is used to continuously monitor the digital interface on a sample- per-sample basis, and the sample error detection (SED) can be used to validate the input data interface for system debug/test purposes. Note that the FRAME and PARITY signals share the same pin assignment because the FRAME signal is typically used during system initialization (for FIFO synchronization purposes), and parity is used in normal operation. FIFO Description The next functional block in the datapath is a set of four FIFOs that are eight registers deep. The dual port data is clocked into the FIFOs on both the rising and the falling edge of the DCI signal. The FIFO acts as a buffer that absorbs timing variations between the data source and DAC, such as the clock-to-data variation of an FPGA or ASIC. For the greatest timing margin, maintain the FIFO level near half full (that is, a difference of four between the write and read pointers). The value of the write pointer determines the FIFO register into which the input data is written, and the value of the read pointer determines the register from which data is read and fed into the data assembler. The write and read pointers are updated every time new data is loaded and removed, respectively, from the FIFO. Valid data is transmitted through the FIFO as long as the FIFO does not overflow or become empty. Note that an overflow or empty condition of the FIFO is the same as the write pointer and read pointer being equal. When both pointers are equal, an attempt is made to simultaneously read and write a single FIFO register. This simultaneous register access leads to unreliable data transfer through the FIFO and must be avoided by ensuring that data is written to the FIFO at the same rate that data is read from the FIFO, keeping the data level in the FIFO constant. This condition must be met by ensuring that DCI is equal to DACCLK/4 (or equivalently, DCO). Resetting the FIFO Data Level FIFO initialization is required to ensure a four-sample spacing and a deterministic pipeline latency. If the clocks are running at power-up, the FIFO initializes to 50% full. The AD9119/ AD9129 has an internal delay that effectively offsets the FIFO pointers by 2, such that the optimal FIFO data level of 4 (center) reads back as 2 (0000011b) from Register 0x13 to Register 0x16. To achieve this level, set Register 0x12 to 0x20 (hexadecimal) before resetting the FIFO. This sets the read pointer to Level 2 and the write pointer to Level 0. To maximize the timing margin between the DCI input and the internal DAC data rate clock, initialize the FIFO data level before beginning data transmission. The value of the FIFO data level can be initialized in three ways: by resetting the device, by strobing the FRM_x input, and via a write sequence to the serial port. The two preferred methods are use of the FRAME signal and via a write sequence to the serial port. Before initializing the FIFO data level, the LVDS DLL and the DAC clock PLL must be locked. The FRM_x input can be used to initialize the FIFO data level value. First, set up the FRM_N and FRM_P pins for frame mode (Register 0x07, Bits[1:0] = 2). Next, assert the FRAME signal high for at least one DCI clock cycle. When the FRAME signal is asserted in this manner, the write pointer is set to 4 (by default or to the FIFO start level (Register 0x12, Bits[2:0])) the next time the read pointer becomes 0 (see Figure 134). 0 1 2 3 4 5 6 7 0 1 2 3 3 4 5 6 7 0 1 2 4 5 6 7 FIFO WRITE RESETS READ POINTER FRAME WRITE POINTER 11149-137 F igure 134. Timing of the Frame Input vs. Write Pointer Value To initialize the FIFO data level through the serial port, toggle Bit 7 of Register 0x11 from 0b to 1b. When the write to the register is complete, the FIFO data level is initialized. The recommended procedure for a serial port FIFO data level initialization is as follows: 1. Request FIFO level reset by setting Register 0x11, Bit 7, to 1b. 2. Verif y that the part acknowledges the request by ensuring that Register 0x11, Bit 6, is set to 1b. 3. Remove the request by setting Register 0x11, Bit 7, to 0b. 4. Verif y that the part drops the acknowledge signal by ensuring that Register 0x11, Bit 6, is set to 0b. Monitoring the FIFO Status The relative FIFO data levels can be read from Register 0x13 through Register 0x16 at any time. The FIFO data level reported by the serial port is denoted as a 7-bit thermometer code of the write counter state, relative to the absolute read counter being at 0. For example, the FIFO data level of 2 is reported as a value of 0000011b in the status register. Adding the internal delay of 2 to this value makes the reported FIFO level equal to 4. It should be noted that, depending on the timing relationship between DCI and the main DACCLK signal, the FIFO level value can be off by a count of ±1. Therefore, it is important that the difference between the read and write pointers be maintained at ≥2. Multiple DAC Synchronization Synchronization of multiple AD9119/AD9129s implies that all of the DAC outputs are time aligned to the same phase when all devices are fed with the same data pattern (along with DCI) at the same instance of time. FIFO initialization ensures that the initial pipeline latency in the FIFO is set to four samples and remains at this level, assuming that no process, voltage, or tem- perature variations occur between the host and the AD9119/ AD9129 clock domains.

The data assembler reconstructs the original sample sequence. update the DAC decode logic on the falling edge of DACCLK. manner. The 2× interpolator can be used with Mix-Mode enabled. enabled with Register 0x18, Bit 7. The FIR25 half-band filter provides 25 dB of stop-band rejection. tilt across any 6 MHz channel is less than −0.05 dB. rejection for multicarrier applications (for example, DOCSIS). consumption. The two filters are compared in Table 12. Table 12. Features of the Two 2× Interpolation Filters to minimize impact of duty cycle errors on image rejection.

mode of operation that is selected. Table 13. Pipeline Delay Values for Each Block

• Pipeline delay is the time from DAC code latched until the DAC output begins to move.
• Group delay is the time for the maximum amplitude pulse to reach the DAC output, as compared to the first time the output moves.
• No 2× filter is the base pipeline delay, including data i nterface, analog circuitry (six cycles), and data FIFO at half-full/Position 3.
• FIR25 is the 2× interpolator with 25 dB of out-of-band rejection.
• FIR40 is the 2× interpolator with 40 dB of out-of-band rejection. Note that the values for pipeline delay apply in both normal mode and Mix-Mode. After the total delay through the digital blocks is calculated, add the FIFO level to that delay to find the total pipeline delay. Note that the pipeline delay can be considered fixed, with the only ambiguity being the FIFO state. The FIFO state can be initialized as part of the startup sequence to ensure a four sample spacing and, therefore, a fixed pipeline delay, or deterministic latency (see the Resetting the FIFO Data Level section for more information). To ensure repeatable pipeline delay over multiple power-up cycles, the SYNC output of the DAC must be aligned with a known system sync reference. Follow a calibration process that is similar to the multiple DAC sync process (see the Multiple DAC Synchronization section for more information) after each power-up event to align the DAC to the system sync reference. Power-Up Time The AD9119/AD9129 have a power-down register (Register 0x01) that enables the user to power down various portions of the DAC. The power-up time for several usage cases is shown in Table 14. The recommended way to power up the AD9119/AD9129 is to power up all parts of the circuit with IREF disabled (by setting Register 0x01, Bit 6 = 1b), and then enable IREF by programming Register 0x01, Bit 6 = 0b.

Table 14. Power-Up Times for Several Usage Cases

the current contents of Register 0x00.

• One of the clock controllers has established or lost lock.
• A parity error has occurred.
• A sample error detection status or result is ready.
• The FIFO is nearing an overwrite status. The IRQ output signal is an active low output signal that is available on the IRQ pin (Pin H2). If used, connect the output to VDD via a 10 kΩ pull-up resistor. Each IRQ is enabled by setting the enable bits in Register 0x03 and Register 0x04 that have the same bit mapping as the IRQ status bits in Registers 0x05 and Register 0x06. If an interrupt bit is not enabled, a read request of that bit shows a direct readback of the current state of the source. Thus, a read request of either register shows the current state of all eight interrupts in that register, regardless of whether each individual bit is actually enabled to generate an interrupt. When an interrupt bit is enabled, it captures a rising edge of the interrupt source and holds it, even if the source subsequently returns to its zero state. It is possible, for example, for the retimer lost interrupt enable and retimer lock interrupt enable status bits (Register 0x03[1:0], respectively) to be set when a controller temporarily loses lock but then reestablishes lock before the IRQ is serviced by the host. In such a case, the host should validate the present status of the suspect block by reading back its current status bits. Based on the status of these bits, the host can take appropriate action, if required. The IRQ pin responds only to those interrupts that are enabled. To clear an IRQ, it is necessary to write a 1b to the bit in Register 0x05 or Register 0x06 that caused the interrupt. See Figure 141 for a detailed diagram of the interrupt circuitry. The IRQ can also be used during the AD9119/AD9129 initialization phase after power-up to determine when the retimer PLL and data receiver controllers achieve lock. For example, before enabling the retimer PLL, the retimer lock interrupt enable bit (Register 0x03[0]) can be set, and the IRQ output signal can be monitored to determine when lock is established, before continuing in a similar manner with the data receiver controller. Clear the relevant lock bit, after locking, before continuing to the next controller. When all of the controllers are locked, set the appropriate lost lock enable bits in Register 0x03 to continuously monitor the controllers for loss of lock. R Q D WRITE 1b TO REQUEST BIT IRQ ENABLE SOURCE IRQ REQUEST IRQ ENABLE IRQ ENABLE IRQ PIN OTHER IRQ BITS SINGLE IRQ BIT 11149-144 F igure 141. Interrupt Request Circuitry

Table 15. Interrupt Request Registers

6 FIFO_Warn1 interrupt status Indicates that the FIFO is within one slot of overwrite

5 SPIFrmAck interrupt status Indicates acknowledgement that the SFrmReq bit has changed from 0b to 1b

4 Reserved Reserved

3 DLL warn interrupt status Indicates that the DLL is close to coming unlocked and action is needed

2 DLL lock interrupt status Indicates that the DLL is now locked

1 Retimer lost interrupt status Indicates that the retimer PLL is no longer locked

0 Retimer lock interrupt status Indicates that the retimer PLL is now locked

6 AED pass interrupt status Indicates that the AED logic has captured eight valid samples

5 AED fail interrupt status Indicates that the AED logic has detected a miscompare

4 SED fail interrupt status Indicates that the SED logic has detected a miscompare

3 Parity error falling edge status Indicates a parity fault due to data captured on the falling edge

2 Parity error rising edge status Indicates a parity fault due to data captured on the rising edge

1 Reserved Reserved

0 Reserved Reserved

Rev. B | Page 48 of 66 INTERFACE TIMING VALIDATION The AD9119/AD9129 provide on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored. SAMPLE ERROR DETECTION (SED) OPERATION The SED circuitry operates on a data set made up of eight 11-bit/14-bit input words, denoted as R0L, R1L, R0H, R1H, F0L, F1L, F0H, and F1H. These represent the rising edge and falling edge data of Data Port 0 and Data Port 1. (The AD9119/ AD9129 use both edges of the DCI clock to sample data on each input port.) To properly align the input samples, the rising edge data-words of the data ports (that is, RxL and RxH) are indicated by asserting the FRAME signal for a minimum of two complete input samples. Figure 142 shows the input timing of the interface in word mode. The FRAME signal can be issued once at the start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the RxL and RxH data-words. 11149-249 FRAME P0[7:0] P0[13:8] DCI R0L R0H F0L F0H P1[7:0] P1[13:8] R1L R1H F1L F1H F igure 142. Timing Diagram of FRAME Signal Required to Align Input Data for SED The SED has three flag bits (Register 0x50, Bit 0, Bit 1, and Bit 2) that indicate the results of the input sample comparisons. The SED fail bit (Register 0x50, Bit 0) is set when an error is detected and remains set until cleared. The SED also provides registers that indicate which input data bits experienced errors (Register 0x51 through Register 0x58). These bits are latched and indicate the accumulated errors detected until cleared. To cl ear the SED registers, write 1b to Register 0x50, Bit 6. The autosample error detection (AED) mode is an autoclear mode that has the following two effects:

• AED mode activates the AED fail bit and the AED pass bit (Register 0x50, Bit 1 and Bit 2).
• AED mode changes the behavior of Register 0x51 throug h Re gister 0x58. The compare pass bit is set if the last comparison indicates that the sample is error free. The compare fail bit is set if an error is detected. The compare fail bit is automatically cleared by the reception of eight consecutive error-free comparisons. When autoclear mode is enabled, Register 0x51 through Register 0x58 accumulate errors as previously described but reset to all 0s after eight consecutive error-free sample comparisons are made. The sample error, compare pass, and compare fail flags can be configured to trigger an IRQ when active, if desired. This is accomplished by enabling the appropriate bits in the event flag register (Register 0x06, Bit 4, Bit 5, and Bit 6). SED EXAMPLE Normal Operation The following example illustrates the SED configuration for continuously monitoring the input data and assertion of an IRQ when a single error is detected. 1. Write to the following registers to load the comparison values: a) Register 0x51: SED Patt/Err R0L, Bits[7:0]. b) Register 0x52: SED Patt/Err R0H, Bits[13:8]. c) Register 0x53: SED Patt/Err R1L, Bits[7:0]. d) Register 0x54: SED Patt/Err R1H, Bits[13:8]. e) Register 0x55: SED Patt/Err F0L, Bits[7:0]. f) Register 0x56: SED Patt/Err F0H, Bits[13:8]. g) Register 0x57: SED Patt/Err F1L, Bits[7:0]. h) Register 0x58: SED Patt/Err F1H, Bits[13:8]. i) Comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test. 2. Enable the SED error detect flag to assert the IRQ pin. a) Register 0x04: set to 0x10. 3. Begin transmitting the input data pattern. 4. Write three times to Register 0x50 to enable the SED. a) Register 0x50: set to 0x80. b) Re gister 0x50: set to 0xC0. c) Register 0x50: set to 0x80. If IRQ is asserted, read Register 0x50 and Register 0x51 through Register 0x58 to verify that a SED error is detected and determine which input bits are in error. The bits in Register 0x51 through Register 0x58 are latched. This means that the bits indicate any errors that occur on those bits throughout the test and not just the errors that caused the error detected flag to be set.

Rev. B | Page 50 of 66 CLOCK INPUT The AD9119/AD9129 contain a low jitter, differential clock receiver that is capable of interfacing directly to a differential or single-ended clock source. Because the input is self-biased to a nominal midsupply voltage of 1.25 V with a nominal impedance of 10 kΩ//2 pF , it is recommended that the clock source be ac-coupled to the DACCLK_x input pins with an external differential load of 100 Ω. When the nominal differential input span is 1 V p-p, the clock receiver can operate with a span that ranges from 250 mV p-p to 2.0 V p-p. DACCLK_P TO DAC AND DLL DACCLK_N 1.25V 5kΩ 5kΩ 50kΩ µA DUTY CYCLE RESTORER 11149-150 F igure 147. Clock Input The quality of the clock source, as well as its interface to the AD9119/AD9129 clock input, directly impacts ac performance. Select the phase noise and spur characteristics of the clock source to meet the target application requirements. Phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. It can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 × log10 (fOUT/fCLK) when the DAC clock path contribution is negligible. (The wideband noise is not dominated by the thermal and quantization noise of the DAC.) Figure 148 shows a clock source based on the ADF4350 low phase noise/jitter PLL. The ADF4350 can provide output frequencies from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms. Its squared-up output level can be varied from −4 dBm to +5 dBm, allowing further optimization of the clock drive level. A clock control register exists at Address 0x30. This register can be used to enable automatic duty cycle correction (Bit 1), enable zero-crossing control (Bit 6), and set the zero-crossing point (Bits[5:2]). Recommended settings for this register are listed in the recommended start-up sequence section (see the Start-Up Sequence section). PLL The DACCLK_x input goes to a high frequency PLL to ensure robust locking of the DAC sample clock to the input clock. The PLL is enabled by default such that the PLL locks upon power-up. The PLL (or DAC clock retimer) control registers are located at Register 0x33 and Register 0x34. Register 0x33 enables the user to set the phase detector phase offset level (Bits[7:4]), clear the PLL lost lock status bit (Bit 3), choose the PLL divider for optimum per- formance (Bit 2), and choose the phase detector mode (Bits[1:0]). These settings are determined during product characterization and are given in the recommended start-up sequence (see the Start-Up Sequence section). It is not normally necessary to change these values, nor is the product characterization data valid on any settings other than the recommended ones. Register 0x34 is used to reset the PLL, should that become necessary. At DACCLK = 2.85 GSPS, the lock time is about 10 µs. In most situations, no action is required with the PLL. If the DACCLK is changed and, especially, if it is changed multiple times, as in a frequency hopping application, a phase slip or glitch may be caused by the change in frequency, and it may become necessary to reset the PLL. This can be checked by reading the PLL retimer lost lock bit (Register 0x35, Bit 6). If that is the case, toggle the PLL reset bit by programming Register 0x34, Bit 3, high and then low. In addition, clear the PLL retimer lost lock bit by writing 0b to Register 0x35, Bit 6. PLL lock can be verified by reading the PLL lock bit at Register 0x35, Bit 7. It is possible to use the IRQ registers to set an interrupt for these events. See the Interrupt Requests section for more details. VCOPLL ADF4350 fREF 0.8GHz TO 2.8GHz 1V p-p 2.4nF 2.4nF AD9129 100Ω DACCLK_P DACCLK_N DIV-BY-2N N = 0 – 4 11149-151 F igure 148. Possible Signal Chain for DACCLK_x Input

Rev. B | Page 53 of 66 For applications that operate the AD9119/AD9129 in Mix-Mode with output frequencies extending beyond 2.2 GHz, the user may want to consider the circuit shown in Figure 154. This circuit uses a wideband balun (for example, −3 dB at 4.0 GHz), with a configuration that is similar to the example shown in Figure 152, to provide a dc bias path for the DAC outputs. This circuit was implemented on an evaluation board, and the frequency response was measured to compare it with the ideal curve in Figure 146. The result is shown in Figure 155. 50Ω 50Ω L L MINI-CIRCUITS TCI-1-13M+ TCI-1-33M+IOUTP IOUTN C C VDDA 11149-158 F igure 154. Recommended Mix-Mode Configuration Offering Extended RF Bandwidth Using TC1-1-13M+ Balun –36 –33 –30 –27 –24 –21 –18 –15 –12 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 POWER (dBc) FREQUENCY (MHz) NORMAL MODE MIX-MODE MEASURED NORMAL MEASURED MIX-MODE 11149-257 F igure 155. Measured vs. Ideal DAC Output Response; fDAC = 2.6 GSPS To assist in matching the AD9119/AD9129 output, a Smith chart is provided in Figure 156. The plot was taken using the circuit in Figure 154, with the balun and the coupling capacitors removed, and L = 270 nH. For the measured vs. ideal response of the DAC output, see Figure 155, which illustrates that a nonideal response occurs in the second half of the second Nyquist zone. This area corresponds to the low impedance area between 2 GHz and 3 GHz, as shown in the Smith chart in Figure 156. Output matching can be used to compensate for this nonideal response; the possible reduction in signal bandwidth must be considered if such matching is used. 1. 300kHz 3.1341Ω 710.55mΩ 376.96nH 2. 1GHz 54.333Ω –44.210Ω 3.5999pF 3. 2GHz 13.113Ω –11.207Ω 7.1006pF 4. 3GHz 13.022Ω –14.259Ω 756.48pH 11149-256 F igure 156. Measured Smith Chart Showing the DAC Output Impedance; fDAC = 2.6 GSPS

sequence is listed in Table 16, along with an explanation of the purpose of each step. Table 16. Start-Up Sequence After Power-Up

Table 17. Device Configuration Register Map

Table 18. Bit Descriptions for Mode

7 SDIO_DIR Selects 3-wire or 4-wire mode

1 R/W

6 LSB/MSB LSB/MSB data packing

0 R/W

5 SoftReset 1: performs a software-based reset 0 R/W

4 Reserved Must be set to 0; reserved (short addressing mode) 0 R/W

3 Reserved Mirror Bit 4 for safety 0 R

2 SoftReset Mirror Bit 5 for safety 0 R

1 LSB/MSB Mirror Bit 6 for safety 0 R

0 SDIO_DIR Mirror Bit 7 for safety 1 R

Table 19. Bit Descriptions for Power-Down

7 BG_PD Band gap power-down

6 IREF_PD IREF power-down

5 BIAS_PD Bias power-down

4 Reserved Reserved 0 R/W

3 Reserved Must be set to 1; reserved 1 R/W

2 CLKPATH_PD Clock path power-down

1 Retimer_PD 1: PLL is powered down 0 R/W

0 DLL_PD DLL (data receiver) power-down

Table 20. Bit Descriptions for IRQ Enable 0

7 FIFO_Warn2 interrupt enable Enables the FIFO warning within two slots of overwrite interrupt 0 R/W

6 FIFO_Warn1 interrupt enable Enables the FIFO warning within one slot of overwrite interrupt 0 R/W

5 SPIFrmAck interrupt enable Enables the FIFO SPI-based calibration acknowledgement of SPIFrmReq

4 Reserved Reserved 0 R

2 DLL lock interrupt enable Enables the DLL warning flag that the data receiver is now locked 0 R/W

1 Retimer lost interrupt enable Enables the retimer lost interrupt indication 0 R/W

0 Retimer lock interrupt enable Enables the retimer lock interrupt indication 0 R/W

Table 21. Bit Descriptions for IRQ Enable 1

7 Reserved Reserved 0 R/W

5 AED fail interrupt enable Enables the AED fail interrupt reporting that a miscompare occurred 0 R/W

4 SED fail interrupt enable Enables the SED fail interrupt reporting that a miscompare occurred 0 R/W

1 Reserved Reserved 0 R

0 Reserved Reserved 0 R

Table 22. Bit Descriptions for IRQ Request 0

7 FIFO_Warn2 interrupt status Indicates that the FIFO is within two slots of overwrite 0 R

6 FIFO_Warn1 interrupt status Indicates that the FIFO is within one slot of overwrite 0 R

5 SPIFrmAck interrupt status Indicates acknowledgement of SPIFrmReq has changed from 0b to1b 0 R

2 DLL lock interrupt status Indicates that the DLL (data receiver) is now locked 0 R

1 Retimer lost interrupt status Indicates that the retimer PLL is no longer locked 0 R

0 Retimer lock interrupt status Indicates that the retimer PLL is now locked 0 R

Table 23. Bit Descriptions for IRQ Request 1

6 AED pass interrupt status Indicates that the AED logic has captured eight valid samples 0 R/W

5 AED fail interrupt status Indicates that the AED logic has detected a miscompare 0 R/W

4 SED fail interrupt status Indicates that the SED logic has detected a miscompare 0 R/W

1 Reserved Reserved 0 R/W

0 Reserved Reserved 0 R/W

Table 24. Bit Descriptions for Frame Pin Usage

6 Reserved Reserved 0 R/W

5 ParUsage 1: FRM_x pin is in parity mode, and parity is enabled

4 FrmUsage 1: FRM_x pin is in frame mode and enable pin framing (Register 0x11[5] = 1b) is

3 Reserved Reserved 0 R

2 Reserved Reserved 0 R

Table 25. Bit Descriptions for Reserved_0 Table 26. Bit Descriptions for Data Ctrl 0

7 DLL enable 1: enables DLL

6 Duty cycle correction enable 1: enables duty cycle correction

5 Reserved Reserved 0 R/W

Table 27. Bit Descriptions for Data Ctrl 1

7 Warn clear 1: clears data receiver warning bit 0 R/W

6 Lock delay divider 1: long delay

Table 28. Bit Descriptions for Data Ctrl 2

6 DCO enable 1: enables DCO output driver 0 R/W

Table 29. Bit Descriptions for Data Ctrl 3 [2:1] Duty correction BW set Sets the bandwidth of the duty cycle correction circuit. Table 30. Bit Descriptions for Data Status 0

7 DLL lock 1: DLL lock 0 R

6 DLL warning 1: DLL near beginning/end of delay line 0 R

5 DLL delay line start warning 1: DLL at beginning of delay line 0 R

4 DLL delay line end warning 1: DLL at end of delay line 0 R

3 DLL correct phase 1: data is sampled on correct phase

0: data is sampled on incorrect phase.

2 DCI on 1: user has provided a clock > 100 MHz 0 R

1 DLL lock phase 1: DLL is locked on negative half of DCI.

0 DLL running 1: closed loop DLL attempting to lock

Table 31. Bit Descriptions for FIFO Ctrl

7 SPIFrmReq Requests a SPI-based FIFO alignment (FIFO reset) 0 R/W

6 SPIFrmAck Acknowledges SPIFrmReq change (tracks SPIFrmReq setting) 0 R/W

5 Enable pin framing 1: enables hardware pin-based FIFO framing 0 R/W

0 Phase report enable 1: enables FIFO phase reporting 0 R/W

Table 32. Bit Descriptions for FIFO Offset

7 Reserved Reserved 0 R

Table 33. Bit Descriptions for FIFO PH0 THRM to 1111111b, where 0000011b is considered the middle of the FIFO storage space. Table 34. Bit Descriptions for FIFO PH1 THRM to 1111111b, where 0000011b is considered the middle of the FIFO storage space. Table 35. Bit Descriptions for FIFO PH2 THRM to 1111111b, where 0000011b is considered the middle of the FIFO storage space. Table 36. Bit Descriptions for FIFO PH3 THRM to 1111111b, where 0000011b is considered the middle of the FIFO storage space.

Table 37. Bit Descriptions for Data Mode Ctrl

7 Filter enable 1: enables 2× interpolation filter

6 Binary select Selects input data format

5 FILT_SEL 2× interpolator filter select

Table 38. Bit Descriptions for Decode Ctrl

0 Mix-Mode enable 1: Mix-Mode

Table 39. Bit Descriptions for Sync

7 Inc latency Increment delay by 1 0 R/W

6 Dec latency Decrement delay by 1 0 R/W

5 Reserved Reserved 0 R

4 Sync enable 1: multi-DAC sync output pin enabled

3 Sync done 1: last increment or decrement request is complete 0 R

Table 40. Bit Descriptions for FSC_1 Table 41. Bit Descriptions for FSC_2

Table 42. Bit Descriptions for ANA_CNT1 Table 43. Bit Descriptions for ANA_CNT2 Table 44. Bit Descriptions for CLK REG1

7 Reserved Must be set to 0; reserved 0 R/W

6 Cross enable Enables zero-crossing control 0 R/W

1 Duty enable Enables duty cycle correction 0 R/W

0 Select internal Must be set to 0 0 R/W

Table 45. Bit Descriptions for Retime Ctrl 0

3 Clear lost Clear lost status bit 0

2 PLL divider 1: divide-by-4

Table 46. Bit Descriptions for Retimer Ctrl 1

3 PLL reset_Z 1: normal operation for DAC clock PLL

Table 47. Bit Descriptions for Retimer Stat 0

7 PLL lock 1: retimer PLL locked 0 R

6 PLL lost 1: retimer PLL lost (can be sticky) 0 R

Table 48. Bit Descriptions for SED Control

7 SED enable 1: setting this bit to 1 enables the SED compare logic 0 R/W

6 SED error clear 1: clears all SED reported error bits below 0 R/W

5 AED enable 1: enables the AED function (SED with autoclear after eight passing sets) 0 R/W

4 Reserved Must be set to 0; reserved 0 R

3 Reserved Must be set to 0; reserved 0 R

2 AED pass 1: signals eight true compare cycles 0 R/W

1 AED fail 1: signals a miscompare 0 R

0 SED fail 1: signals an SED miscompare (with SED or AED enabled) 0 R

Table 49. Bit Descriptions for SED Patt/Err R0L Table 50. Bit Descriptions for SED Patt/Err R0H Table 51. Bit Descriptions for SED Patt/Err R1L Table 52. Bit Descriptions for SED Patt/Err R1H

Table 53. Bit Descriptions for SED Patt/Err F0L Table 54. Bit Descriptions for SED Patt/Err F0H Table 55. Bit Descriptions for SED Patt/Err F1L Table 56. Bit Descriptions for SED Patt/Err F1H Table 57. Bit Descriptions for Parity Control

7 Parity enable 1: enables parity 0x00 R/W

Note that the parity bit must be enabled in Register 0x07.

5 Parity error clear 1: clears parity error counters 0 R/W

1 Parity error falling edge 1: signals detection of a falling edge parity error 0 R

0 Parity error rising edge 1: signals detection of a rising edge parity error 0 R

Table 58. Bit Descriptions for Parity Err Rising

Table 59. Bit Descriptions for Parity Err Falling Table 60. Bit Descriptions for Delay Ctrl 0 Table 61. Bit Descriptions for Delay Ctrl 1 Table 62. Bit Descriptions for Drive Strength Table 63. Bit Descriptions for Part ID

Rev. B | Page 66 of 66 OUTLINE DIMENSIONS 12.10 12.00 SQ 11.90

0.43 MAX

0.25 MIN

1.00 MAX

0.85 MIN

A B C D E F G H J K L M N P 1413121110 8 7 6 3 2 19 5 4

1.40 MAX

0.55 0.50 0.45 10.40 BSC SQ 11-18-2011-ACOMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1. COPLANARITY 0.12 BALL DIAMETER 0.80 BSC DETAIL A A1 BALL CORNERA1 BALL CORNER DETAIL A BOTTOM VIEWTOP VIEW SEATING PLANE Fig ure 157. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-160-1) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9119BBCZ −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9119BBCZRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9119-EBZ Evaluation Board for Normal Mode Evaluation AD9119-MIX-EBZ Evaluation Board for Mix-Mode Evaluation AD9119-CBLTX-EBZ Evaluation Board for Cable Transmitter Evaluation AD9129BBCZ −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9129BBCZRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9129BBC −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9129BBCRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9129-EBZ Evaluation Board for Normal Mode Evaluation AD9129-MIX-EBZ Evaluation Board for Mix-Mode Evaluation AD9129-CBLTX-EBZ Evaluation Board for Cable Transmitter Evaluation 1 Z = RoHS Compliant Part. ©2013-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11149-0-6/17(B)