AD9117-DPG2-EBZ

AD9114_17 AD | Alldatasheet

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Dual Low Power, 8-/10-/12-/14-Bit TxDAC Digital-to-Analog Converters Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2008–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Power dissipation @ 3.3 V, 20 mA output 191 mW @ 10 MSPS 232 mW @ 125 MSPS Sleep mode: <3 mW @ 3.3 V Supply voltage: 1.8 V to 3.3 V SFDR to Nyquist 86 dBc @ 1 MHz output 85 dBc @ 10 MHz output AD9117 NSD @ 1 MHz output, 125 MSPS, 20 mA: −162 dBc/Hz Differential current outputs: 2 mA to 20 mA 2 on-chip auxiliary DACs CMOS inputs with single-port operation Output common mode: adjustable 0 V to 1.2 V Small footprint 40-lead LFCSP RoHS-compliant package

APPLICATIONS

Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators GENERAL DESCRIPTION The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC® converters are optimized for the transmit signal path of commu- nication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications. PRODUCT HIGHLIGHTS 1. Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 225 mW at 100 MSPS. Sleep and power-down modes are provided for low power idle periods. 2. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. 3. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows for easy interfacing to other components that accept common-mode levels greater than 0 V .

AD9114/AD9115/AD9116/AD9117 Data Sheet Rev. D | Page 2 of 52 TABLE OF CONTENTS Correcting for Nonideal Performance of Quadrature

AD9114/AD9115/AD9116/AD9117 Data Sheet Rev. D | Page 4 of 52 FUNCTIONAL BLOCK DIAGRAM I DAC Q DAC AUX1DAC AUX2DAC BAND GAP CLOCK DIST 10kΩ QRSET 2kΩ IRSET 2kΩ IREF 100µA IRCM 60Ω TO 260Ω QRCM 60Ω TO 260Ω 62.5Ω 62.5Ω 62.5Ω 62.5Ω SPI INTERFACE

1 INTO 2

Q DATA1.8V LDO 1V AD9117 RLIN IOUTN IOUTP RLIP AVDD AVSS RLQP QOUTP QOUTN RLQN DB11 DB10 DB9 DB8 DVDDIO DVSS DVDD DB7 DB6 DB5 DB12 DB13 (MSB) CS/PWRDN SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJQ/AUXQ FSADJI/AUXI CMLI DB4 DB3 DB2 DB1 (LSB) DB0 DCLKIO CVDD CLKIN CVSS CMLQ 07466-001 Figure 1.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 5 of 52 SPECIFICATIONS DC SPECIFICATIONS Table 1. Parameter AD9114 AD9115 AD9116 AD9117 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max RESOLUTION 8 10 12 14 Bits ACCURACY, AVDD = DVDDIO = CVDD = 3.3 V Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.06 ±0.4 ±1.4 LSB Postcalibration ±0.02 ±0.04 ±0.2 ±0.6 LSB Integral Nonlinearity (INL) Precalibration ±0.03 ±0.19 ±0.68 ±1.2 LSB Postcalibration ±0.03 ±0.07 ±0.42 ±0.6 LSB ACCURACY, AVDD = DVDDIO =CVDD = 1.8 V Differential Nonlinearity (DNL) Precalibration ±0.02 ±0.08 ±0.5 ±1.8 LSB Postcalibration ±0.01 ±0.06 ±0.2 ±1.0 LSB Integral Nonlinearity (INL) Precalibration ±0.04 ±0.2 ±0.5 ±1.8 LSB Postcalibration ±0.02 ±0.1 ±0.3 ±1.1 LSB MAIN DAC OUTPUTS Offset Error −1 +1 −1 +1 −1 +1 −1 +1 mV Gain Error Internal Reference −2 +2 −2 +2 −2 +2 −2 +2 % of FSR Full-Scale Output Current1 AVDD = 3.3 V 2 8 20 2 8 20 2 8 20 2 8 20 mA AVDD = 1.8 V 2 8 2 8 2 8 2 8 mA Output Common-Mode Level (8 mA CMLx Pin) Output Compliance Range AVDD = 3.3 V, 8 mA Output Output Resistance 200 200 200 200 MΩ Crosstalk, Q DAC to I DAC (fOUT = 30 MHz) 95 95 95 95 dB Crosstalk, Q DAC to I DAC (fOUT = 60 MHz) 76 76 76 76 dB MAIN DAC TEMPERATURE DRIFT Offset 0 0 0 0 ppm/°C Gain ± 40 ± 40 ± 40 ±40 ppm/°C Reference Voltage ± 25 ± 25 ± 25 ± 25 ppm/°C

AD9114/AD9115/AD9116/AD9117 Data Sheet Rev. D | Page 6 of 52 Parameter AD9114 AD9115 AD9116 AD9117 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max AUXDAC OUTPUTS Resolution 10 10 10 10 Bits Full-Scale Output Current (Current Sourcing Mode) 125 125 125 125 µA Voltage Output Mode Output Compliance Range (Sourcing 1 mA) VSS VDD − 0.25 VSS VDD − 0.25 VSS VDD − 0.25 VSS VDD − 0.25 V Output Compliance Range (Sinking 1 mA) VSS + 0.25 V DD VSS + 0.25 V DD VSS + 0.25 V DD VSS + 0.25 V DD V Output Resistance in Current Output Mode AVSS to 1 V 1 1 1 1 MΩ AUXDAC Monotonicity Guaranteed 10 10 10 10 Bits REFERENCE OUTPUT Output Resistance 10 10 10 10 kΩ REFERENCE INPUT Voltage Compliance Input Resistance External Reference Mode 1 1 1 1 MΩ DAC MATCHING Gain Matching −1 +1 −1 +1 −1 +1 −1 +1 % of FSR ANALOG SUPPLY VOLTAGES DIGITAL SUPPLY VOLTAGES POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 3.3 V fDAC = 125 MSPS, IF = 12.5 MHz 220 220 220 220 mW IAVDD 55 55 55 55 mA IDVDD + IDVDDIO 10 10 10 10 mA ICVDD 3 3 3 3 mA Power-Down Mode with Clock 8.5 8.5 8.5 8.5 mW Power-Down Mode No Clock 3 3 3 3 mW Power Supply Rejection Ratio −0.009 −0.009 −0.009 −0.009 % FSR/V POWER CONSUMPTION, AVDD = DVDDIO = CVDD = 1.8 V fDAC = 125 MSPS, IF = 12.5 MHz 58 58 58 58 mW IAVDD 24 24 24 24 mA IDVDD + IDVDDIO 8 8 8 8 mA ICVDD 2 2 2 2 mA Power-Down Mode with Clock 12 12 12 12 mW Power-Down Mode No Clock 850 850 850 850 µW Power Supply Rejection Ratio − 0.007 −0.007 −0.007 −0.007 % FSR/V OPERATING RANGE − 40 +25 +85 − 40 +25 +85 − 40 +25 +85 − 40 +25 +85 °C 1 Based on a 1.6 kΩ external resistor for 20 mA full-scale current.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 7 of 52 DIGITAL SPECIFICATIONS Table 2. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKIN) VIH 2.1 3 V VIL 0 0.9 V Maximum Clock Rate 125 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 25 MHz Minimum Pulse Width High 20 ns Minimum Pulse Width Low 20 ns Minimum SDIO and to SCLK Setup, tDS 10 ns Minimum SCLK to SDIO Hold, tDH 5 ns Maximum SCLK to Valid SDIO, tDV 20 ns Minimum SCLK to Invalid SDIO, tDNV 5 ns INPUT DATA

1.8 V Q Channel or DCLKIO Falling Edge

Setup 0.25 ns Hold 1.2 ns

1.8 V I Channel or DCLKIO Rising Edge

Setup 0.13 ns Hold 1.1 ns

3.3 V Q Channel or DCLKIO Falling Edge

Setup − 0.2 ns Hold 1.5 ns

3.3 V I Channel or DCLKIO Rising Edge

Setup − 0.2 ns Hold 1.6 ns DVDDIO = 3.3 V VIH 2.1 3 V VIL 0 0.9 V DVDDIO = 1.8 V VIH 1.2 1.8 V VIL 0 0.5 V

AD9114/AD9115/AD9116/AD9117 Data Sheet Rev. D | Page 8 of 52 AC SPECIFICATIONS Table 3. Parameter AD9114 AD9115 AD9116 AD9117 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max DYNAMIC PERFORMANCE Output Rise Time (10% to 90%) 0.27 0.27 0.27 0.27 ns Output Fall Time (90% to 10%) 0.27 0.27 0.27 0.27 ns Output Noise (IOUTFS = 20mA) 1471 465 117 37 pA/√Hz SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz 76 85 85 85 dBc fDAC = 125 MSPS, fOUT = 50 MHz 55 55 55 55 dBc TWO TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz 81 81 81 82 dBc fDAC = 125 MSPS, fOUT = 50 MHz 60 60 60 61 dBc NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 1 MHz −131 −141 −153 −163 dBc/Hz fDAC = 125 MSPS, fOUT = 10 MHz −132 −143 −153 −157 dBc/Hz fDAC = 125 MSPS, fOUT = 50 MHz −128 −138 −146 −149 dBc/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz −78 −78 −78 − 78 dBc fDAC = 122.88 MSPS, fOUT = 30 MHz −80 −80 −80 −80 dBc Table 4. Parameter AD9114 AD9115 AD9116 AD9117 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 125 MSPS, fOUT = 10 MHz 73 76 76 76 dBc fDAC = 125 MSPS, fOUT = 50 MHz 48 48 48 48 dBc TWO TONE INTERMODULATION DISTORTION (IMD) fDAC = 125 MSPS, fOUT = 10 MHz 76 76 76 76 dBc fDAC = 125 MSPS, fOUT = 50 MHz 50 50 50 50 dBc NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING fDAC = 125 MSPS, fOUT = 1 MHz − 131 − 143 − 152 − 158 dBc/Hz fDAC = 125 MSPS, fOUT = 10 MHz −132 −143 −151 −152 dBc/Hz fDAC = 125 MSPS, fOUT = 50 MHz −128 −138 −140 −141 dBc/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 61.44 MSPS, fOUT = 20 MHz −69 −69 −69 −69 dBc fDAC = 122.88 MSPS, fOUT = 30 MHz − 72 − 72 − 72 − 72 dBc

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 9 of 52 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS −0.3 V to +3.9 V DVDD to DVSS −0.3 V to +2.1 V AVSS to DVSS, CVSS −0.3 V to +0.3 V DVSS to AVSS, CVSS −0.3 V to +0.3 V CVSS to AVSS, DVSS − 0.3 V to +0.3 V REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS −0.3 V to AVDD + 0.3 V QOUTP , QOUTN, IOUTP , IOUTN, RLQP , RLQN, RLIP , RLIN to AVSS −1.0 V to AVDD + 0.3 V DBn1 (MSB) to D0 (LSB), CS, SCLK, SDIO, RESET to DVSS −0.3 V to DVDDIO + 0.3 V CLKIN to CVSS − 0.3 V to CVDD + 0.3 V Junction Temperature 125°C Storage Temperature Range − 65°C to +150°C 1 n stands for 7 for the AD9114, 9 for the AD9115, 11 for the AD9116, and 13 for the AD9117. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Table 6. 40-Lead LFCSP (with No Airflow Movement) 29.8 19.0 3.4 °C/W

1 These calculations are intended to represent the thermal performance of the

indicated packages using a JEDEC multilayer test board. Do not assume the same level of thermal performance in actual applications without a careful inspection of the conditions in the application to determine that they are similar to those assumed in these calculations. ESD CAUTION

THE EXPOSED PAD IS CONNECTED TO AVSS AND

MUST BE SOLDERED TO THE GROUND PLANE. Figure 2. AD9114 Pin Configuration Table 7. AD9114 Pin Function Descriptions 1 to 4 DB[5:2] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.

8 DB1 Digital Inputs

9 DB0 (LSB) Digital Input (LSB). NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V). 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 11 of 52 Pin No. Mnemonic Description 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s. 30 RLIN Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally. 31 CMLI I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. 33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output. 34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required). 35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer, see the Retimer section. 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB7 (MSB) Digital Input (MSB). 40 DB6 Digital Input. EP (EPAD) The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad.

23 QOUTP

24 RLQP

25 AVSS

26 AVDD

27 RLIP

28 IOUTP

29 IOUTN

30 RLIN

22 QOUTN

21 RLQN11

THE EXPOSED PAD IS CONNECTED TO AVSS AND

MUST BE SOLDERED TO THE GROUND PLANE. Figure 3. AD9115 Pin Configuration Table 8. AD9115 Pin Function Description 1 to 4 DB[7:4] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 10 DB[3:1] Digital Inputs. 11 DB0 (LSB) Digital Input (LSB). 12 to 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 22 QOUTN Complementary Q DAC Current Output. Full-scal e current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V). 28 IOUTP I DAC Current Output. Full-scale curren t is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scal e current is sourced when all data bits are 0s.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 13 of 52 Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full- scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current . Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. 33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output. 34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required). 35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section. 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB9 (MSB) Digital Input (MSB). 40 DB82 Digital Input. EP (EPAD) The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad.

24 RLQ P

27 RLI P

21 RLQN

THE EXPOSED PAD IS CONNECTED TO AVSS AND

MUST BE SOLDERED TO THE GROUND PLANE. Figure 4. AD9116 Pin Configuration Table 9. AD9116 Pin Function Descriptions 1 to 4 DB[9:6] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 12 DB[5:1] Digital Inputs. 13 DB0 (LSB) Digital Input (LSB). 14, 15 NC No Connect. These pins are not connected to the chip. 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 22 QOUTN Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V). 28 IOUTP I DAC Current Output. Full-scale current is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 15 of 52 Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full- scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current . Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. 33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output. 34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required). 35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section. 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB11 (MSB) Digital Input (MSB). 40 DB10 Digital Input. EP (EPAD) The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad.

THE EXPOSED PAD IS CONNECTED TO AVSS AND

MUST BE SOLDERED TO THE GROUND PLANE. Figure 5. AD9117 Pin Configuration Table 10. AD9117 Pin Function Descriptions 1 to 4 DB[11:8] Digital Inputs. 5 DVDDIO Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal). with a 1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads. 8 to 14 DB[7:1] Digital Inputs. 15 DB0 (LSB) Digital Input (LSB). 16 DCLKIO Data Input/Output Clock. Clock used to qualify input data. 17 CVDD Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD. 18 CLKIN LVCMOS Sampling Clock Input. 19 CVSS Sampling Clock Supply Voltage Common. see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 22 QOUTN Complementary Q DAC Current Output. Full-scal e current is sourced when all data bits are 0s. 23 QOUTP Q DAC Current Output. Full-scale current is sourced when all data bits are 1s. 26 AVDD Analog Supply Voltage Input (1.8 V to 3.3 V). 28 IOUTP I DAC Current Output. Full-scale curren t is sourced when all data bits are 1s. 29 IOUTN Complementary I DAC Current Output. Full-scal e current is sourced when all data bits are 0s.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 17 of 52 Pin No. Mnemonic Description 31 CMLI I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 Ω. 32 FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full- scale current output adjust for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current . Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output. 33 FSADJI/AUXI Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is 4 kΩ for 8 mA output current. Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output. 34 REFIO Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in internal reference mode (a 0.1 µF capacitor to AVSS is required). 35 RESET/PINMD This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset the SPI registers to their default values. A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD). 36 SCLK/CLKMD Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port. Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section. 37 SDIO/FORMAT Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port. Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format. 38 CS/PWRDN Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port. 39 DB13 (MSB) Digital Input (MSB). 40 DB12 Digital Input. EP (EPAD) The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected to this pad.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 31 of 52 TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTP, the 0 mA output is expected when the inputs are all 0. For IOUTN, the 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and the ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient value (25°C) to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full- scale range per degree Celsius (ppm FSR/°C). For reference drift, the drift is reported in parts per million per degree Celsius (ppm/°C). Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage (%) or in decibels (dB). Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels (dB). Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Figure 84. Simplified Block Diagram output impedance of the main DACs (that is, >200 MΩ). differential current switches. capacitor at DVDD (Pin 7) is required when using the LDO. reference, and a reference control amplifier. resistor, xRSET, connected to its full-scale adjust pin (FSADJx). proper scaling factor. The full-scale current, IxOUTFS, is 32 × IxREF. 4 mA IxOUTFS, respectively).

instruction byte into the AD9114/AD9115/AD9116/AD9117. or a data transfer cycle, none of the present data is written. upon writing to the last bit of each transfer byte. The instruction byte contains the information shown in Table 11. indicates a read operation. Logic 0 indicates a write operation. number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 12. Table 12. Byte Transfer Count edges line up in the middle of the data in the data transfer cycle. the entire communication cycle.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 35 of 52 SPI REGISTER MAP Table 13. Name Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPI Control 0x00 0x00 Reserved LSBFIRST Reset LNGINS Reserved Power-Down 0x01 0x40 LDOOFF LDOSTAT PWRDN Q DACOFF I DACOFF QCLKOFF ICLKOFF EXTREF Data Control 0x02 0x34 TWOS Reserved IFIRST IRISING SIMULBIT DCI_EN DCOSGL DCODBL I DAC Gain 0x03 0x00 Reserved I DACGAIN[5:0] IRSET 0x04 0x00 IRSETEN Reserved IRSET[5:0] IRCML 0x05 0x00 IRCMLEN Reserved IRCML[5:0] Q DAC Gain 0x06 0x00 Reserved Q DACGAIN[5:0] QRSET 0x07 0x00 QRSETEN Reserved QRSET[5:0] QRCML 0x08 0x00 QRCMLEN Reserved QRCML[5:0] AUXDAC Q 0x09 0x00 QAUXDAC[7:0] AUX CTLQ 0x0A 0x00 QAUXEN QAUXRNG[1:0] QAUXOFS[2:0] QAUXDAC[9:8] AUXDAC I 0x0B 0x00 IAUXDAC[7:0] AUX CTLI 0x0C 0x00 IAUXEN IAUXRNG[1:0] IAUXOFS[2:0] IAUXDAC[9:8] Reference Resistor 0x0D 0x00 Reserved RREF[5:0] Cal Control 0x0E 0x00 PRELDQ PRELDI CALSELQ CALSELI CALCLK DIVSEL[2:0] Cal Memory 0x0F 0x00 CALSTATQ CALSTATI Reserved CALMEMQ[1:0] CALMEMI[1:0] Memory Address 0x10 0x00 Reserved MEMADDR[5:0] Memory Data 0x11 0x34 Reserved MEMDATA[5:0] Memory R/W 0x12 0x00 CALRSTQ CALRSTI CALEN SMEMWR SMEMRD UNCALQ UNCALI CLKMODE 0x14 0x00 CLKMODEQ[1:0] Searching Reacquire CLKMODEN CLKMODEI[1:0] Version 0x1F 0x0A Version[7:0]

AD9114/AD9115/AD9116/AD9117 Data Sheet Rev. D | Page 36 of 52 SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 14. Register Address Bit Name Description SPI Control 0x00 6 LSBFIRST 0 (default): MSB first per SPI standard. 1: LSB first per SPI standard. Note that the user must always change the LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors.

5 Reset Executes software reset of SPI and controllers, reloads default register values,

except Register 0x00. 1: s et software reset; write 0 on the next (or any following) cycle to release reset. 4 LNGINS 0 (default): the SPI instruction word uses a 5-bit address. 1: t he SPI instruction word uses a 13-bit address. Power Down 0x01 7 LDOOFF 0 (default): LDO voltage regulator on. 1: turns core LDO voltage regulator off. 6 LDOSTAT 0: indicates that the core LDO voltage regulator is off. 1 (default): indicates that the core LDO voltage regulator is on. 5 PWRDN 0 (default): all analog, digital circuitry and SPI logic are powered on. 1: powers down all analog and digital circuitry, except for SPI logic. 4 Q DACOFF 0 (default): turns on Q DAC output current. 1: turns off Q DAC output current. 3 I DACOFF 0 (default): turns on I DAC output current. 1: turns off I DAC output current. 2 QCLKOFF 0 (default): turns on Q DAC clock. 1: turns off Q DAC clock. 1 ICLKOFF 0 (default): turns on I DAC clock. 1: turns off I DAC clock. 0 EXTREF 0 (default): turns on internal voltage reference. 1: powers down the internal voltage reference (external reference required). Data Control 0x02 7 TWOS 0 (default): Unsigned binary input data format. 1: twos complement input data format. 5 IFIRST 0: pairing of data— Q first of pair on data input pads. 1(default): pairing of data— I first of pair on data input pads (default). 4 IRISING 0: Q data latched on DCLKIO rising edge. 1 (default): I data latched on DCLKIO rising edge (default). 3 SIMULBIT 0 (default): allows simultaneous input and output enable on DCLKIO. 1: disallows simultaneous input and output enable on DCLKIO. 2 DCI_EN Controls the use of the DCLKIO pad for the data clock input. 0: data clock input disabled. 1 (default): data clock input enabled. 1 DCOSGL Controls the use of the DCLKIO pad for the data clock output. 0 (default): data clock output disabled. 1: data clock output enabled; regular strength driver. 0 DCODBL Controls the use of the DCLKIO pad for the data clock output. 0 (default): DCODBL data clock output disabled. 1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive current. I DAC Gain 0x03 5:0 I DACGAIN[5:0] DAC I fine gain adjustment; alters the full-scale current, as shown in Figure 99. Default IDACGAIN = 0x00.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 37 of 52 Register Address Bit Name Description IRSET 0x04 7 IRSETEN 0 (default): IRSET resistor value for I channel is set by an external resistor connected to the FADJI/AUXI pin. Nominal value for this external resistor is 4 kΩ . 1: enables the on-chip IRSET value to be changed for I channel. 5:0 IRSET[5:0] Changes the value of the on-chip IRSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps twos complement (nonlinear), see Figure 98. 000000 (default): IRSET = 2 kΩ. 011111: IRSET = 8 kΩ . 100000: IRSET = 1.6 kΩ . 111111: IRSET = 2 kΩ . IRCML 0x05 7 IRCMLEN 0 (default): IRCML resistor value for the I channel is set by an external resistor connected to CMLI pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip IRCML adjustment for I channel. 5:0 IRCML[5:0] Changes the value of the on-chip IRCML resistor for I channel; this adjusts the common-mode level of the DAC output stage. 000000 (default): IRCML = 60 Ω. 100000: IRCML = 160 Ω. 111111: IRCML = 260 Ω. Q DAC Gain 0x06 5:0 Q DACGAIN[5:0] DAC Q fine gain adjustment; alters the full-scale current, as shown in Figure 99. Default QDACGAIN = 0x00. QRSET 0x07 7 QRSETEN 0 (default): QRSET resistor value for Q channel is set by an external resistor connected to FADJI/AUXI pin. Nominal value for this external resistor is 4 kΩ. 1: enables on-chip QRSET adjustment for Q channel. 5:0 QRSET[5:0] Changes the value of the on-chip QRSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps twos complement (nonlinear). 000000 (default): QRSET = 2 kΩ. 011111: QRSET = 8 kΩ. 100000: QRSET = 1.6 kΩ. 111111: QRSET = 2 kΩ. QRCML 0x08 7 QRCMLEN 0 (default): QRCML resistor value for the Q channel is set by an external resistor connected to CMLQ pin. Recommended value for this external resistor is 0 Ω. 1: enables on-chip QRCML adjustment. 5:0 QRCML[5:0] Changes the value of the on-chip QRCML resistor for Q channel; this adjusts the common-mode level of the DAC output stage. 000000 (default): QRCML = 60 Ω. 100000: QRCML = 160 Ω. 111111: QRCML = 260 Ω . AUXDAC Q 0x09 7:0 QAUXDAC[7:0] AUXDAC Q output voltage adjustment word LSBs. 0x3FF: sets AUXDAC Q output to full scale. 0x200: sets AUXDAC Q output to midscale. 0x000 (default): sets AUXDAC Q output to bottom of scale. AUX CTLQ 0x0A 7 QAUXEN 0 (default): AUXDAC Q output disabled. 1: enables AUXDAC Q output. 6:5 QAUXRNG[1:0] 00 (default): sets AUXDAC Q output voltage range to 2 V. 01: sets AUXDAC Q output voltage range to 1.5 V. 10: sets AUXDAC Q output voltage range to 1.0 V. 11: sets AUXDAC Q output voltage range to 0.5 V. 4:2 QAUXOFS[2:0] 000 (default): sets AUXDAC Q top of range to 1.0 V. 001: sets AUXDAC Q top of range to 1.5 V. 010: sets AUXDAC Q top of range to 2.0 V. 011: sets AUXDAC Q top of range to 2.5 V. 100: sets AUXDAC Q top of range to 2.9 V. 1:0 QAUXDAC[9:8] AUXDAC Q output voltage adjustment word MSBs (default = 00).

AD9114/AD9115/AD9116/AD9117 Data Sheet Rev. D | Page 38 of 52 Register Address Bit Name Description AUXDAC I 0x0B 7:0 IAUXDAC[7:0] AUXDAC I output voltage adjustment word LSBs. 0x3FF: sets AUXDAC I output to full scale. 0x200: sets AUXDAC I output to midscale. 0x000 (default): sets AUXDAC I output to bottom of scale. AUX CTLI 0x0C 7 IAUXEN 0 (default): AUXDAC I output disabled. 1: enables AUXDAC I output. 6:5 IAUXRNG[1:0] 00 (default): sets AUXDAC I output voltage range to 2 V. 01: sets AUXDAC I output voltage range to 1.5 V. 10: sets AUXDAC I output voltage range to 1.0 V. 11: sets AUXDAC I output voltage range to 0.5 V. 4:2 IAUXOFS[2:0] 000 (default): sets AUXDAC I top of range to 1.0 V. 001: sets AUXDAC I top of range to 1.5 V. 010: sets AUXDAC I top of range to 2.0 V. 011: sets AUXDAC I top of range to 2.5 V. 100: sets AUXDAC I top of range to 2.9 V. 1:0 IAUXDAC[9:8] AUX DAC I output voltage adjustment word MSBs (default = 00). Reference Resistor 0x0D 5:0 RREF[5:0] Permits an adjustment of the on-chip reference voltage and output at REFIO (see Figure 97) twos complement. 000000 (default): sets the value of RREF to 10 kΩ, V REF = 1.0 V. 011111: sets the value of RREF to 12 kΩ, V REF = 1.2 V. 100000: sets the value of RREF to 8 kΩ, V REF = 0.8 V. 111111: sets the value of RREF to 10 kΩ, V REF = 1.0 V. Cal Control 0x0E 7 PRELDQ 0 (default): preloads Q DAC calibration reference set to 32. 1: preloads Q DAC calibration reference set by user (Cal Address 1). 6 PRELDI 0 (default): preloads I DAC calibration reference set to 32. 1: preloads I DAC calibration reference set by user (Cal Address 1). 5 CALSELQ 0 (default): Q DAC self-calibration done. 1: selects Q DAC self-calibration. 4 CALSELI 0 (default): I DAC self-calibration done. 1: selects I DAC self-calibration. 3 CALCLK 0 (default): calibration clock disabled. 1: calibrates clock enabled. 2:0 DIVSEL[2:0] Calibration clock divide ratio from DAC clock rate. 000 (default): divide by 256. 001: divide by 128. 110: divide by 4. 111: divide by 2. Cal Memory 0x0F 7 CALSTATQ 0 (default): Q DAC calibration in progress. 1: calibration of Q DAC complete. 6 CALSTATI 0 (default): I DAC calibration in progress. 1: calibration of I DAC complete. 3:2 CALMEMQ[1:0] Status of Q DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user-calibrated. 1:0 CALMEMI[1:0] Status of I DAC calibration memory. 00 (default): uncalibrated. 01: self-calibrated. 10: user-calibrated. Memory Address 0x10 5:0 MEMADDR[5:0] Address of static memory to be accessed. Memory Data 0x11 5:0 MEMDATA[5:0] Data for static memory access.

Data Sheet AD9114/AD9115/AD9116/AD9117 Rev. D | Page 39 of 52 Register Address Bit Name Description Memory R/W 0x12 7 CALRSTQ 0 (default): no action. 1: clears CALSTATQ. 6 CALRSTI 0 (default): no action. 1: clears CALSTATI. 4 CALEN 0 (default): no action. 1: initiates device self-calibration. 3 SMEMWR 0 (default): no action. 1: writes to static memory (calibration coefficients). 2 SMEMRD 0 (default): no action. 1: reads from static memory (calibration coefficients). 1 UNCALQ 0 (default): no action. 1: resets Q DAC calibration coefficients to default (uncalibrated). 0 UNCALI 0 (default): no action. 1: resets I DAC calibration coefficients to default (uncalibrated). CLKMODE 0x14 7:6 CLKMODEQ[1:0] Depending on CLKMODEN bit setting, these two bits reflect the phase relationship between DCLKIO and CLKIN, as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retime. If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if needed to better synchronize the DACs (see the Retimer section). 4 Searching Datapath retimer status bit. 0 (default): clock relationship established. 1: indicates that the internal datapath retimer is searching for clock relationship (device output is not usable while this bit is high). 3 Reacquire Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.

2 CLKMODEN 0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read

back in CLKMODEI[1:0] and CLKMODEQ[1:0]. 1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers. 1:0 CLKMODEI[1:0] Depending on CLKMODEN bit setting, these two bits reflect the phase relationship between DCLKIO and CLKIN, as described in Table 16. If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer. If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if needed to better synchronize the DACs (see the Retimer section). Version 0x1F 7:0 Version[7:0] Hardware version of the device. This register is set to 0x0A for the latest version of the device.

Table 15. Timer Register List CLKMODEQ[1:0] Q datapath retimer clock selected output. Valid after the searching bit goes low. Searching High indicates that the internal datapath retimer is searching for the clock relationship (DAC is not usable until it is low again). Reacquire Changing this bit from 0 to 1 causes the datapath retimer circuit to reacquire the clock relationship. CLKMODEN 0: Uses the CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking. 1 : Uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both the I and Q retimers (that is, force the retimer). register overrides both I and Q automatic retimer values. Table 16. CLKMODEI/CLKMODEQ Details reinitiate phase detection in the I and Q retimers at any time. detectors in the retimer (see Table 16). and the required phase value is written into CLKMODEI[1:0]. synchronizing multiple devices. SCLK pin can be taken low and then high again. not be allowed to automatically select a phase each time. selected or manually forced.

example of the use of the internal reference is shown in Figure 96. Figure 96. Internal Reference Configuration summarizes the reference operation. Table 17. Reference Operation for gain control of the DAC output. amplifier that regulates the full-scale output current, IxOUTFS. combination, and add a 1 µF capacitor from 4 kΩ to ground. The wide adjustment span of IxOUTFS provides several benefits. voltage, VREFIO, and external resistors, IRSET and QRSET, respectively.

AD9114/AD9115/AD9116/AD9117 Data Sheet Rev. D | Page 44 of 52 where: IIREF = VREFIO/IRSET (4) IQREF = VREFIO/QRSET or IIOUTFS = 32 × VREFIO/IRSET (5) IQOUTFS = 32 × VREFIO/QRSET A differential pair (IOUTP/IOUTN or QOUTP/QOUTN) typically drives a resistive load directly or via a transformer. If dc coupling is required, the differential pair (IOUTP/IOUTN or QOUTP/QOUTN) should be connected to matching resistive loads, xRLOAD, that are tied to analog common, AVSS. The single- ended voltage output appearing at the positive and negative nodes is VIOUTP = IOUTP × IRLOAD (6) VQOUTP = QOUTP × QRLOAD VIOUTN = IOUTN × IRLOAD (7) VQOUTN = QOUTN × QRLOAD To achieve the maximum output compliance of 1 V at the nominal 20 mA output current, IRLOAD = QRLOAD must be set to 50 Ω. Substituting the values of IOUTP , IOUTN, IxREF, and VIDIFF can be expressed as VIDIFF = {(2 × IDAC CODE − (2N − 1))/2N} × (32 × VREFIO/IRSET) × IRLOAD (8) Equation 8 highlights some of the advantages of operating the AD9114/AD9115/AD9116/AD9117 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTP and IOUTN, such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, VIDIFF, is twice the value of the single-ended voltage output (that is, VIOUTP or VIOUTB), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a single-ended output (VIOUTP and VIOUTN) or differential output of the AD9114/AD9115/AD9116/ AD9117 can be enhanced by selecting temperature tracking resistors for xRLOAD and xRSET because of their ratiometric relationship, as shown in Equation 8. ANALOG OUTPUT The complementary current outputs in each DAC, IOUTP/ IOUTN and QOUTP/QOUTN, can be configured for single- ended or differential operation. IOUTP/IOUTN and QOUTP/ QOUTN can be converted into complementary single-ended voltage outputs, VIOUTP and VIOUTN as well as VQOUTP and VQOUTN via a load resistor, xRLOAD, as described in the DAC Transfer Function section by Equation 6 through Equation 8. The differential voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN, and VQOUTP and VQOUTN, can also be converted to a single-ended voltage via a transformer or a differential amplifier configuration. The ac performance of the AD9114/AD9115/AD9116/AD9117 is optimum and is specified using a differential transformer-coupled output in which the voltage swing at IOUTP and IOUTN is limited to ±0.5 V . The distortion and noise performance of the AD9114/AD9115/AD9116/AD9117 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTP/IOUTN and QOUTP/QOUTN can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first- order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Because the output currents of IOUTP/IOUTN and QOUTP/QOUTN are complementary, they become additive when processed differentially. SELF-CALIBRATION The AD9114/AD9115/AD9116/AD9117 have a self-calibration feature that improves the DNL of the device. Performing a self- calibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced more by dynamic device behavior than by DNL and, in these cases, self-calibration is unlikely to produce measurable benefits. The calibration clock frequency is equal to the DAC clock divided by the division factor chosen by the DIVSEL value. There is a fixed pre-divider of 16 and it is multiplied by the DIVSEL, which has a range of divide by 2 -256. Each calibration clock cycle is between 32 and 2048 DAC input clock cycles, depending on the value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The frequency of the calibration clock should be between 0.5 MHz and 4 MHz for reliable calibrations. Best results are obtained by setting DIVSEL[2:0] to produce a calibration clock frequency between these values. Separate self-calibration hardware is included for each DAC. The DACs can be self-calibrated individually or simultaneously. To perform a device self-calibration, use the following procedure: 1. Write 0x00 to Register 0x12. This ensures that the UNCALI and UNCALQ bits (Bit 1 and Bit 0) are reset. 2. Set up a calibration clock between 0.5 MHz and 4 MHz using DIVSEL[2:0], and then enable the calibration clock by setting the CALCLK bit (Register 0x0E, Bit 3). 3. Select the DAC(s) to self-calibrate by setting either Bit 4 (CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E. Note that each DAC contains independent calibration hardware so that they can be calibrated simultaneously. 4. Start self-calibration by setting Bit 4 (CALEN) in Register 0x12. Wait approximately 300 calibration clock cycles.

quite practical when using this method. detail in the Applications Information section. Figure 99. Typical DAC Gain Characteristics termination internal resistors (two for each DAC output). voltage, connect each DAC output pin to the adjacent load pin. Internal Common-Mode Resistor section. Figure 100. Simplified Internal Load Options outputs. By default, the common-mode resistor is not connected. in Register 0x05 (IRCML[5:0]) and Register 0x08 (QRCML[5:0]). Figure 101. Typical CML Resistor Value vs. Register Code the parts allowing them to run at higher dc output bias voltages.

3.3 V , the parts perform optimally when the CMLx pins are tied

to 0 V and connect the CMLx pins directly to ground.

performance, a differential output configuration is suggested. and/or a low output impedance. cost and low power consumption are primary concerns. Figure 102. Differential Output Using a Transformer is equal to IIOUTFS and flows out of both IOUTP and IOUTN. ended current-to-voltage conversion, as shown in Figure 103.

21 FSFB

Figure 103. Single-Supply, Single-Ended Buffer

4.50 REF

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.60 MAX

Figure 111. 40-Lead Lead Frame Chip Scale Package [LFCSP]

0.20 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5. Figure 112. 40-Lead Lead Frame Chip Scale Package [LFCSP]

AD9114/AD9115/AD9116/AD9117 Data Sheet Rev. D | Page 52 of 52 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9114BCPZ −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9114BCPZRL7 −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9115BCPZ −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9115BCPZRL7 −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9116BCPZ −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9116BCPZRL7 −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9117BCPZ −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9117BCPZRL7 −40°C to +85°C 40-Lead LFCSP CP-40-1 AD9117BCPZN −40°C to +85°C 40-Lead LFCSP CP-40-9 AD9117BCPZNRL7 −40°C to +85°C 40-Lead LFCSP CP-40-9 AD9114-DPG2-EBZ Evaluation Board AD9115-DPG2-EBZ Evaluation Board AD9116-DPG2-EBZ Evaluation Board AD9117-DPG2-EBZ Evaluation Board 1 Z = RoHS Compliant Part. ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07466-0-12/17(D)

Summary

Dual Low Power Digital-to-Analog Converters 12/2017-Rev. C to Rev. D

Description