AD9106

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Quad, Low Power, 12-Bit, 180 MSPS, Digital-to- Analog Converter and Waveform Generator Data Sheet AD9106 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 2012–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Highly integrated quad DAC On-chip 4096 × 12-bit pattern memory On-chip DDS Power dissipation at 3.3 V, 4 mA output typical 315.25 mW at 180 MSPS Power-down mode: <5 mW at 3.3 V Supply voltage: 1.8 V to 3.3 V SFDR to Nyquist: 86 dBc at 10 MHz output Phase noise at 1 kHz offset, 180 MSPS, 4 mA: −140 dBc/Hz Differential full-scale current outputs: 8 mA maximum at 3.3 V Small footprint, 5 mm × 5 mm with 3.5 mm × 3.6 mm exposed paddle, 32-lead LFCSP RoHS compliant package

APPLICATIONS

Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators GENERAL DESCRIPTION The AD9106 TxDAC® and waveform generator is a high perfor- mance, quad digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform generation with a direct digital synthesizer (DDS). The DDS is a 12-bit output, up to

180 MHz master clock sinewave generator with a 24-bit tuning

word allowing 10.8 Hz/LSB frequency resolution. The DDS has a single frequency output for all four DACs and independent programmable phase shift outputs for each of the four DACs. SRAM data can include directly generated stored waveforms, amplitude modulation patterns applied to DDS outputs, or DDS frequency tuning words. An internal pattern control state machine allows the user to program the pattern period for all four DACs as well as the start delay within the pattern period for the signal output on each DAC channel. Registers accessed using the serial peripheral interface (SPI) configure the digital waveform generator and load patterns into the SRAM. There are gain adjustment factors and offset adjustments applied to the digital signals on their way into the four DACs. The AD9106 offers exceptional ac and dc performance and supports DAC sampling rates up to 180 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9106 make it well suited for portable and low power applications.

Rev. B | Page 2 of 58 TABLE OF CONTENTS Waveform Generation Setups with Ready to Use Register

Rev. B | Page 3 of 58

REVISION HISTORY

12/2017—Rev. A to Rev. B Changes to Internal Reference Voltage with AVDDx = 3.3 V Changes to Internal Reference Voltage with AVDDx = 3.3 V Change to Phase Noise at 1 kHz from Carrier Parameter, Table 6 Changes to SPI Port Section, Writing to On-Chip SRAM Changes to DAC Transfer Function Section and Programming Changes to General Signal Patterns Section and Pattern Changes to DACx Input Data Paths Section and DACx Digital Changes to DACx DDS Phase Shift Section, Direct Digital Changes to Clock Selection for Incrementing Pattern Added Waveform Generation Setups with Ready to Use Register Values Section, Programming Example 1: Four Gaussian Pulses with Different Start Delays and Varied Digital Gain Settings Added Programming Example 2: Four Pulses Generated from Added Programming Example 3: Four Pulsed Sine Waves with Different Start Delays and Varied Digital Gain Settings Added Programming Example 4: Pulsed Sine Wave from DDS and Three Sawtooth Generator Waveforms Section, Figure 58, Added Programming Example 5: Pulsed Sine Waves from DDS Amplitude Modulated by an SRAM Vector Section, Figure 59, Added Programming Example 6: Sine Wave from DDS and /2013—Rev. 0 to Rev. A Deleted Recommendations When Using an External /2012—Revision 0: Initial Version

Rev. B | Page 4 of 58 FUNCTIONAL BLOCK DIAGRAM DAC1 DAC2 10kΩ IREF 100µA 1.8V LDOs 1VAD9106 IOUTP1 IOUTN1 AVDD1 AGND IOUTP2 IOUTN2 DVDD DGND DLDO1 SDIO SCLK RESET REFIO FSADJ1 FSADJ2/CAL_SENSE CLKVDD CLKGND CLKN CS CLDO CLKP 1.8V LDO DAC3 DAC4 IOUTP3 IOUTN3 AVDD2 IOUTP4 IOUTN4 R SET3 16kΩ RSET4 16kΩ FSADJ4 FSADJ3 DPRAM ADDRESS 1, ADDRESS 2 ADDRESS 3, ADDRESS 4 GAIN1 OFFSET1 DAC1 DAC2 DAC3 DAC4 DAC3 TO DAC4 TIMERS + STATE MACHINES DAC1 TO DAC2 TIMERS + STATE MACHINES START ADDR START DLY STOP ADDR START ADDR START DLY STOP ADDR DAC CLOCK DAC CLOCK TRIGGER SDO/SDI2/DOUT DLDO2 DDS TUNING WORD PHASE1 PHASE2 PHASE3 PHASE4 DAC CLOCK DDS1 DDS2 DDS3 DDS4 SAWTOOTH1 CONSTANT1 DDS1 RANDOM1 SPI INTERFACE GAIN2 OFFSET2 GAIN3 OFFSET3 GAIN4 OFFSET4 BAND GAP RSET1 16kΩ RSET2 16kΩ CLOCK DIST 11121-001 F igure 1.

Rev. B | Page 5 of 58 SPECIFICATIONS DC SPECIFICATIONS (3.3 V) TMIN to TMAX, AVDDx = 3.3 V , DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter Min Typ Max Unit RESOLUTION 12 Bit s ACCURACY AT 3.3 V Differential Nonlinearity (DNL) ±0.4 LSB Integral Nonlinearity (INL) ±0.5 LSB DAC OUTPUTS Offset Error ±0.00025 % o f FSR Gain Error Internal Reference—No Automatic IOUTFS Calibration −1.0 +1.0 % of FSR Full-Scale Output Current1 at 3.3 V 2 4 8 mA Output Resistance 200 MΩ Output Compliance Voltage −0.5 +1.0 V Crosstalk, DAC to DAC fOUT = 10 MHz 96 dBc fOUT = 60 MHz 82 dBc DAC TEMPERATURE DRIFT Gain with Internal Reference ±251 pp m/°C Internal Reference Voltage ±119 pp m/°C REFERENCE OUTPUT Internal Reference Voltage with AVDDx = 3.3 V 1.0 V Output Resistance 10 kΩ REFERENCE INPUT Voltage Compliance 0.1 1.25 V Input Resistance External, Reference Mode 1 MΩ DAC MATCHING Gain Matching—No Automatic IOUTFS Calibration ±0.75 % o f FSR 1 Based on use of 8 kΩ ex ternal RSETx resistors.

Rev. B | Page 6 of 58 DC SPECIFICATIONS (1.8 V) TMIN to TMAX, AVDDx = 1.8 V, DVDD = DLDO1 = DLDO2 = 1 . 8 V, CLKVDD = CLDO = 1.8 V , IOUTFS = 4 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter Min Typ Max Unit RESOLUTION 12 Bits ACCURACY AT 1.8 V Differential Nonlinearity (DNL) ±0.4 LSB Integral Nonlinearity (INL) ±0.4 LSB DAC OUTPUTS Offset Error ±0.00025 % of FSR Gain Error Internal Reference—No Automatic IOUTFS Calibration −1.0 +1.0 % of FSR Full-Scale Output Current1 at 1.8 V 2 4 4 mA Output Resistance 200 MΩ Output Compliance Voltage −0.5 +1.0 V Crosstalk, DAC to DAC fOUT = 30 MHz 94 dB fOUT = 60 MHz 78 dB DAC TEMPERATURE DRIFT Gain ±228 ppm/°C Reference Voltage ±131 ppm/°C REFERENCE OUTPUT Internal Reference Voltage with AVDDx = 1.8 V 1.0 V Output Resistance 10 kΩ REFERENCE INPUT Voltage Compliance 0.1 1.25 V Input Resistance External, Reference Mode 1 MΩ DAC MATCHING Gain Matching—No Automatic IOUTFS Calibration ±0.75 % of FSR 1 Based on use of 8 kΩ ex ternal RSETx resistors.

Rev. B | Page 7 of 58 DIGITAL TIMING SPECIFICATIONS (3.3 V) TMIN to TMAX, AVDDx = 3.3 V , DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKx) Maximum Clock Rate 180 MSP S SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 80 MHz Minimum Pulse Width High 6.25 ns Minimum Pulse Width Low 6.25 ns Setup Time, SDIO to SCLK 3.5 ns Hold Time, SDIO to SCLK 1.5 ns Output Data Valid, SCLK to SDO1 or SDIO 6.2 ns Setup Time, CS to SCLK 4.0 ns TRIGGER TIMING RELATIVE TO CLKP/CLKN RISING EDGE Setup Time (tSU), TRIGGER Edge to CLKP/CLKN 1.5 ns Hold Time, CLKP/CLKN to TRIGGER Edge 2.0 ns 1 Note that throughout this data sheet, multifunction pins, such as SDO/SDI2/DOUT, are referred to either by the entire pin name or by a single function of the pin, for example, SDO, when only that function is relevant. DIGITAL TIMING SPECIFICATIONS (1.8 V) TMIN to TMAX, AVDDx = 1.8 V , DVDD = DLDO1 = DLDO2 = 1.8 V , CLKVDD = CLDO = 1.8 V , IOUTFS = 4 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKx) Maximum Clock Rate 180 MSP S SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 80 MHz Minimum Pulse Width High 6.25 ns Minimum Pulse Width Low 6.25 ns Setup Time, SDIO to SCLK 3.5 ns Hold Time, SDIO to SCLK 1.5 ns Output Data Valid, SCLK to SDO or SDIO 8.8 ns Setup Time, CS to SCLK 4.0 ns TRIGGER TIMING RELATIVE TO CLKP/CLKN RISING EDGE Setup Time, TRIGGER Edge to CLKP/CLKN 1.5 ns Hold Time, CLKP/CLKN to TRIGGER Edge 2.0 ns

Rev. B | Page 8 of 58 INPUT/OUTPUT SIGNAL SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit CMOS INPUT LOGIC LEVEL (SCLK, CS, SDIO, SDO/SDI2/DOUT, RESET, TRIGGER) Input Voltage, VIN Logic High DVDD = 1.8 V 1.53 V DV DD = 3.3 V 2.475 V Logic Low DVDD = 1.8 V 0.27 V DV DD = 3.3 V 0.825 V CMOS OUTPUT LOGIC LEVEL (SDIO, SDO/SDI2/DOUT) Output Voltage, VOUT Logic High DVDD = 1.8 V 1.79 V DV DD = 3.3 V 3.28 V Logic Low DVDD = 1.8 V 0.25 V DV DD = 3.3 V 0.625 V DAC CLOCK INPUT (CLKP , CLKN) Minimum Peak-to-Peak Differential Input Voltage, VCLKP/VCLKN 150 mV Maximum Voltage at VCLKP or VCLKN VDVDD V Minimum Voltage at VCLKP or VCLKN VDGND V Common-Mode Voltage Generated on Chip 0.9 V

Rev. B | Page 9 of 58 AC SPECIFICATIONS (3.3 V) TMIN to TMAX, AVDDx = 3.3 V , DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate, unless otherwise noted. Table 6. Parameter Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) DAC Sample Rate (fDAC) = 180 MSPS, DAC Output Frequency (fOUT) = 10 MHz 86 dBc fDAC = 180 MSPS, fOUT = 50 MHz 73 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 180 MSPS, fOUT = 10 MHz 92 dBc fDAC = 180 MSPS, fOUT = 50 MHz 77 dBc NOISE SPECTRAL DENSITY (NSD) fDAC = 180 MSPS, fOUT = 50 MHz −167 dB m/Hz PHASE NOISE AT 1 kHz FROM CARRIER fDAC = 180 MSPS, fOUT = 10 MHz −140 dB c/Hz DYNAMIC PERFORMANCE Output Settling Time, Full-Scale Output Step (to 0.1%)1 31.2 ns Trigger to Output Delay, fDAC = 180 MSPS2 96 ns Rise Time, Full-Scale Swing1 3.25 ns Fall Time, Full-Scale Swing1 3.26 ns 1 Based on the 85 Ω re sistors from DAC output terminals to ground. 2 Start delay = 0 fDAC clock cycles. AC SPECIFICATIONS (1.8 V) TMIN to TMAX, AVDDx = 1.8 V, DVDD = DLDO1 = DLDO2 = 1 . 8 V, CLKVDD = CLDO = 1.8 V , IOUTFS = 4 mA, maximum sample rate, unless otherwise noted. Table 7. Parameter Min Typ Max Unit SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 180 MSPS, fOUT = 10 MHz 83 dBc fDAC = 180 MSPS, fOUT = 50 MHz 74 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 180 MSPS, fOUT = 10 MHz 91 dBc fDAC = 180 MSPS, fOUT = 50 MHz 83 dBc NSD fDAC = 180 MSPS, fOUT = 50 MHz −163 dB m/Hz PHASE NOISE AT 1 kHz FROM CARRIER fDAC = 180 MSPS, fOUT = 10 MHz −140 dB c/Hz DYNAMIC PERFORMANCE Output Settling Time (to 0.1%)1 31.2 ns Trigger to Output Delay, fDAC = 180 MSPS2 96 ns Rise Time1 3.25 ns Fall Time1 3.26 ns 1 Based on the 85 Ω re sistors from DAC output terminals to ground. 2 Start delay = 0 fDAC clock cycles.

Rev. B | Page 10 of 58 POWER SUPPLY VOLTAGE INPUTS AND POWER DISSIPATION Table 8. Parameter Test Conditions/Comments Min Typ Max Unit ANALOG SUPPLY VOLTAGES AVDD1, AVDD2 1.7 3.6 V CLKVDD 1.7 3.6 V CLDO On-chip low dropout (LDO) regulator not in use 1.7 1.9 V DIGITAL SUPPLY VOLTAGES DVDD 1.7 3.6 V DLDO1, DLDO2 On-chip LDO not in use 1.7 1.9 V POWER CONSUMPTION, 3.3 V AVDDx = 3.3 V; DVDD = 3.3 V; CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2 fDAC = 180 MSPS, Pure Continuous Waveform (CW) Sine Wave 12.5 MHz (DDS only), all four DACs 315.25 mW IAVDDx 28.51 mA IDVDD DDS Only CW sine wave output 60.3 mA RAM Only 50% duty cycle full-scale (FS) pulse output 27.1 mA DDS and RAM Only 50% duty cycle sine wave output 39.75 mA ICLKVDD 6.72 mA Power-Down Mode REF_PDN = 0, DACs sleep, clock power down, external clock, and supplies on 4.73 mW POWER CONSUMPTION, 1.8 V AVDDx = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V fDAC = 180 MSPS, Pure CW Sine Wave 12.5 MHz (DDS on ly) 167 mW IAVDDx 28.14 mA IDVDD 0.151 mA IDLDO2 DDS Only CW sine wave output 53.75 mA RAM Only 50% duty cycle FS pulse output 17.78 mA DDS and RAM Only—50% Duty Cycle Sine Wave Output 35.4 mA IDLDO1 4.0 mA ICLKVDD 0.0096 mA ICLDO 6.6 mA Power-Down Mode REF_PDN = 0, DACs sleep, clock power down, external clock, and supplies on 1.49 mW

PCB thermal design is required. Table 10. Thermal Resistance

1 Typical θJA, θJB, and θJC values are specified for a JEDEC 4-layer 2S2P board in

still air. Airflow increases heat dissipation, effectively reducing θJA and θJB. 2 θJC is junction to case on the exposed pad.

24 FSADJ2/CAL_SENSE

23 CLKVDD

22 CLDO

21 CLKP

20 CLKN

19 CLKGND

18 REFIO

17 FSADJ4

1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.

Table 11. Pin Function Descriptions 2 SDIO SPI Data Input/Output. Primary bidirectional data line for the SPI port. 7 SDO/SDI2/DOUT Serial Data Output (SDO). In 4-wire SPI mode, this pin outputs the data from the SPI. port used to write to the SRAM. Pulse Output (DOUT). In data output mode, this terminal is a programmable pulse output. 8 CS SPI Port Chip Select, Active Low. 9 RESET Active Low Reset Pin. Resets registers to their default values. 10 IOUTP4 DAC4 Current Output, Positive Side. 11 IOUTN4 DAC4 Current Output, Negative Side. 12 AVDD2 1.8 V to 3.3 V Power Supply Input for DAC3 and DAC4. 13 IOUTN3 DAC3 Current Output, Negative Side. 14 IOUTP3 DAC3 Current Output, Positive Side. 16 FSADJ3 External Full-Scale Current Output Adjust for DAC3. 17 FSADJ4 External Full-Scale Current Output Adjust for DAC4. 18 REFIO DAC Voltage Reference Input/Output. 20 CLKN Clock Input, Negative Side. 21 CLKP Clock Input, Positive Side. 23 CLKVDD Clock Power Supply Input. 24 FSADJ2/CAL_SENSE External Full-Scale Current Output Adjust for DAC2 (FSADJ2). Sense Input for Automatic IOUTFS Calibration (CAL_SENSE). Automatic IOUTFS Calibration. 27 IOUTP1 DAC1 Current Output, Positive Side.

Rev. B | Page 13 of 58 Pin No. Mnemonic Description 28 IOUTN1 DAC1 Current Output, Negative Side. 29 AVDD1 1.8 V to 3.3 V Power Supply Input for DAC1 and DAC2. 30 IOUTN2 DAC2 Current Output, Negative Side. 31 IOUTP2 DAC2 Current Output, Positive Side. 32 TRIGGER Pattern Trigger Input, Active Low. EPAD Ex posed Pad. The exposed pad must be connected to DGND.

Rev. B | Page 16 of 58 0.4 0.3 0.2 0.1 –0.1 –0.2 –0.3 0 500 1000 1500 2000 2500 3000 450040003500 DNL (LSB) CODE 2mA 4mA 8mA 11121-015 F igure 15. DNL, at Three IOUTFS Values 0.5 0.4 0.3 0.2 0.1 –0.1 –0.2 –0.3 0 500 1000 1500 2000 2500 3000 450040003500 INL (LSB) CODE 2mA 4mA 8mA 11121-016 F igure 16. INL, at Three IOUTFS Values –80 –100 –120 –140 –160 –180 100 10M1M100k10k1k PHASE NOISE (dBc/Hz) OFFSET (Hz) fS = 175MHz, 10MHz fS = 175MHz, 10.9375MHz fS = 175MHz, 20MHz 11121-017 F igure 17. Phase Noise

Rev. B | Page 19 of 58 0.5 0.4 0.3 0.2 0.1 –0.1 –0.2 –0.3 0 500 1000 1500 2000 2500 3000 450040003500 INL (LSB) CODE 2mA 4mA 11121-031 F igure 30. INL, at Two IOUTFS Values

Rev. B | Page 20 of 58 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTPx, 0 mA output is expected when the inputs are all 0s. For IOUTNx, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1, minus the output when all inputs are set to 0. The ideal gain is calculated using the measured V REFIO. Therefore, the gain error does not include effects of the reference. Output Compliance Voltage Output compliance voltage is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. T emperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in ppm of full- scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in picovolt-seconds (pV-sec). Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Noise Spectral Density (NSD) Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.

for the SRAM update procedure. the built in automatic gain calibration capability of the device. mode signals at the DAC outputs are rejected. specifications in these tables to be met. and/or lower temperature drift than the on-chip band gap. Table 13 summarizes reference connections and programming. Table 13. Reference Operation The internal REFIO voltage level is programmable. tracks this change. As a result, IREFx varies by the same amount. shown in Table 1 and Table 2 from chip to chip.

Rev. B | Page 25 of 58 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515/ AD9516/AD9518 0.1µF CLK CLK 0.1µF 0.1µF CLKN CLKP AD9106 OPTIONAL 100Ω 39kΩ CMOS DRIVER CLK+ 50Ω 11121-040 F igure 39. Single-Ended 1.8 V CMOS Sample Clock AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515/ AD9516/AD9518 100Ω 0.1µF 0.1µF0.1µF 0.1µF 240Ω240Ω50Ω* 50Ω* CLK CLK *50Ω RESISTORS ARE OPTIONAL. CLKN CLKP AD9106PECL DRIVER CLK+ CLK– 11121-041 F igure 40. Differential PECL Sample Clock 0.1µF 0.1µF0.1µF SCHOTTKY DIODES: HSM2812 CLK+ 50Ω CLKN CLKP Mini-Circuits® ADT1-1WT, 1:1Z XFMR AD9106 11121-042 F igure 41. Transformer Coupled Clock DAC OUTPUT CLOCK EDGE Each of the four DACs can be configured independently to output samples on the rising or falling edge of the CLKP/CLKN clock input by configuring the DACx_INV_CLK bits in the CLOCKCONFIG register. This functionality sets the DAC output timing resolution at 1/(2 × fCLKP/CLKN). GENERATING SIGNAL PATTERNS The AD9106 can generate two types of signal patterns under the control of its programmable pattern generator.

• Periodic pulse train waveforms that repeat indefinitely.
• Periodic pulse train waveforms that repeat a finite number of times. Run Bit Setting the run bit in the PAT_STATUS register to 1 activates the AD9106 for pattern generation. Clearing this bit shuts down the pattern generator, as shown in Figure 45. Trigger Terminal A falling edge on the trigger terminal starts the generation of a pattern. If the run bit is set, the falling edge of trigger starts pattern generation. As shown in Figure 43, the pattern generator state goes to pattern generator on after a number of CLKP/CLKN clock cycles following the falling edge of trigger. This delay is programmed in the PATTERN_DELAY bit field. The rising edge on the trigger terminal is a request for the termination of pattern generation (see Figure 44). Pattern Bit (Read Only) The read only pattern bit in the PAT_STATUS register indicates, when set to 1, that the pattern generator is in the pattern generator on state. A 0 indicates that the pattern generator is in the pattern generator off state. Pattern Types
• Periodic pulse trains that repeat indefinitely are waveforms that are output once during each pattern period. Pattern periods occur one after the other as long as the pattern generator is in the pattern on state.
• Periodic pulse trains that repeat a finite number of times are just like those that repeat indefinitely except that the wa veforms are output during a finite number of consecutive pattern periods. PATTERN EXECUTED PATTERN EXECUTED PATTERN EXECUTED TRIGGER DAC1 DAC2 DAC3 DAC4 PATTERN_PERIOD START_DLY1 START_DLY2 START_DLY4 START_DLY3 DATA AT START_ADDR1 DATA AT STOP_ADDR1 DATA AT START_ADDR2 DATA AT STOP_ADDR2 DATA AT START_ADDR3 DATA AT STOP_ADDR3 DATA AT START_ADDR4 DATA AT STOP_ADDR4 11121-043 F igure 42. Periodic Pulse Trains Output on All DACx

Rev. B | Page 27 of 58 DACx, Number of DDS Cycles Each DACx input data path establishes the pulse width of the sine wave output from the single common DDS in number of sine wave cycles. The cycle counts are programmed in the DDS_CYCx registers. DACx DDS Phase Shift Each DACx input data path shifts the phase of the output of the single common DDS. The phase shift is programmed using the DDSx_PHASE fields. The DDSx phase offset for each DACx data path has a range of 360° and a resolution of 360°/(2 16 − 1). DOUT FUNCTION In applications where AD9106 DACs drive high voltage amplifiers, such as in ultrasound transducer array element driver signal chains, it can be useful to turn on and off each amplifier at precise times relative to the waveform generated by each AD9106 DAC. The SDO/SDI2/DOUT terminal can be configured to provide this function. One amplifier on/off strobe can be provided for all four DACs. The SPI interface needs to be configured in 3-wire mode (see Figure 32 and Figure 33) by setting the SPI3WIRE or SPI3WIREM bits in the SPICONFIG register. When SPI_DRV or SPI_DRVM of the SPICONFIG register is set to Logic 1, the SDO/SDI2/DOUT terminal provides the DOUT function. Manually Controlled DOUT If DOUT_MODE = 0 in the DOUT_CONFIG register, DOUT can be turned on or off using the DOUT_V AL bit of that same register. Pattern Generator Controlled DOUT Figure 46 depicts the rising edge of a pattern generator controlled DOUT pulse. Figure 47 shows the falling edge. The pattern generator controlled DOUT pulse is set by setting DOUT_MODE = 1. Then, the start delay is programmed in the DOUT_START_DLY register and the stop delay is programmed into the DOUT_STOP field of the DOUT_CONFIG register. DOUT goes high DOUT_START[15:0] CLKP/CLKN cycles after the falling edge of the signal input to the trigger terminal. DOUT stays high as long as a pattern is being generated. DOUT goes low DOUT_STOP[3:0] CLKP/CLKN cycles after the clock edge that causes pattern generation to stop. TRIGGER CLKP/ CLKN DOUT DELAY= DOUT_START[15:0] CLKP/CLKN CYCLES DOUT tSU 11121-047 F igure 46. DOUT Start Sequence CLKP/CLKN PATTERN GENERATOR STATE DOUT PATTERN ON PATTERN OFF PATTERN STOPS DOUT DELAY = DOUT_STOP[3:0] CLKP/CLKN CYCLES 11121-048 F igure 47. DOUT Stop Sequence DIRECT DIGITAL SYNTHESIZER (DDS) The DDS generates a single frequency sine wave that can be output on any of the four DACx. The DDS is a global shared signal resource. It can generate one sinusoid at a frequency determined by its tuning word input. The tuning word is 24 bits wide. The resolution of DDS tuning is fCLKP/CLKN/224. The DDS output frequency is DDS_TW × fCLKP/CLKN/224. The DDS tuning word is programmed using one of two methods. For a fixed frequency, DDSTW_MSB and DDSTW_LSB are programmed with a constant. When the frequency of the DDS needs to change within each pattern period, a sequence of values stored in SRAM is combined with a selection of DDSTW_MSB bits to form the tuning word. DDS Phase Offset for Each DACx The single shared DDS has an output for each DACx data path that includes a programmable phase shifter. SRAM The AD9106 4096 × 12-bit SRAM can contain signal samples, amplitude modulation patterns, lists of DDS tuning words, or lists of DDS output phase offset words. Data is written to and read from the memory via the SPI port as long as the SRAM is not actively engaged in pattern generation (run = 0). To write to SRAM, set up the PAT_STATUS register as follows:

• BUF_READ = 0
• MEM_ACCESS = 1
• Run = 0 To read data from SRAM, set up the PAT_STATUS register as follows:
• BUF_READ = 1
• MEM_ACCESS = 1
• Run = 0 The SPI port address space for SRAM is Location 0x6000 through Location 0x6FFF . The SRAM SPI address autodecrements during multiple location SPI reads and writes.

Rev. B | Page 28 of 58 SRAM can be accessed using any of the SPI operating modes shown in Figure 32 through Figure 35. Using the SPI modes of operation shown in Figure 33 and Figure 34, the entire SRAM can be written in (2 + 2 × 4096) × 8/fSCLK seconds. The SRAM is a shared signal generation resource. Data from this one 4096 × 12-bit SRAM can be used to generate signals for all four DACs. When the RUN bit = 1 (pattern generation enabled) in the PAT_STATUS register, each DACx data path has its own SRAM address counter. Each address counter has its own START_ADDRx and STOP_ADDRx. During each pattern period, data is read from RAM after the START_DELAYx period and while the each address counter is incrementing. SRAM is read simultaneously by all four DACx data paths. The SRAM length being written must be an even number if Register 0x44, Bit 1 = 0x01. This requirement implies that the START_ADDRx and STOP_ADDRx cannot both be even or both be odd: only one of the addresses can be even, while the other address must be odd. Clock Selection for Incrementing Pattern Generation Mode SRAM Address Counters The DDS_MSB_ENx bits in the DDSx_CONFIG registers select the signal that clocks each address counter. When the SRAM contains waveform samples or DDS amplitude modulation samples, each of the SRAM address counters must be incremented by CLKP/CLKN (default). When the SRAM contains a list of DDS tuning words, such as when generating a chirp waveform, SRAM address counters can be incremented by CLKP/CLKN (default) or by the rising edge of the DDSx output MSB. SAWTOOTH GENERATOR There is a separate sawtooth signal generator for each DACx. When the sawtooth is selected in any of the PRESTORE_SELx fields in the W AV4_3CONFIG or W AV2_1 CONFIG register, the appropriate sawtooth generator is connected to the desired DACx digital data path. Sawtooth types, shown in Figure 48, are selected using the SAW_TYPEx fields in the SAWx_yCONFIG registers. The number of samples per sawtooth waveform step is programmed in each SAW_STEPx field. POSITIVE SAWTOOTH NEGATIVE SAWTOOTH TRIANGLE WAVE 11121-049 F igure 48. Sawtooth Patterns PSEUDORANDOM SIGNAL GENERATOR The pseudorandom noise generator generates a noise signal on each DACx output if pseudorandom sequence is selected in any of the PRESTORE_SELx fields in the W AV4_3CONFIG or W AV2_1 CONFIG register. The pseudorandom noise signals are generated as continuous waveforms only. DC CONSTANT A programmable dc current between 0.0 and IOUTFSx can be generated on each DACx if constant value is selected in any of the PRESTORE_SELx fields of the W AV4_3CONFIG or W AV2_1 CONFIG register. DC constant currents are generated as continuous waveforms only. The dc current level is programmed by writing to the DACx_CONST field in the appropriate DACx_CST register. POWER SUPPLY NOTES The AD9106 supply rails are specified in Table 9. The AD9106 includes three on-chip linear regulators. The supply rails driven by these regulators operate at 1.8 V. Two usage rules for these regulators follow:

• When CLKVDD is 2.5 V or higher, the 1.8 V on-chip CLDO regulator can be used. If CLKVDD = 1.8 V , the CLDO regulator must be disabled by setting the PDN_LDO_CLK bit in the POWERCONFIG register. CLKVDD and CLDO are connected together.
• When DVDD is 2.5 V or higher, the 1.8 V on-chip DLDO1 a nd DLDO2 regulators can be used. If DVVD is 1.8 V, t h e DLDO1 and DLDO2 regulators must be disabled by setting the PDN_LDO_DIG1 and PDN_LDO_DIG2 bits in the POWERCONFIG register. DVDD, DLDO1, and DLDO2 are connected together POWER-DOWN CAPABILITIES The POWERCONFIG register allows the user to place the AD9106 in a reduced power dissipation configuration while the CLKP/CLKN input is running and the power supplies are on. DAC1, DAC2, DAC3, and DAC4 can all be put to sleep by setting the DACx_SLEEP bits in the POWERCONFIG register. Clocking of the waveform generator and the DACs can be turned off by setting the CLK_PDN bit in the CLOCKCONFIG register. Taking these actions places the AD9106 in the power-down mode specified in Table 8.

downloading the DAC software suite from www.analog.com. Table 14. Register Values for Programming Example 1

Figure 56. Programming Example 2 Table 15. Register Values for Programming Example 2

Rev. B | Page 33 of 58 Address Data 0x0027 0x3030 0x0028 0x0111 0x0029 0xFFFF 0x002A 0x0101 0x002B 0x0101 0x002C 0x0003 0x002D 0x0000 0x002E 0x0000 0x002F 0x0000 0x0030 0x0000 0x0031 0x0000 0x0032 0x4000 0x0033 0x2000 0x0034 0x2000 0x0035 0x4000 0x0036 0x0001 0x0037 0x0200 0x0038 0x0000 0x0039 0x0000 0x003A 0x0000 0x003B 0x0000 0x003C 0x0000 0x003D 0x0000 0x003E 0x0000 0x003F 0x0000 0x0040 0x0000 0x0041 0x0000 0x0042 0x0000 0x0043 0x0000 0x0044 0x0000 0x0045 0x0000 0x0046 0x0000 0x0047 0x0000 0x0048 0x0000 0x0049 0x0000 0x004A 0x0000 0x004B 0x0000 0x004C 0x0000 0x004D 0x0000 0x004E 0x0000 0x004F 0x0000 0x0050 0x07D0 0x0051 0xC000 0x0052 0xFFF0 0x0053 0x0100 Address Data 0x0054 0x03E8 0x0055 0x8000 0x0056 0xBFF0 0x0057 0x0100 0x0058 0x0BB8 0x0059 0x3FF0 0x005A 0x7FF0 0x005B 0x0100 0x005C 0x0FA0 0x005D 0x0000 0x005E 0x3FF0 0x005F 0x0100 0x0060 0x0000 0x0061 0x0000 0x0062 0x0000 0x0063 0x0000 0x0064 0x0000 0x0065 0x0000 0x0066 0x0000 0x0067 0x0000 0x0068 0x0000 0x0069 0x0000 0x006A 0x0000 0x006B 0x0000 0x006C 0x0000 0x006D 0x0000 0x006E 0x0000 0x006F 0x0000 0x0070 0x0000 0x0071 0x0000 0x0072 0x0000 0x0073 0x0000 0x0074 0x0000 0x0075 0x0000 0x0076 0x0000 0x0077 0x0000 0x0078 0x0000 0x0079 0x0000 0x007A 0x0000 0x007B 0x0000 0x007C 0x0000 0x007D 0x0000 0x007E 0x0000 0x007F 0x0000

Figure 57. Programming Example 3 Table 16. Register Values for Programming Example 3

Table 17. Register Values for Programming Example 4

Rev. B | Page 36 of 58 Address Data 0x0027 0x1232 0x0028 0x0121 0x0029 0xFFFF 0x002A 0x0101 0x002B 0x0101 0x002C 0x0003 0x002D 0x0000 0x002E 0x0000 0x002F 0x0000 0x0030 0x0000 0x0031 0x0000 0x0032 0x4000 0x0033 0x4000 0x0034 0x4000 0x0035 0x4000 0x0036 0x1011 0x0037 0x0600 0x0038 0x0000 0x0039 0x0000 0x003A 0x0000 0x003B 0x0000 0x003C 0x0000 0x003D 0x0000 0x003E 0x1999 0x003F 0x9A00 0x0040 0x0000 0x0041 0x0000 0x0042 0x0000 0x0043 0x0000 0x0044 0x0000 0x0045 0x0000 0x0046 0x0000 0x0047 0x0000 0x0048 0x0000 0x0049 0x0000 0x004A 0x0000 0x004B 0x0000 0x004C 0x0000 0x004D 0x0000 0x004E 0x0000 0x004F 0x0000 0x0050 0x07D0 0x0051 0x0000 0x0052 0x0000 0x0053 0x0001 Address Data 0x0054 0x03E8 0x0055 0x0000 0x0056 0x0000 0x0057 0x0001 0x0058 0x03E8 0x0059 0x0000 0x005A 0x0000 0x005B 0x0001 0x005C 0x0FA0 0x005D 0x0000 0x005E 0x0000 0x005F 0x16FF 0x0060 0x0004 0x0061 0x0000 0x0062 0x0000 0x0063 0x0000 0x0064 0x0000 0x0065 0x0000 0x0066 0x0000 0x0067 0x0000 0x0068 0x0000 0x0069 0x0000 0x006A 0x0000 0x006B 0x0000 0x006C 0x0000 0x006D 0x0000 0x006E 0x0000 0x006F 0x0000 0x0070 0x0000 0x0071 0x0000 0x0072 0x0000 0x0073 0x0000 0x0074 0x0000 0x0075 0x0000 0x0076 0x0000 0x0077 0x0000 0x0078 0x0000 0x0079 0x0000 0x007A 0x0000 0x007B 0x0000 0x007C 0x0000 0x007D 0x0000 0x007E 0x0000 0x007F 0x0000

Table 18. Register Values for Programming Example 5

Figure 60. Programming Example 6 Table 19. Register Values for Programming Example 6

Rev. B | Page 39 of 58 Address Data 0x0027 0x3333 0x0028 0x0111 0x0029 0xFFFF 0x002A 0x0101 0x002B 0x0101 0x002C 0x0003 0x002D 0x0000 0x002E 0x0000 0x002F 0x0000 0x0030 0x0000 0x0031 0x0000 0x0032 0x4000 0x0033 0x4000 0x0034 0x4000 0x0035 0x4000 0x0036 0x0001 0x0037 0x0200 0x0038 0x0000 0x0039 0x0000 0x003A 0x0000 0x003B 0x0000 0x003C 0x0000 0x003D 0x0000 0x003E 0x0750 0x003F 0x7500 0x0040 0x0000 0x0041 0x0000 0x0042 0x0000 0x0043 0x0000 0x0044 0x0000 0x0045 0x0000 0x0046 0x0000 0x0047 0x0000 0x0048 0x0000 0x0049 0x0000 0x004A 0x0000 0x004B 0x0000 0x004C 0x0000 0x004D 0x0000 0x004E 0x0000 0x004F 0x0000 0x0050 0x07D0 0x0051 0x0000 0x0052 0xFFF0 0x0053 0x0100 Address Data 0x0054 0x03E8 0x0055 0x0000 0x0056 0xFFF0 0x0057 0x0100 0x0058 0x0BB8 0x0059 0x0000 0x005A 0xFFF0 0x005B 0x0100 0x005C 0x0FA0 0x005D 0x0000 0x005E 0xFFF0 0x005F 0x0100 0x0060 0x0005 0x0061 0x0000 0x0062 0x0000 0x0063 0x0000 0x0064 0x0000 0x0065 0x0000 0x0066 0x0000 0x0067 0x0000 0x0068 0x0000 0x0069 0x0000 0x006A 0x0000 0x006B 0x0000 0x006C 0x0000 0x006D 0x0000 0x006E 0x0000 0x006F 0x0000 0x0070 0x0000 0x0071 0x0000 0x0072 0x0000 0x0073 0x0000 0x0074 0x0000 0x0075 0x0000 0x0076 0x0000 0x0077 0x0000 0x0078 0x0000 0x0079 0x0000 0x007A 0x0000 0x007B 0x0000 0x007C 0x0000 0x007D 0x0000 0x007E 0x0000 0x007F 0x0000

Table 20. Register Summary

Rev. B | Page 41 of 58 Addr (Hex) Register Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x28 PAT_TIMEBASE [15:8] RESERVED HOLD 0x0111 RW [7:0] PAT_PERIOD_BASE START_DELAY_BASE 0x29 PAT_PERIOD [15:8] PATTERN_PERIOD[15:8] 0x8000 RW [7:0] PATTERN_PERIOD[7:0] 0x2A DAC4_3PATx [15:8] DAC4_REPEAT_CYCLE 0x0101 RW [7:0] DAC3_REPEAT_CYCLE 0x2B DAC2_1PATx [15:8] DAC2_REPEAT_CYCLE 0x0101 RW [7:0] DAC1_REPEAT_CYCLE 0x2C DOUT_START _DLY [15:8] DOUT_START[15:8] 0x0003 RW [7:0] DOUT_START[7:0] 0x2D DOUT_CONFIG [15:8] RESERVED[9:2] 0x00 RW [7:0] RESERVED[1:0] DOUT_VAL DOUT_MODE DOUT_STOP 0x2E DAC4_CST [15:8] DAC4_CONST[11:4] 0x00 RW [7:0] DAC4_CONST[3:0] RESERVED 0x2F DAC3_CST [15:8] DAC3_CONST[11:4] 0x00 RW [7:0] DAC3_CONST[3:0] RESERVED 0x30 DAC2_CST [15:8] DAC2_CONST[11:4] 0x00 RW [7:0] DAC2_CONST[3:0] RESERVED 0x31 DAC1_CST [15:8] DAC1_CONST[11:4] 0x00 RW [7:0] DAC1_CONST[3:0] RESERVED 0x32 DAC4_DGAIN [15:8] DAC4_DIG_GAIN[11:4] 0x00 RW [7:0] DAC4_DIG_GAIN[3:0] RESERVED 0x33 DAC3_DGAIN [15:8] DAC3_DIG_GAIN[11:4] 0x00 RW [7:0] DAC3_DIG_GAIN[3:0] RESERVED 0x34 DAC2_DGAIN [15:8] DAC2_DIG_GAIN[11:4] 0x00 RW [7:0] DAC2_DIG_GAIN[3:0] RESERVED 0x35 DAC1_DGAIN [15:8] DAC1_DIG_GAIN[11:4] 0x00 RW [7:0] DAC1_DIG_GAIN[3:0] RESERVED 0x36 SAW4_3CONFIG [15:8] SAW_STEP4 SAW_TYPE4 0x00 RW [7:0] SAW_STEP3 SAW_TYPE3 0x37 SAW2_1CONFIG [15:8] SAW_STEP2 SAW_TYPE2 0x00 RW [7:0] SAW_STEP1 SAW_TYPE1 0x38 to 0x3D RESERVED RESERVED 0x3E DDS_TW32 [15:8] DDSTW_MSB[15:8] 0x00 RW [7:0] DDSTW_MSB[7:0] 0x3F DDS_TW1 [15:8] DDSTW_LSB 0x00 RW [7:0] RESERVED 0x40 DDS4_PW [15:8] DDS4_PHASE[15:8] 0x00 RW [7:0] DDS4_PHASE[7:0] 0x41 DDS3_PW [15:8] DDS3_PHASE[15:8] 0x00 RW [7:0] DDS3_PHASE[7:0] 0x42 DDS2_PW [15:8] DDS2_PHASE[15:8] 0x00 RW [7:0] DDS2_PHASE[7:0] 0x43 DDS1_PW [15:8] DDS1_PHASE[15:8] 0x00 RW [7:0] DDS1_PHASE[7:0] 0x44 TRIG_TW_SEL [15:8] RESERVED[13:6] 0x00 RW [7:0] RESERVED[5:0] TRIG_DELAY_EN RESERVED 0x45 DDSx_CONFIG [15:8] DDS_COS_EN4 DDS_MSB_EN4 RESERVED DDS_COS_EN3 DDS_MSB_EN3 PHASE_MEM_EN3 RESERVED 0x00 RW [7:0] DDS_COS_EN2 DDS_MSB_EN2 RESERVED DDS_COS_EN1 DDS_MSB_EN1 RESERVED TW_MEM_EN 0x47 TW_RAM _CONFIG [15:8] RESERVED RESERVED 0x00 RW [7:0] RESERVED TW_MEM_SHIFT

Rev. B | Page 42 of 58 Addr (Hex) Register Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x50 START_DLY4 [15:8] START_DELAY4[15:8] 0x00 RW [7:0] START_DELAY4[7:0] 0x51 START_ADDR4 [15:8] START_ADDR4[11:4] 0x00 RW [7:0] START_ADDR4[3:0] RESERVED 0x52 STOP_ADDR4 [15:8] STOP_ADDR4[11:4] 0x00 RW [7:0] STOP_ADDR4[3:0] RESERVED 0x53 DDS_CYC4 [15:8] DDS_CYC4[15:8] 0x0001 RW [7:0] DDS_CYC4[7:0] 0x54 START_DLY3 [15:8] START_DELAY3[15:8] 0x00 RW [7:0] START_DELAY3[7:0] 0x55 START_ADDR3 [15:8] START_ADDR3[11:4] 0x00 RW [7:0] START_ADDR3[3:0] RESERVED 0x56 STOP_ADDR3 [15:8] STOP_ADDR3[11:4] 0x00 RW [7:0] STOP_ADDR3[3:0] RESERVED 0x57 DDS_CYC3 [15:8] DDS_CYC3[15:8] 0x0001 RW [7:0] DDS_CYC3[7:0] 00x58 START_DLY2 [15:8] START_DELAY2[15:8] 0x00 RW [7:0] START_DELAY2[7:0] 0x59 START_ADDR2 [15:8] START_ADDR2[11:4] 0x00 RW [7:0] START_ADDR2[3:0] RESERVED 0x5A STOP_ADDR2 [15:8] STOP_ADDR2[11:4] 0x00 RW [7:0] STOP_ADDR2[3:0] RESERVED 0x5B DDS_CYC2 [15:8] DDS_CYC2[15:8] 0x0001 RW [7:0] DDS_CYC2[7:0] 0x5C START_DLY1 [15:8] START_DELAY1[15:8] 0x00 RW [7:0] START_DELAY1[7:0] 0x5D START_ADDR1 [15:8] START_ADDR1[11:4] 0x00 RW [7:0] START_ADDR1[3:0] RESERVED 0x5E STOP_ADDR1 [15:8] STOP_ADDR1[11:4] 0x00 RW [7:0] STOP_ADDR1[3:0] RESERVED 00x5F DDS_CYC1 [15:8] DDS_CYC1[15:8] 0x0001 RW [7:0] DDS_CYC1[7:0] 00x60 CFG_ERROR [15:8] ERROR_CLEAR RESERVED[8:2] 0x00 R [7:0] RESERVED[1:0] DOUT_START_LG _ERR PAT_DLY_SHORT _ERR DOUT_START _SHORT_ERR PERIOD _SHORT_ERR ODD_ADDR _ERR MEM_READ _ERR 0x6000 to 0x6FFF SRAM_DATA [15:8] SRAM_DATA[11:4] 0x0000 RW [7:0] SRAM_DATA[3:0] RESERVED

Table 21. Bit Descriptions for SPICONFIG 0 MSB first per SPI standard (default). 1 LSB first per SPI standard.

13 RESET Executes software reset of SPI and controllers, reloads default register

values, except for Register 0x00. 1 Resets whole register map, except for Register 0x00.

0 The SPI port has only one data line and can be used as a 3-wire or 4-wire

1 The SPI port has two data lines: both bidirectional defining a pseudo dual

3-wire interface where CS and SCLK are shared between the two ports. This mode is only available for RAM data read or write. 0 Single SPI output drive ability. 1 Two-time drive ability on SPI output. 0 SDO/SDI2 function input/output.

2 RESETM1 Executes software reset of SPI and controllers, reloads default register

values, except for Register 0x00.

Table 22. Bit Descriptions for POWERCONFIG external voltage or provide external bandgap (BG) resistor. Table 23. Bit Descriptions for CLOCKCONFIG receiver, but maintains low jitter performance on DAC clock rising edge. The DAC clock falling edge is substantially degraded. allowing 180° phase shift in DAC1 update timing. allowing 180° phase shift in DAC2 update timing. allowing 180° phase shift in DAC3 update timing. allowing 180° phase shift in DAC4 update timing. Table 24. Bit Descriptions for REFADJ voltage from 800 mV to 1.2 V, respectively.

Table 25. Bit Descriptions for DAC4AGAIN

15 RESERVED 0 RW

7 RESERVED 0 RW

Table 26. Bit Descriptions for DAC3AGAIN Table 27. Bit Descriptions for DAC2AGAIN Table 28. Bit Descriptions for DAC1AGAIN Table 29. Bit Descriptions for DACxRANGE

Table 30. Bit Descriptions for DAC4RSET

15 DAC4_RSET_EN F or write, enable the internal RSET4 resistor for DAC4; for read, RSET4 for

DAC4 is enabled during calibration mode. Table 31. Bit Descriptions for DAC3RSET

15 DAC3_RSET_EN F or write, enable the internal RSET3 resistor for DAC3; for read, RSET3 for

DAC3 is enabled during calibration mode. Table 32. Bit Descriptions for DAC2RSET

15 DAC2_RSET_EN F or write, enable the internal RSET2 resistor for DAC2; for read, RSET2 for

DAC2 is enabled during calibration mode. Table 33. Bit Descriptions for DAC1RSET

15 DAC1_RSET_EN F or write, enable the internal RSET1 resistor for DAC1; for read, RSET1 for

DAC1 is enabled during calibration mode.

Table 34. Bit Descriptions for CALCONFIG Table 35. Bit Descriptions for COMPOFFSET

15 RESERVED 0x 00 RW

Table 36. Bit Descriptions for RAMUPDATE Table 37. Bit Descriptions for PAT_STATUS

Table 38. Bit Descriptions for PAT_TYPE

0 PATTERN_RPT Setting this bit allows the pattern to repeat the number of times

defined in DAC4_3PATx and DAC2_1PATx. 0 Pattern continuously runs.

1 Pattern repeats the number of times defined in DAC4_3PATx and

Table 39. Bit Descriptions for PATTERN_DLY cycles + 1. Minimum = 14. Maximum = 65535. Increment = 1. Table 40. Bit Descriptions for DAC4DOF Table 41. Bit Descriptions for DAC3DOF Table 42. Bit Descriptions for DAC2DOF Table 43. Bit Descriptions for DAC1DOF

Table 44. Bit Descriptions for WAV4_3CONFIG 0 Constant value held into DAC4 constant value MSB/LSB register.

1 Sawtooth defined in DAC4 sawtooth configuration register

0 Waveform read from RAM between START_ADDR4 and STOP_ADDR4. 2 Prestored waveform using START_DELAY4 and PATTERN_PERIOD. 3 Prestored waveform modulated by waveform from RAM. 0 Constant value held into DAC3 constant value MSB/LSB register.

1 Sawtooth defined in DAC3 sawtooth configuration register

0 Waveform read from RAM between START_ADDR3 and STOP_ADDR3. 2 Prestored waveform using START_DELAY3 and PATTERN_PERIOD. 3 Prestored waveform modulated by waveform from RAM. Table 45. Bit Descriptions for WAV2_1CONFIG 0 Constant value held into DAC2 constant value MSB/LSB register.

1 Sawtooth defined in DAC2 sawtooth configuration register

0 Normal operation for DAC2/DAC4. DAC4 output remains unchanged. 0 Waveform read from RAM between START_ADDR2 and STOP_ADDR2. 2 Prestored waveform using START_DELAY2 and PATTERN_PERIOD. 3 Prestored waveform modulated by waveform from RAM.

0 Constant value held into DAC1 constant value MSB/LSB register.

1 Sawtooth defined in DAC1 sawtooth configuration register

0 Normal operation for DAC1/DAC3. DAC3 output remains unchanged. 0 Waveform read from RAM between START_ADDR1 and STOP_ADDR1. 2 Prestored waveform using START_DELAY1 and PATTERN_PERIOD. 3 Prestored waveform modulated by waveform from RAM. Table 46. Bit Descriptions for PAT_TIMEBASE (0 = PATTERN_PERIOD LSB = 1 DAC clock period). (0 = START_DELAYx LSB = 1 DAC clock period). Table 47. Bit Descriptions for PAT_PERIOD Table 48. Bit Descriptions for DAC4_3PATx Table 49. Bit Descriptions for DAC2_1PATx

Table 50. Bit Descriptions for DOUT_START_DLY clock cycles. Minimum = 3. Maximum = 65535. Increment = 1. Table 51. Bit Descriptions for DOUT_CONFIG

5 DOUT_VAL M anually sets DOUT signal value, only valid when DOUT_MODE = 0

by Bit 5, DOUT_EN in Register 0x00, which must be set to use this feature. cycles. Minimum = 0. Maximum = 15. Increment = 1. Table 52. Bit Descriptions for DAC4_CST Table 53. Bit Descriptions for DAC3_CST Table 54. Bit Descriptions for DAC2_CST Table 55. Bit Descriptions for DAC1_CST

Table 56. Bit Descriptions for DAC4_DGAIN Table 57. Bit Descriptions for DAC3_DGAIN Table 58. Bit Descriptions for DAC2_DGAIN Table 59. Bit Descriptions for DAC1_DGAIN Table 60. Bit Descriptions for SAW4_3CONFIG Table 61. Bit Descriptions for SAW2_1CONFIG

Table 62. Bit Descriptions for DDS_TW32 Table 63. Bit Descriptions for DDS_TW1 Table 64. Bit Descriptions for DDS4_PW Table 65. Bit Descriptions for DDS3_PW Table 66. Bit Descriptions for DDS2_PW Table 67. Bit Descriptions for DDS1_PW Table 68. Bit Descriptions for TRIG_TW_SEL 0 Delay repeats for all patterns. 1 Delay is only at the start of first pattern.

0 RESERVED 0 RW

Table 69. Bit Descriptions for DDSx_CONFIG DDS4 MSB. Default is coming from DAC clock.

13 RESERVED 0 RW

12 RESERVED 0 RW

DDS3 MSB. Default is coming from DAC clock. 9 PHASE_MEM_EN3 E nable DDS3 phase offset input coming from RAM reading START_ADDR3. are taken into account. Default is coming from SPI map, DDS3_PHASE.

8 RESERVED 0 RW

DDS2 MSB. Default is coming from DAC clock.

5 RESERVED 0 RW

4 RESERVED 0 RW

DDS1 MSB. Default is coming from DAC clock.

1 RESERVED 0 RW

0 TW_MEM_EN Enable DDS tuning word input coming from RAM reading using

the TW_RAM_CONFIG register. Default is coming from the SPI map, DDSTW. Table 70. Bit Descriptions for TW_RAM_CONFIG

Table 71. Bit Descriptions for START_DLY4 Table 72. Bit Descriptions for START_ADDR4 Table 73. Bit Descriptions for STOP_ADDR4 Table 74. Bit Descriptions for DDS_CYC4 start and stop delays is selected for DAC4 output. Table 75. Bit Descriptions for START_DLY3 Table 76. Bit Descriptions for START_ADDR3 Table 77. Bit Descriptions for STOP_ADDR3 Table 78. Bit Descriptions for DDS_CYC3 stop delays is selected for DAC3 output.

Table 79. Bit Descriptions for START_DLY2 Table 80. Bit Descriptions for START_ADDR2 Table 81. Bit Descriptions for STOP_ADDR2 Table 82. Bit Descriptions for DDS_CYC2 start and stop delays is selected for DAC2 output. Table 83. Bit Descriptions for START_DLY1 Table 84. Bit Descriptions for START_ADDR1 Table 85. Bit Descriptions for STOP_ADDR1 Table 86. Bit Descriptions for DDS_CYC1 start and stop delays is selected for DAC1 output.

Table 87. Bit Descriptions for CFG_ERROR

5 DOUT_START_LG_ERR When DOUT_START is larger than pattern delay, this error

4 PAT_DLY_SHORT_ERR When pattern delay value is smaller than default value,

65536 − (14 − PATTERN_DELAY_SHORT).

3 DOUT_START_SHORT_ERR When DOUT_START value is smaller than default value,

2 PERIOD_SHORT_ERR When period register setting value is smaller than pattern

play cycle, this error is toggled.

1 ODD_ADDR_ERR When memory pattern play is not even in length in trigger

delay mode, this error flag is toggled.

0 MEM_READ_ERR When there is a memory read conflict, this error flag is

Table 88. Bit Descriptions for SRAM_DATA

Rev. B | Page 58 of 58 OUTLINE DIMENSIONS 0.50 0.40 0.30 02-22-2017-B 0.50 BSC BOTTOM VIEWTOP VIEW TOP VIEW PIN 1 INDICATOR 3 2 916 EXPOSED PAD SEATING PLANE

0.05 MAX

0.02 NOM

0.20 REF

0.08 0.30 0.25 0.18 5.10 5.00 SQ 4.90 0.80 0.75 0.70 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

0.25 MIN

3.75 3.60 SQ 3.55 COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5. PKG-004570 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) DETAIL A (JEDEC 95) Fi gure 61. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9106BCPZ −40°C to +85°C 32-Lead LFCSP CP-32-12 AD9106BCPZRL7 −40°C to +85°C 32-Lead LFCSP CP-32-12 AD9106-EBZ Ev aluation Board 1 Z = RoHS Compliant Part. ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11121-0-12/17(B)