AD9100

AD9100 Datasheet

Document overview

• Manufacturer or author: Hoka hey!
• PDF pages: 12

Technical content

62.3V CLAMP C HOLD 22pF VOUT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Ultrahigh Speed Monolithic Track-and-Hold AD9100*

FEATURES

Excellent Hold Mode Distortion into 250 V –88 dB @ 30 MSPS (2.3 MHz V IN) –83 dB @ 30 MSPS (12.1 MHz V IN) –74 dB @ 30 MSPS (19.7 MHz V IN) 16 ns Acquisition Time to 0.01% <1 ps Aperture Jitter

250 MHz Tracking Bandwidth

83 dB Feedthrough Rejection @ 20 MHz 3.3 nV/ √Hz Spectral Noise Density MlL-STD-Compliant Versions Available

APPLICATIONS

The AD9100 is a monolithic track-and-hold amplifier which sets a new standard for high speed and high dynamic range applications. It is fabricated in a mature high speed complemen- tary bipolar process. In addition to innovative design topologies, a custom package is utilized to minimize parasitics and optimize dynamic performance. Acquisition time (hold to track) is 13 ns to 0.1% accuracy, and 16 ns to 0.01%. The AD9100 boasts superlative hold-mode frequency domain performance; when sampling at 30 MSPS hold mode distortion is less than 83 dBfs for analog frequencies up to 12 MHz; and –74 dBfs at 20 MHz. The AD9100 can also drive capacitive loads up to 100 pF with little degradation in acquisition time; it is therefore well suited to drive 8- and 10-bit flash converters at clock speeds to 50 MSPS. With a spectral noise density of 3.3 nV/ √Hz and feedthrough rejection of 83 dB at 20 MHz, the AD9100 is well suited to enhance the dynamic range of many 8- to 16-bit systems. The AD9100 is “user friendly” and easy to apply: (1) it requires +5 V/–5.2 V power supplies; (2) the hold capacitor and switch power supply decoupling capacitors are built into the DIP pack- age; (3) the encode clock is differential ECL to minimize clock jitter; (4) the input resistance is typically 800 k Ω ; (5) the analog input is internally clamped to prevent damage from voltage transients. The AD9100 is available in a 20-lead side-brazed “skinny DIP” package. Commercial, industrial, and military temperature grade parts are available. Consult the factory for information about the availability of 883-qualified devices. PRODUCT HIGHLIGHTS 1. Hold Mode Distortion is guaranteed. 2. Monolithic construction. 3. Analog input is internally clamped to protect against over- voltage transients and ensure fast recovery. 4. Output is short circuit protected. 5. Drives capacitive loads to 100 pF. 6. Differential ECL clock inputs. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 *Patent pending.

REV. B–2– AD9100–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Conditions Temp Level Min Typ Max Units DC ACCURACY Gain ΔVIN = 2 V Full VI 0.989 0.994 V/V Offset V IN = 0 V Full VI –5 ± 1+ 5 m V Output Resistance 25 °C V 0.4 Ω Output Drive Capability Full VI ± 40 ± 60 mA PSRR ΔVS = 0.5 V p-p Full VI 48 55 dB Pedestal Sensitivity to Supply ΔVS = 0.5 V p-p Full VI 0.9 3 mV/V ANALOG INPUT/OUTPUT Output Voltage Range Full VI +2 ± 2.2 –2 V Input Bias Current 25 °CV I – 8 ± 3+ 8 µA Full VI –16 +16 µA Input Overdrive Current 2 VIN = ± 4 V; RIN = 50 Ω 25°CV ± 22 mA Input Capacitance 25 °C V 1.2 pF Input Resistance 25 °C, TMAX VI 350 800 k Ω TMIN VI 200 k Ω CLOCK/CLOCK INPUTS Input Bias Current CL/ CL = –1.0 V Full VI 4 5 mA Input Low Voltage (V IL) Full VI –1.8 –1.5 V Input High Voltage (V IH) Full VI –1.0 –0.8 V TRACK MODE DYNAMICS Bandwidth (–3 dB) V OUT ≤ 0.4 V p-p Full IV 150 250 MHz Slew Rate 4 V Step 25 °C IV 550 850 V/ µs

4 V Step Full IV 500 V/ µs

Overdrive Recovery Time 2 (to 0.1%) V IN = ± 4 V to 0 V 25 °CV 2 1 n s 2nd Harm. Dist. (20 MHz, 2 V p-p) Full V –65 dBc 3rd Harm. Dist. (20 MHz, 2 V p-p) Full V –75 dBc Integrated Output Noise (1-200 MHz) 25 °CV 4 5 µV RMS Spectral Noise @ 10 MHz 25 °C V 3.3 nV/ √Hz HOLD MODE DYNAMICS Worst Harmonic (2.3 MHz, 30 MSPS) V OUT = 2 V p-p 25 °C V –83 dBfs Worst Harmonic (12.1 MHz, 30 MSPS) V OUT = 2 V p-p 25 °C IV –80 –72 dBfs Worst Harmonic (12.1 MHz, 30 MSPS) V OUT = 2 V p-p T MAX IV –70 dBfs Worst Harmonic (12.1 MHz, 30 MSPS) V OUT = 2 V p-p T MIN IV –77 –68 dBfs Worst Harmonic (19.7 MHz, 30 MSPS) V OUT = 2 V p-p 25 °C V –74 dBfs Hold Noise3 25°C V 300 3 tH V/s rms Droop Rate4 VIN = 0 V 25 °CV I 11 0 ± mV/µs TMIN VI 7 40 ± mV/µs TMAX VI 5 30 ± mV/µs Feedthrough Rejection (20 MHz) V IN = 2 V p-p Full V 83 dB TRACK-TO-HOLD SWITCHING Aperture Delay 25 °C V +800 ps Aperture Jitter 25 °CV <1p s Pedestal Offset V IN = 0 V 25 °CV I – 8 ± 1+ 8 m V Full VI –10 +10 mV Transient Amplitude V IN = 0 V Full V ± 6m V Settling Time to 1 mV Full IV 7 10 ns Glitch Product V IN = 0 V 25 °C V 15 pV-s HOLD-TO-TRACK SWITCHING Acquisition Time to 0.1% 2 V Step 25 °CV 1 3 n s Acquisition Time to 0.01% 2 V Step Full IV 16 23 ns Acquisition Time to 0.01% 4 V Step 25 °CV 2 0 n s POWER SUPPLY Power Dissipation Full VI 1.05 1.25 W +VS Current Full VI 96 118 mA –VS Current Full VI 116 132 mA NOTES 1AD9100JD: 0 °C to +70 °C. AD9100AD: –40 °C to +85 °C. AD9100SD: –55 °C to +125 °C. DIP θJA = 38 °C/W; this is valid with the device mounted flush to a grounded 2 oz. copper clad board with 16 sq. inches of surface area and no air flow. 2The input to the AD9100 is internally clamped at ± 2.3 V. The internal input series resistance is nominally 50 Ω . 3Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t H) is 20 ns, the accumulated noise is typically 6 µV (300 V/s 3 20 ns). This value must be combined with the track mode noise to obtain total noise. 4Min and max droop rates are based on the military temperature range (–55 °C to +125 °C). Refer to the “Droop Rate vs Temperature” chart for min/max limits over the commercial and industrial ranges. Specifications subject to change without notice. (unless otherwise noted, +VS = +5 V; –VS = –5.2 V; RLOAD = 100 V; RIN = 50 V)

III – Periodically sample tested. V – Parameter is a typical value only. extremes for commercial/industrial devices. *Consult factory about availability of parts screened to MIL-STD-883. accumulate on the human body and test equipment and can discharge without detection. precautions are recommended to avoid performance degradation or loss of functionality. Figure 1. Timing Diagram (1 ns/div) conditions for an extended period of time may affect device reliability. 2Analog input voltage should not exceed ± VS.

REV. B–4– PIN FUNCTION DESCRIPTIONS/CONNECTIONS Pin No. Description Connection 1– V S –5.2 V Power Supply 2, 3, 8, 10–13, 17 GND Common Ground Plane 4V IN Analog Input Signal 5, 7 –V S –5.2 V Power Supply 6, 15 BYPASS 0.1 µF to Ground 9V OUT Track-and-Hold Output 14, 16, 20 +V S +5 V, Power Supply

18 CLK Complement ECL Clock

19 CLK “True” ECL Clock

(NOTE 3) 23456789101112 3214 18 19 20 21 22 23 24 25 26 S CAP (NOTE 1) CLOCK GND NC BYPASS (NOTE 2) AD9100 TOP VIEW (Not to scale) +VS+VS+VS +VS+VS +VS BYPASS (NOTE 2) +VS +VOUT –VS–VIN–VS –VS CAP (NOTE 1) –VS SIZE = 148 3 63 3 15 mils NC = NO CONNECT NOTES: 1. SUPPLY BYPASS CAPACITOR; 0.01 TO 0.1mF CERAMIC CONNECTED TO GROUND. 2. 0.01mF CERAMIC CONNECTED BETWEEN PAD 29 AND PAD 31. 3. HOLD CAPACITOR CONNECTED FROM PAD 4 AND PAD 5 TO GROUND; 10–100pF, NOMINALLY 22pF. DIP PACKAGE DOES NOT REQUIRE EXTERNAL HOLD CAPACITOR. 113 BYPASS –VS GND +VS CLK –VS –VS +V S BYPASS +V S GND VIN CLK GND GND GND VOUT GND GND GND TOP VIEW (Not to Scale) AD9100 PIN CONFIGURATION 20-Lead Side-Brazed Ceramic DIP TERMINOLOGY Analog Delay is the time required for an analog input signal to propagate from the device input to output. Aperture Delay tells when the input signal is actually sampled. It is the time difference between the analog propagation delay of the front-end buffer and the control switch delay time. (The time from the hold command transition to when the switch is opened.) For the AD9100, this is a positive value which means that the switch delay is longer than the analog delay. Aperture Jitter is the random variation in the aperture delay. This is measured in ps-rms and results in phase noise on the held signal. Droop Rate is the change in output voltage as a function of time (dV/dt). It is measured at the AD9100 output with the device in hold mode and the input held at a specified dc value, the measurement starts immediately after the T/H switches from track to hold. Feedthrough Rejection is the ratio of the input signal to the output signal when in hold mode. This is a mea- sure of how well the switch isolates the input signal from feeding through to the output. Hold-to-Track Switch Delay is the time delay from the track command to the point when the output starts to change and acquire a new signal. Pedestal Offset is the offset voltage step measured immediately after the AD9100 is switched from track to hold with the input held at zero volts. It manifests itself as an added offset during the hold time. Track-to-Hold Settling Time is the time necessary for the track to hold switching transient to settle to within 1 mV of its final value. Track-to-Hold Switching Transient is the maximum peak switch induced transient voltage which appears at the AD9100 output when it is switched from track to hold.

error band at the hold capacitor. the overall AD9100 acquisition time. Figure 13. Acquisition Time Diagram referenced to the hold capacitor. total; in hold mode, it contributes only 1.8 ns (as stated above). to optimize the encoder’s performance. maximum sampling rate and input frequency. sient is typically only 6 mV and settles to less than 1 mV in 7 ns. extremely high input resistance and very low droop sensitivity vs. correction and results in low distortion under heavy loads.

2 V step) ensures that the output buffer does not limit the

AD9100 hold mode distortion levels for loads as low as 250 Ω .

Figure 21. Acquisition Time Figure 22. Output Acquisition Time Figure 23. Frequency (500 kHz/Division) Analog Input = Figure 24. Frequency (500 kHz/Division) Analog Input =

2.3 MHz

4 PLACES

Figure 26. Bottom of AD9100/PCB Evaluation Board Viewed Figure 28. Top of AD9100/PCB Evaluation Board Viewed Figure 25. Frequency (500 kHz/Division) Analog Input =

12.1 MHz

Figure 27. Frequency (500 kHz/Division) Analog Input =

19.8 MHz

REV. B–12– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C1513a–0–6/98PRINTED IN U.S.A. 20-Lead Side-Brazed Ceramic DIP (D-20) 1 10 PIN 1 IDENTIFIER 0.100 (2.54) TYP SEATING PLANE 0.150 (3.81) MIN 0.290 6 0.010 (7.366 6 0.254) 0.05 (1.27) TYP 0.020 (0.51) 0.016 (0.41) 0.020 6 0.005 (0.508 6 0.127) 1.052 6 0.011 (26.721 6 0.279) 0.175 (4.45) MAX 0.010 6 0.002 (0.254 6 0.051) 0.300 (7.62) REF