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REV. a AD9058 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781/329-4700 www.analog.com Fax: © Analog Devices, Inc. All rights reserved. Dual 8-Bit 50 MSPS A/D Converter FUNCTIONAL BLOCK DIAGRAM B –VREF AIN ENCODE +VREF 8-BIT ANALOG- TO-DIGIT AL CONVERTER 8-BIT ANALOG- TO-DIGIT AL CONVERTER +VREF ENCODE AIN –VREF A AD9058 2VREF QUADRATURE RECEIVER Q LO I AD9058 G G 90/H11543RF GENERAL DESCRIPTION The AD9058 combines two independent, high performance, 8-bit analog-to-digital converters (ADCs) on a single monolithic IC. Combined with an optional on-board voltage reference, the AD9058 provides a cost-effective alternative for systems requiring two or more ADCs. Dynamic performance (SNR, ENOB) is optimized to provide up to 50 MSPS conversion rates. The unique architecture results in low input capacitance while maintaining high per- formance and low power (<0.5 W/channel). Digital inputs and outputs are TTL compatible. Performance has been optimized for an analog input of 2 V p-p (±1 V; 0 V to 2 V). Using the on-board 2 V voltage reference, the AD9058 can be set up for unipolar positive operation (0 V to 2 V). This internal voltage reference can drive both ADCs. Commercial (0°C to 70°C) and military (–55 °C to +125 °C) temperature range parts are available. Parts are supplied in hermetic 48-lead DIP and 44-lead “J” lead packages.

FEATURES

2 Matched ADCs on Single Chip

50 MSPS Conversion Speed

On-Board Voltage Reference Low Power (<1 W) Low Input Capacitance (10 pF)

65 V Power Supplies

APPLICATIONS

Quadrature Demodulation for Communications Digital Oscilloscopes Electronic Warfare Radar E 2012 781/461-3113

REV. –2– AD9058–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

[/H11550VS = /H115505 V; VREF = 2 V (internal); ENCODE = 40 MSPS; A IN = 0 V to 2 V; –VREF = GROUND, unless otherwise noted.] 1 All specifications apply to either of the two ADCs. Test AD9058AJD/AJJ AD9058AKD/AKJ Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25 °C I 0.25 0.65 0.25 0.5 LSB Full VI 0.8 0.7 LSB Integral Nonlinearity 25 °C I 0.5 1.3 0.5 1.0 LSB Full VI 1.4 1.25 LSB No Missing Codes Full VI Guaranteed Guaranteed ANALOG INPUT Input Bias Current 25 °C I 75 170 75 170 μA Full VI 340 340 μA Input Resistance 25 °C I 12 28 12 28 k Ω Input Capacitance 25 °CI V 1 0 1 5 1 0 1 5 p F Analog Bandwidth 25 °C V 175 175 MHz REFERENCE INPUT Reference Ladder Resistance 25 °C I 120 170 220 120 170 220 Ω Full VI 80 270 80 270 Ω Ladder Tempco Full V 0.45 0.45 Ω/°C Reference Ladder Offset 25 °CI 8 1 6 8 1 6 m V (Top) Full VI 24 24 mV Reference Ladder Offset 25 °CI 8 2 3 8 2 3 m V (Bottom) Full VI 33 33 mV Offset Drift Coefficient Full V 50 50 μV/°C INTERNAL VOLTAGE REFERENCE Full VI 1.90 2.25 1.90 2.25 V Temperature Coefficient Full V 150 150 μV/°C Power Supply Rejection Ratio (PSRR) 25 °C I 10 25 10 25 mV/V SWITCHING PERFORMANCE Maximum Conversion Rate 2 25°C I 50 50 60 MSPS Aperture Delay Matching 25 °C IV 0.2 0 5 0.2 0.5 ns Aperture Uncertainty (Jitter) 25 °C V 10 10 ps, rms Output Delay (Valid) (t V)2 25°CI 8 5 8 n s Output Delay (tV) Tempco Full V 16 16 ps/ °C Propagation Delay (t PD)2 25°C I 12 12 19 ns Propagation Delay (t PD) Tempco Full V –16 –16 ps/ °C Output Time Skew 25 °CV 1 1 n s ENCODE INPUT Logic “1” Voltage Full VI 2 2 V Logic “0” Voltage Full VI 0.8 0.8 V Logic “1” Current Full VI 600 600 μA Logic “0” Current Full VI 1000 1000 μA Input Capacitance 25 °CV 5 5 p F Pulsewidth (High) 25 °CI 8 8 n s Pulsewidth (Low) 25 °CI 8 8 n s E

REV. –3– AD9058 Test AD9058AJD/AJJ AD9058AKD/AKJ Parameter Temp Level Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Transient Response 25 °CV 2 2 n s Overvoltage Recovery Time 25 °CV 2 2 n s Effective Number of Bits (ENOB) 3 Analog Input @ 2.3 MHz 25 °C I 7.7 7.2 7.7 Bits @ 10.3 MHz 25 °C I 7.4 7.1 7.4 Bits Signal-to-Noise Ratio 3 Analog Input @ 2.3 MHz 25 °C I 48 45 48 dB @ 10.3 MHz 25 °C I 46 44 46 dB Signal-to-Noise Ratio 3 (Without Harmonics) Analog Input @ 2.3 MHz 25 °C I 48 46 48 dB @ 10.3 MHz 25 °C I 47 45 47 dB Second Harmonic Distortion Analog Input @ 2.3 MHz 25 °C I 58 48 58 dBc @ 10.3 MHz 25 °C I 58 48 58 dBc Third Harmonic Distortion Analog Input @ 2.3 MHz 25 °C I 58 50 58 dBc @ 10.3 MHz 25 °C I 58 50 58 dBc Crosstalk Rejection4 25°C IV 60 48 60 dBc DIGITAL OUTPUTS Logic “1” Voltage (IOH = 2 mA) Full VI 2.4 2.4 V Logic “0” Voltage (IOL = 2 mA) Full VI 0.4 0.4 V POWER SUPPLY5 +VS Supply Current Full VI 127 154 127 154 mA –VS Supply Current Full VI 27 38 27 38 mA Power Dissipation Full VI 770 960 770 960 mW NOTES 1For applications in which +V S may be applied before –V S, or +V S current is not limited to 500 mA, a reverse-biased clamping diode should be inserted between ground and –V S to prevent destructive latch up. See section entitled “Using the AD9058.” 2To achieve guaranteed conversion rate, connect each data output to ground through a 2 k Ω pull-down resistor. 3SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and EN OB measured with analog in put signal 1 dB below full scale at specified frequency. 4Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. Wi th both signals synchronously encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT. 5Applies to both A/Ss and includes internal ladder dissipation. Specifications subject to change without notice. E

REV. AD9058 –4– EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25 °C, and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25 °C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. DIGIT AL BITS +VS Equivalent Digital Outputs ENCODE 13k/H9024 Equivalent Encode Circuit AD9058 ENCODE AIN –VREF +VS –VS –5.2V +5V GROUND COMP +VREF +VINT D0–D7*+VS ** INDICA TES EACH PIN IS CONNECTED THROUGH 100/H9024 * INDICA TES EACH PIN IS CONNECTED THROUGH 2k/H9024 0.1/H9262F Burn-In Connections ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature Range Maximum Junction Temperature 3 NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2For applications in which +V S may be applied before –V S, or +V S current is not limited to 500 mA, a reverse-biased clamping diode should be inserted between ground and –V S to prevent destructive latch up. See section entitled “Using the AD9058.” 3Typical thermal impedances: 44-lead hermetic J-leaded ceramic package: θJA = 86.4°C/W; θJC = 24.9°C/W; 48-lead hermetic: DIP θJA = 40°C/W; θJC = 12°C/W. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE E

REV. AD9058 –5– 18 28 GROUND GROUND +VREF COMP NC ENCODE GROUND GROUND GROUND NC GROUND ENCODE D7 (MSB) TOP VIEW (Not to Scale) AD9058 NC = NO CONNECT GROUND +VINT +VREF +VS AIN AIN +VS +VS +VS –VREF –VS –VREF –VS +VS –VS–VS +VS D7 (MSB) D0 (LSB) D0 (LSB) D1D1 AD9058AJJ/AKJ Pinouts TOP VIEW (Not to Scale) AD9058 NC = NO CONNECT GROUND D 7 (MSB) ENCODE D 6 +VS D5 GROUND D 4 –VREF D3 –VS D2 NC D 1 AIN D0 (LSB) +VS GROUND GROUND –V S +VREF GROUND COMP +V S +VINT +VS +VREF GROUND GROUND –V S +VS GROUND AIN D0 (LSB) NC D 1 –VREF D3 GROUND D 4 +VS D5 ENCODE D 6 GROUND D 7 (MSB) –VS AD9058AJD/AKD Pinouts PIN FUNCTION DESCRIPTIONS J-Lead Ceramic DIP Pin Number Pin Number ADC-A ADC-B Mnemonic Function ADC-A ADC-B 34 3 + V REF Top of Internal Voltage Reference Ladder 14 11 4 42 GROUND Analog Ground Return 15 10 54 1 + V S Positive 5 V Analog Supply Voltage 16 9 64 0 A IN Analog Input Voltage 17 8 73 9 – V S Negative 5 V Supply Voltage 19 6 83 8 – V REF Bottom of Internal Voltage Reference Ladder 20 5 93 7 + V S Positive 5 V Digital Supply Voltage 22 3 10 36 ENCODE TTL Compatible Convert Command 23 2 11 35 D 7 (MSB) Most Significant Bit of TTL Digital Output 25 48 12–17 34–29 D 6–D1 TTL Compatible Digital Output Bits 26–31 47–42 18 28 D 0 (LSB) Least Significant Bit of TTL Digital Output 32 41 19 27 GROUND Digital Ground Return 21, 24, 33 1, 4, 40 20 26 –V S Negative 5 V Supply Voltage 34 39 21 25 GROUND Analog Ground Return 35 38 22 24 +V S Positive 5 V Analog Supply Voltage 36 37 COMMON PINS COMMON PINS 1 COMP Connection for External (0.1 μF) 12 Compensation Capacitor 2+ V INT Internal 2 V Reference; Can Drive 13 +VREF for Both ADCs PIN CONFIGURATIONS E

Figure 3. AD9058 Using External Voltage References that has sufficient drive capability for both reference ladders. AD9058 for unipolar positive operation (0 V to 2 V). is shown configured for ±1 V operation. designed into the reference circuit for the AD9058. power, the data outputs have relatively slow rise and fall times. and hold times; and (2) the intervals when data is changing.

40 MSPS, these resistors help equalize rise and fall times and

recommended choices for speeds of 40 MSPS or more. nected together and to the ground plane at the AD9058 device. through 0.1 μF ceramic capacitors as close to the unit as possible.

REV. AD9058 –9– S ENCODE D7 (MSB) –VREF –VS +VS GROUND GROUND GROUND GROUND +VS –VS –VS +VS D0 (LSB) D0 (LSB) GROUND GROUND +VREF +VREF +VS AIN AIN +VS ENCODE +VS –VREF –VS D7 (MSB) MECHANICAL INFORMATION E COMP +VINT

Rev. E | Page 10 OUTLINE DIMENSIONS 44-Lead Ceramic Leaded Chip Carrier — J-Formed Leads [JLCC] (J-44) Dimensions shown in inches and (millimeters) 48-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-48) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 Temperature Range Package Description Package Option2 AD9058AJJ 0°C to 70°C 44-Lead JLCC J-44 AD9058AJJ-REEL 0°C to 70°C 44-Lead JLCC J-44 AD9058AKJ 0°C to 70°C 44-Lead JLCC J-44 AD9058ATJ/883B –55°C to +125°C 44-Lead JLCC J-44 AD9058AJD 0°C to 70°C 48-Lead SBDIP D-48 AD9058AKD 0°C to 70°C 48-Lead SBDIP D-48 AD9058ATD/883B –55°C to +125°C 48-Lead SBDIP D-48 1 For AD9058ATJ/883B and AD9058ATD/883B specifications, refer to Analog Devices Military Products Databook. 2 D = Hermetic ceramic DIP package; J = leaded ceramic package. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 177 PIN 1 TOP VIEW 0.662 (16.82) 0.628 (15.95)SQ 0.700 (17.78) 0.680 (17.27) SQ 0.050 (1.27) BSC 0.500 (12.70) 0.492 (12.50) 0.650 (16.51) 0.610 (15.49) 0.023 (0.58) 0.013 (0.33) 0.025 (0.64) MIN 0.078 (1.98) 0.054 (1.37) 0.135 (3.43) 0.100 (2.54) 0.032 (0.81) 0.020 (0.51) BOTTOM VIEW PIN 1 INDEX 0.065 (1.65) 0.040 (1.02) REF  45°

3 PLACES

0.020 (0.51) REF  45° 12 4 0.620 (15.75) 0.590 (14.99) PIN 1 0.098 (2.49) MAX0.005 (0.13) MIN SEATING PLANE 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) 0.030 (0.76) 0.150 (3.81) MIN 0.225 (5.72) MAX 2.424 (63.57) MAX 0.110 (2.79) 0.090 (2.29) 0.630 (16.00) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Rev. E | Page 11

REVISION HISTORY

9/12—Rev. D to Rev. E 5/03—Rev. C to Rev. D 6/01—Rev. B to Rev. C ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00562-0-9/12(E)