AD9054PCB

AD9054 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9054 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997 8-Bit, 200 MSPS A/D Converter FUNCTIONAL BLOCK DIAGRAM ENCODE TIMINGENCODE AD9054 T/H AIN AIN GND 12.5V REFERENCE ENCODE LOGIC DEMULTIPLEXER VDD DSDSDEMUX QUANTIZER VREF IN VREF OUT DA 7–DA 0 DB 7–DB 0

FEATURES

200 MSPS Guaranteed Conversion Rate

135 MSPS Low Cost Version Available

350 MHz Analog Bandwidth

1 V p-p Analog Input Range

Internal +2.5 V Reference and T/H Low Power: 500 mW +5 V Single Supply Operation TTL Output Interface Single or Demultiplexed Output Ports

APPLICATIONS

Digital Data Storage Read Channels Digital Communications Digital Instrumentation Medical Imaging GENERAL DESCRIPTION The AD9054 is an 8-bit monolithic analog-to-digital converter optimized for high speed, low power, small size and ease of use. With a 200 MSPS encode rate capability and full-power analog bandwidth of 350 MHz, the component is ideal for applications requiring the highest possible dynamic performance. To minimize system cost and power dissipation, the AD9054 includes an internal +2.5 V reference and track-and-hold circuit. The user provides only a +5 V power supply and an encode clock. No external reference or driver components are required for many applications. The AD9054’s encode input interfaces directly to TTL, CMOS or positive-ECL logic and will operate with single-ended or differential inputs. The user may select dual-channel or single- channel digital outputs. The dual (demultiplexed) mode inter- leaves ADC data through two 8-bit channels at one-half the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces while allowing the ADC to be clocked to the full 200 MSPS conversion rate. In the single- channel (nondemultiplexed) mode, all data is piped at the full clock rate to the Channel A outputs. Fabricated with an advanced BiCMOS process, the AD9054 is provided in a space-saving 44-lead TQFP surface mount plastic package (ST-44) and specified over the full industrial (–40 °C to +85°C) temperature range.

–2– REV. 0 AD9054–SPECIFICATIONS ELECTRICAL CHARACTERISTICS(VDD = +5 V, external reference, f S = max unless otherwise noted) Test AD9054BST-200 AD9054BST-135 Parameter Temp Level Min Typ Max Min Typ Max Units RESOLUTION 8 8 Bits DC ACCURACY Integral Nonlinearity +25 °CI ± 0.6 ± 1.5 ± 0.6 ± 1.5 LSB Full VI ± 0.9 ± 2.0 ± 0.9 ± 2.0 LSB No Missing Codes Full VI Guaranteed Guaranteed Gain Error1 +25°CI ± 2 ± 7 ± 2 ± 7% F S Gain Tempco1 Full V 160 160 ppm/ °C ANALOG INPUT Input Voltage Range (With Respect to AIN) Full V ± 512 ± 512 mV p–p Compliance Range AIN or AIN Full V 1.8 3.2 1.8 3.2 V Input Offset Voltage +25 °CI ± 4 ± 16 ± 4 ± 16 mV Full VI ± 8 ± 19 ± 8 ± 19 mV Input Resistance +25 °C I 36 62 36 62 k Ω Full VI 23 23 k Ω Input Capacitance +25 °CV 4 4 p F Input Bias Current +25 °C I 25 50 25 50 µA Full VI 75 75 µA Analog Bandwidth, Full Power 2 +25°C V 350 350 MHz REFERENCE OUTPUT Temperature Coefficient Full V 110 110 ppm/ °C SWITCHING PERFORMANCE Maximum Conversion Rate (f S) Full VI 200 135 MSPS Minimum Conversion Rate (f S) Full IV 25 25 MSPS Encode Pulsewidth High (t EH) +25 °C IV 2.0 15 3.0 15 ns Encode Pulsewidth Low (t EL) +25 °C IV 2.0 15 3.0 15 ns Aperture Delay (t A) +25 °C V 0.5 0.5 ns Aperture Uncertainty (Jitter) +25 °C V 2.3 2.3 ps rms Data Sync Setup Time (t SDS) +25 °CI V 0 0 n s Data Sync Hold Time (t HDS) +25 °C IV 0.5 0.5 ns Data Sync Pulsewidth (t PWDS) +25 °C IV 2.0 2.0 ns Output Valid Time (t V)3 Full VI 2.7 5.1 2.7 5.7 ns Output Propagation Delay (t PD)3 Full VI 5.9 7.9 7.5 8.5 ns DIGITAL INPUTS HIGH Level Current (I IH)4 Full VI 500 625 500 625 µA LOW Level Current (I IL)4 Full VI 500 625 500 625 µA Input Capacitance +25 °CV 3 3 p F DIFFERENTIAL INPUTS Differential Signal Amplitude (VID) Full IV 400 400 mV HIGH Input Voltage (V IHD) Full IV 1.5 V DD 1.5 V DD V LOW Input Voltage (V ILD) Full IV 0 V DD – 0.4 0 V DD – 0.4 V Common-Mode Input (V ICM) Full IV 1.5 1.5 V DEMUX INPUT HIGH Input Voltage (V IH) Full IV 2.0 V DD 2.0 V DD V LOW Input Voltage (V IL) Full IV 0 0.8 0 0.8 V DIGITAL OUTPUTS HIGH Input Voltage (V OH) Full VI 2.4 2.4 V LOW Input Voltage (V OL) Full VI 0.4 0.4 V Output Coding Binary Binary

–3–REV. 0 AD9054 Test AD9054BST-200 AD9054BST-135 Parameter Temp Level Min Typ Max Min Typ Max Units POWER SUPPLY VDD Supply Current (I DD) Full VI 100 145 100 140 mA Power Dissipation 5, 6 Full VI 500 725 500 700 mW Power Supply Sensitivity 7 +25°C I 0.005 0.015 0.005 0.015 V/V DYNAMIC PERFORMANCE 8 Transient Response +25 °C V 1.5 1.5 ns Overvoltage Recovery Time +25 °C V 1.5 1.5 ns Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 19.7 MHz +25 °CI V 4 2 4 5 4 2 4 5 d B Full V 45 45 dB fIN = 49.7 MHz +25 °C I 42 45 42 45 dB Full V 45 45 dB fIN = 70.1 MHz +25 °C I 42 45 dB Full V 45 dB Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 19.7 MHz +25 °CI V 4 0 4 3 4 0 4 3 d B Full V 43 43 dB fIN = 49.7 MHz +25 °C I 40 43 40 43 dB Full V 43 43 dB fIN = 70.1 MHz +25 °C I 39 42 dB Full V 42 dB Effective Number of Bits fIN = 70.1 MHz +25 °C I 6.18 6.85 Bits 2nd Harmonic Distortion fIN = 19.7 MHz +25 °C IV 58 63 58 63 dBc fIN = 49.7 MHz +25 °C I 54 59 54 59 dBc fIN = 70.1 MHz +25 °C I 52 55 dBc 3rd Harmonic Distortion fIN = 19.7 MHz +25 °C IV 48 56 48 56 dBc fIN = 49.7 MHz +25 °C I 48 54 48 54 dBc fIN = 70.1 MHz +25 °C I 43 50 dBc Two-Tone Intermod Distortion (IMD) fIN = 19.7 MHz +25 °C V 60 60 dBc fIN = 49.7 MHz +25 °C V 55 55 dBc fIN = 70.1 MHz +25 °C V 50 dBc NOTES 1Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 23 dB bandwidth with full-power input signal. 3tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels of the digital outputs. The output ac load du ring test is 5 pF (Refer to equivalent circuits Figures 5 and 6). 4IIH and IIL are valid for differential input voltages of less than 1.5 V. At higher differential voltages, the input current will increase to a maximum of 1.25 mA. 5Power dissipation is measured under the following conditions: analog input is –1 dBfs at 19.7 MHz. 6Typical thermal impedance for the ST-44 (TQFP) 44–lead package (in still air): θJC = 20°C/W, θCA = 35°C/W, θJA = 55°C/W. 7A change in input offset voltage with respect to a change in V DD. 8SNR/harmonics based on an analog input voltage of –1.0 dBfs referenced to a 1.024 V full–scale input range. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at +25 °C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at +25 °C; guaranteed by design and characterization testing for industrial temperature range.

–4– REV. 0 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9054 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS* *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table I. Output Coding Step AIN– AIN Code Binary 255 ≥0.512 V 255 1111 1111 254 0.508 V 254 1111 1110 253 0.504 V 253 1111 1101

• • • •
• • • •
• • • • 129 0.006 V 129 1000 0001 128 0.002 V 128 1000 0000 127 –0.002 V 127 0111 1111 126 –0.006 V 126 0111 1110
• • • •
• • • •
• • • • 2 –0.504 V 2 0000 0010 1 –0.508 V 1 0000 0001 0 ≤–0.512 V 0 0000 0000 ORDERING GUIDE Temperature Package Model Range Option* AD9054BST-200 –40 °C to +85°C ST-44 AD9054BST-135 –40 °C to +85°C ST-44 AD9054/PCB +25 °C Evaluation Board *ST = Plastic Thin Quad Flatpack (TQFP). PIN FUNCTION DESCRIPTIONS Pin Number Name Function

1 ENCODE Encode Clock for ADC (ADC

ENCODE).

2 ENCODE Encode Clock Complement

(ADC Samples on Falling Edge of ENCODE). 3, 5, 15, 18, 28, VDD Power Supply (+5 V). 30, 31, 36, 41 4, 6, 16, 17, 27, GND Ground. 29, 32, 35, 37, 40 14–7 DA 0–DA7 Digital Outputs of ADC Channel A. DA7 is the MSB, DA0 the LSB. 19–26 DB 0–DB7 Digital Outputs of ADC Channel B. DB7 is the MSB, DB0 the LSB.

33 VREF OUT Internal Reference Output

(+2.5 V typical); Bypass with 0.1 µF to Ground. 34 VREF IN Refe rence Input for ADC (+2.5 V typical, ± 4%). 38 AIN Analog Input—Complement. Connect to input signal midscale reference. 39 AIN Analog Input—True. 42 DEMUX Format Select. LOW = Dual. Channel Mode, HIGH = Single. Channel Mode (Channel A Only). 43 DS Data Sync Complement.

44 DS Data Sync—Aligns output chan-

nels in Dual-Channel Mode. PIN CONFIGURATION WARNING! ESD SENSITIVE DEVICE PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) DB 1 DB 2 DB 3 GND DA 2 DA 1 DA 0 (LSB) VDD GND VDD DB 0 (LSB) VREF OUT GND VDD VDD GND VDD GND ENCODE ENCODE VDD GND VDD GND DA 7 (MSB) DA 6 DA 5 DA 4 DA 3 DB 7 (MSB) DB 6 DB 5 DB 4 DS DS DEMUX VDD GND AIN AIN GND VDD GND VREF IN AD9054

bined into the eight-bit result. conditions described in the Timing section. Track/Hold circuit processes these signals without difficulty. VREF IN pin should also be decoupled by a 0.1 µF capacitor. guaranteed sampling rate, the T/H droop becomes excessive. degraded linearity at even lower frequencies. ing at twice the desired rate is not high. verters as might be required in a triple video converter application. 1.1264 V. The new input range will then be AIN ± 0.5632 V. to maintain a threshold appropriate for TTL or CMOS logic. Figure 33. Reference Voltage vs. Temperature

tion on the rising edge can be ignored. each graphics line or frame. parallel by adding a register stage to the output. sample is taken (five pipeline delays). Figure 36. Dual Port Mode—Aligned Output Data time the A Port with the synchronizing latch.

• DC-Coupled Analog Input
• Demuxed Outputs
• Differential Clocks
• Internal Voltage Reference. VREF OUT VREF IN AIN AIN DEMUX AD9054 DS DS ENC ENC A PORT '574 A PORT '574 DAC CLK A CLK BCLOCKING ENC ENC S102 VREF EXT S103 DC BIAS 50V AIN D FF D C RESET BUTTON CLK A CLK B S104 S105 ENC 50V ENC 50V

Figure 37. PCB Block Diagram

1. DC-coupled through an AD9631 op amp; this is the mode in
2. Differential TTL, CMOS, or PECL; it is shipped in this
3. Single-ended TTL or CMOS. To use in this mode, remove

input, and insert a 0.1 µF ceramic capacitor into the C5 slot. tors to 1.5 V, but it can be externally driven to any dc voltage. Dual Port). The maximum speed in this mode is 200 MSPS. board’s latch clocks with the data coming out of the AD9054. A only. Output Port B is not reconstructed.

• Check that all jumpers are in the correct position for the desired mode of operation.
• Push the reset button. This will align the 9054’s data output with the half speed latch clocks.
• Switch the jumper S105 from A-R to R-B or vice-versa, then push the reset button. In demuxed mode, this will have the effect of inverting the half speed latch clocks.
• At high encode rates, the evaluation board’s clock generation circuitry is sensitive to the +5 V digital power supply. At high encode rates, the +5 V digital power should be kept below +5.2 V. This is an evaluation board sensitivity and not an AD9054 sensitivity. The AD9054 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warran- ties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.

Figure 38. Evaluation Board Schematic

–17–REV. 0 BILL OF MATERIALS GS00104 REV. B ITEM QTY PART NUMBER REFERENCE DESCRIPTION MFG/DISTRIBUTOR 11 30 GRM40Z5U104M050BL C1, C2, C4, C6–8, 0.1 µF CER CHIP CAP 0805 TTI C10–C22, C24–C29, C31–C35 12 1 P10FBK-ND R5 10 Ω SURFACE MT RES 1206 DIGI-KEY 13 21 P100FBK-ND R3, R9, R21–R39 100 Ω SURFACE MT RES 1206 DIGI-KEY 14 4 T491C106M016AS C3, C9, C23, C30 10 µF TANTALUM CHIP CAP TTI 15 2 P140FBK-ND R2, R4 140 Ω SURFACE MT RES 1206 DIGI-KEY 16 1 P1KFBK-ND R12 1 k Ω SURFACE MT RES 1206 DIGI-KEY 17 3 P2KFBK-ND R6, R8, R14 2 k Ω SURFACE MT RES 1206 DIGI-KEY 18 1 3296W-102-ND R7 1k TRIM POT TOP ADJ, 25 TURN DIGI-KEY 19 1 K44-C37S-QJ J6 37P D CONN RT ANG PCMT FEM CENTURY ELEC 10 5 P49.9FBK-ND R1, R10, R11, 49.9 Ω SURFACE MT RES 1206 DIGI-KEY R15, R16 11 1 CSC06A-01-511G RP1 510 Ω 6P BUSED RES NETWORK TTI 12 1 51F54113 TB1 8291Z 3-PIN TERMINAL BLOCK NEWARK 13 1 51F54112 TB1 8291Z 2-PIN TERMINAL BLOCK NEWARK 14 4 AMP-227699-2 J1–J4 BNC COAX CONN PCMT 5 LEAD TIME ELEC 15 1 MC10H131P U6 DIP-16 DUAL D FLIP-FLOP HAMILTON/HALLMARK 16 1 MC10H125P U7 DIP-16 QUAD ECL TO TTL TRANS HAMILTON/HALLMARK 17 1 74F74SC-ND U2 SO-14 FAST TTL DUAL D FLIP-FLOP DIGI-KEY 18 1 TSW-120-08-G-S J5 HEADER STRIP 20P GOLD MALE SAMTEC ALT: 1/2 90F3987 J5 40P HEADER NEWARK 19 1 AD96685BR U3 HIGH SPEED COMP SOIC-16 ANALOG DEVICES, INC. 20 7 S90F9280 S101–S107 SHORTING JUMPER NEWARK 21 8 89F4700 S101–S107, GND 3-PIN HEADER (DIVIDE 1 OF THE NEWARK

8 FOR 3 GND HOLES)

22 2 MC74F574DW U4, U5 SO-20 OCTAL D TYPE FLIP-FLOP HAMILTON/HALLMARK 23 1 AD9631AR U1 SOIC-8 OP AMP ANALOG DEVICES, INC. 24 1 AD9760AR U8 10-BIT CMOS DAC SOIC-28 ANALOG DEVICES, INC. 25 1 AD9054ST UA1 TQFP-44 DUAL 8-BIT ADC ANALOG DEVICES, INC. 26 1 P8002SCT-ND B1 SURFACE MOUNT MOMENTARY DIGI-KEY PUSHBUTTON 27 4 90F1533 – BUMPON PROTECTIVE BUMPER NEWARK PARTS NOT ON BILL OF MATERIALS, AND NOT TO BE INSTALLED: C5, C36, C37, R17–R20.

–18– REV. 0 44-Lead Plastic Thin Quad Flatpack (TQFP) (ST-44) TOP VIEW (PINS DOWN) 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) BSC 0.394 (10.0) SQ 0.472 (12.00) SQ 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) OUTLINE DIMENSIONS Dimensions shown in inches and (mm).

–19–

–20– C3146–8–10/97PRINTED IN U.S.A.