REV.D
Document overview
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Technical content
REV.D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9054A Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 8-Bit, 200 MSPS A/D Converter FUNCTIONAL BLOCK DIAGRAM ENCODE ENCODE AD9054A T/H AIN AIN GND 2.5V REFERENCE ENCODE LOGIC DEMULTIPLEXER VDD DSDSDEMUX QUANTIZER VREF IN VREF OUT DA7–DA 0 DB7–DB 0TIMING
FEATURES
200 MSPS Guaranteed Conversion Rate
135 MSPS Low Cost Version Available
350 MHz Analog Bandwidth
1 V p-p Analog Input Range
Internal 2.5 V Reference and T/H Low Power: 500 mW
5 V Single Supply Operation
Single or Demultiplexed Output Ports
APPLICATIONS
Digital Data Storage Read Channels Digital Communications Digital Instrumentation Medical Imaging GENERAL DESCRIPTION The AD9054A is an 8-bit monolithic analog-to-digital converter optimized for high speed, low power, small size and ease of use. With a 200 MSPS encode rate capability and full-power analog bandwidth of 350 MHz, the component is ideal for applications requiring the highest possible dynamic performance. To minimize system cost and power dissipation, the AD9054A includes an internal 2.5 V reference and track-and-hold circuit. The user provides only a 5 V power supply and an encode clock. No external reference or driver components are required for many applications. The AD9054A’s encode input interfaces directly to TTL, CMOS or positive-ECL logic and will operate with single-ended or differential inputs. The user may select dual-channel or single- channel digital outputs. The dual (demultiplexed) mode inter- leaves ADC data through two 8-bit channels at one-half the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces while allowing the ADC to be clocked to the full 200 MSPS conversion rate. In the single- channel (nondemultiplexed) mode, all data is piped at the full clock rate to the Channel A outputs. Fabricated with an advanced BiCMOS process, the AD9054A is provided in a space-saving 44-lead LQFP surface mount plastic package (ST-44) and specified over the full industrial (–40 °C to +85°C) temperature range.
–2– REV. D AD9054A–SPECIFICATIONS ELECTRICAL CHARACTERISTICS(VDD = 5 V, external reference, f S = max unless otherwise noted.) Test AD9054ABST-200 AD9054ABST-135 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Integral Nonlinearity 25 °CI ±0.6 ±1.5 ±0.6 ±1.5 LSB Full VI ±0.9 ±2.0 ±0.9 ±2.0 LSB No Missing Codes Full VI Guaranteed Guaranteed Gain Error1 25°CI ± 2 ± 7 ± 2 ± 7% F S Gain Tempco1 Full V 160 160 ppm/ °C ANALOG INPUT Input Voltage Range (With Respect to AIN) Full V ±512 ±512 mV p-p Compliance Range AIN or AIN Full V 1.8 3.2 1.8 3.2 V Input Offset Voltage 25 °CI ± 4 ±16 ± 4 ±16 mV Full VI ± 8 ±19 ± 8 ±19 mV Input Resistance 25 °C I 36 62 36 62 k Ω Full VI 23 23 k Ω Input Capacitance 25 °CV 4 4 p F Input Bias Current 25 °C I 25 50 25 50 µA Full VI 75 75 µA Analog Bandwidth, Full Power 2 25°C V 350 350 MHz REFERENCE OUTPUT Temperature Coefficient Full V 110 110 ppm/ °C SWITCHING PERFORMANCE Maximum Conversion Rate (f S) Full VI 200 135 MSPS Minimum Conversion Rate (f S) Full IV 25 25 MSPS Encode Pulsewidth High (t EH)2 5 °C IV 2.0 22 3.0 22 ns Encode Pulsewidth Low (t EL)2 5 °C IV 2.0 22 3.0 22 ns Aperture Delay (t A)2 5 °C V 0.5 0.5 ns Aperture Uncertainty (Jitter) 25 °C V 2.3 2.3 ps rms Data Sync Setup Time (t SDS)2 5 °CI V 0 0 n s Data Sync Hold Time (t HDS)2 5 °C IV 0.5 0.5 ns Data Sync Pulsewidth (t PWDS)2 5 °C IV 2.0 2.0 ns Output Valid Time (t V)3 Full VI 2.7 5.1 2.7 5.7 ns Output Propagation Delay (t PD)3 Full VI 5.9 7.9 7.5 8.5 ns DIGITAL INPUTS HIGH Level Current (I IH)4 Full VI 500 625 500 625 µA LOW Level Current (I IL)4 Full VI 500 625 500 625 µA Input Capacitance 25 °CV 3 3 p F DIFFERENTIAL INPUTS Differential Signal Amplitude (VID) Full IV 400 400 mV HIGH Input Voltage (V IHD) Full IV 1.5 V DD 1.5 V DD V LOW Input Voltage (V ILD) Full IV 0 V DD – 0.4 0 V DD – 0.4 V Common-Mode Input (V ICM) Full IV 1.5 1.5 V DEMUX INPUT HIGH Input Voltage (V IH) Full IV 2.0 V DD 2.0 V DD V LOW Input Voltage (V IL) Full IV 0 0.8 0 0.8 V DIGITAL OUTPUTS HIGH Output Voltage (V OH) Full VI 2.4 2.4 V LOW Output Voltage (V OL) Full VI 0.4 0.4 V Output Coding Binary Binary
–3–REV. D AD9054A Test AD9054ABST-200 AD9054ABST-135 Parameter Temp Level Min Typ Max Min Typ Max Unit POWER SUPPLY VDD Supply Current (I DD) Full VI 128 156 120 140 mA Power Dissipation 5, 6 Full VI 640 781 600 700 mW Power Supply Sensitivity 7 25°C I 0.005 0.015 0.005 0.015 V/V DYNAMIC PERFORMANCE 8 Transient Response 25 °C V 1.5 1.5 ns Overvoltage Recovery Time 25 °C V 1.5 1.5 ns Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 19.7 MHz 25 °CI V 4 24 5 4 2 4 5 d B Full V 45 45 dB fIN = 49.7 MHz 25 °C I 42 45 42 45 dB Full V 45 45 dB fIN = 70.1 MHz 25 °C I 42 45 dB Full V 45 dB Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 19.7 MHz 25 °CI V 4 04 3 4 0 4 3 d B Full V 43 43 dB fIN = 49.7 MHz 25 °C I 40 43 40 43 dB Full V 43 43 dB fIN = 70.1 MHz 25 °C I 39 42 dB Full V 42 dB Effective Number of Bits fIN = 70.1 MHz 25 °C I 6.18 6.85 Bits 2nd Harmonic Distortion fIN = 19.7 MHz 25 °C IV 58 63 58 63 dBc fIN = 49.7 MHz 25 °C I 54 59 54 59 dBc fIN = 70.1 MHz 25 °C I 49 55 dBc 3rd Harmonic Distortion fIN = 19.7 MHz 25 °C IV 48 56 48 56 dBc fIN = 49.7 MHz 25 °C I 48 54 48 54 dBc fIN = 70.1 MHz 25 °C I 43 50 dBc Two-Tone Intermod Distortion (IMD) fIN = 19.7 MHz 25 °C V 60 60 dBc fIN = 49.7 MHz 25 °C V 55 55 dBc fIN = 70.1 MHz 25 °C V 50 dBc NOTES 1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference). 23 dB bandwidth with full-power input signal. 3tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels of the digital outputs. The output ac load du ring test is 5 pF (Refer to equivalent circuits Figures 5 and 6). 4IIH and IIL are valid for differential input voltages of less than 1.5 V. At higher differential voltages, the input current will increase to a maximum of 1.5 mA. 5Power dissipation is measured under the following conditions: analog input is –1 dBFS at 19.7 MHz. 6Typical thermal impedance for the ST-44 (LQFP) 44-lead package (in still air): θJC = 20°C/W, θCA = 35°C/W, θJA = 55°C/W. 7A change in input offset voltage with respect to a change in V DD. 8SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25 °C and sample tested at speci- fied temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25 °C; guaranteed by design and characterization testing for industrial temperature range.
–4– REV. D CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9054A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS * *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Temperature Package Model Range Option * AD9054ABST-200 –40 °C to +85°C ST-44 AD9054ABST-135 –40 °C to +85°C ST-44 AD9054A/PCB 25 °C Evaluation Board *ST = Plastic Thin Quad Flatpack (LQFP). Table I. Output Coding Step AIN– AIN Code Binary 255 ≥0.512 V 255 1111 1111 254 0.508 V 254 1111 1110 253 0.504 V 253 1111 1101
- • • •
- • • •
- • • • 129 0.006 V 129 1000 0001 128 0.002 V 128 1000 0000 127 –0.002 V 127 0111 1111 126 –0.006 V 126 0111 1110
- • • •
- • • •
- • • • 2 –0.504 V 2 0000 0010 1 –0.508 V 1 0000 0001 0 ≤–0.512 V 0 0000 0000
Figure 1. Timing—Single Channel Mode
1 ENCODE Encode Clock for ADC (ADC
2 ENCODE Encode Clock Complement
33 VREF OUT Int ernal Reference Output
38 AIN Analog Input—Complement.
39 AIN Analog Input—True
42 DEMUX Format Select. LOW = Dual. Channel Mode, HIGH = Single.
43 DS Data Sync Complement
44 DS Data Sync—Aligns Output Chan-
fIN – MHz SNR – dB 30 0 140 20 40 60 80 100 120 SNR SINAD NYQUIST FREQUENCY (100MHz) TPC 1. SNR vs. fIN:f S = 200 MSPS fS – MSPS SNR – dB 25 50 100 150 200 250 300 75 125 175 225 270 SNR SINAD TPC 2. SNR vs. fS: fIN = 19.7 MHz fS – MSPS SNR – dB 25 50 100 150 200 250 300
45 SNR
TPC 3. SNR vs. fS:f IN = 70.1 MHz AD9054A–Typical Performance Characteristics –8– REV. D SNR – dB TC – /H11543C 44.0 –45 0 25 70 90 45.2 44.8 44.4 44.2 45.4 45.0 44.6 70MHz 20MHz50MHz TPC 4. SNR vs. Temperature, fS = 135 MSPS SNR – dB TC – /H11543C 46.0 44.0–60 100–40 –20 0 20 40 60 80 45.8 45.2 44.8 44.4 44.2 45.6 45.4 45.0 44.6 20MHz 50MHz 70MHz TPC 5. SNR vs. Temperature, fS = 200 MSPS SNR – dB ENCODE PULSEWIDTH – ns fS = 135MSPS fIN = 10.3MHz SNR SINAD TPC 6. SNR vs. Clock Pulsewidth, (tPWH): fS = 135 MSPS
–9–REV. D ENCODE PULSEWIDTH – ns SNR – dB fS = 200MSPS fIN = 10.3MHz SNR SINAD TPC 7. SNR vs. Clock Pulsewidth, (tPWH): fS = 200 MSPS TC – /H11543C SINAD – dB –60 100–40 –2 00 2 04 0 6 08 0 20MHz 50MHz 70MHz TPC 8. SINAD vs. Temperature: fS = 135 MSPS TC – /H11543C SINAD – dB –60 100–40 –20 0 20 40 60 80 20MHz 50MHz 70MHz TPC 9. SINAD vs. Temperature: fS = 200 MSPS fS – MSPS dBc –70 –50 25 22550 100 150 200 250 300 –68 –58 –56 –54 –52 –64 –60 –66 –62 –48 –46 75 125 175 270 3RD HARMONIC 2ND HARMONIC TPC 10. Harmonic Distortion vs. fS:f IN = 19.7 MHz fS – MSPS –60 25 30050 100 150 225 27075 125 175 200 250 –40 –20 –10 –50 –30 2ND HARMONIC 3RD HARMONIC dBc TPC 11. Harmonic Distortion vs. fS:f IN = 70.1 MHz TC – /H11543C dB –40 –70 –60 100–40 –2 0 0 2 04 0 6 08 0 –45 –50 –55 –60 –65 70MHz 50MHz 20MHz TPC 12. 2nd Harmonic vs. Temperature: fS = 135 MSPS
–10– REV. D TC – /H11543C –40 –70–60 100–40 –20 0 20 40 60 80 –45 –50 –55 –60 –65 dB 70MHz 50MHz 20MHz TPC 13. 2nd Harmonic vs. Temperature: fS = 200 MSPS TC – /H11543C –40 –70 –60 100–40 –20 0 20 40 60 80 –45 –50 –55 –60 –65 dB 70MHz 50MHz 20MHz TPC 14. 3rd Harmonic vs. Temperature: fS = 135 MSPS TC – /H11543C –40 –70 –60 100–40 –20 0 20 40 60 80 –45 –50 –55 –60 –65 dB 70MHz 50MHz 20MHz TPC 15. 3rd Harmonic vs. Temperature: fS = 200 MSPS fIN – MHz dB 0 50050 100 150 200 250 300 350 400 450 NYQUIST FREQUENCY 100MHz TPC 16. Frequency Response: fS = 200 MSPS MHz dB 0 100 10 20 30 40 50 60 70 80 90 –10 –90 –50 –60 –70 –80 –30 –40 –20 FUNDAMENTAL = –0.5dBFS SNR = 45.8dB SINAD = 45.2dB 2ND HARMONIC = 69.8dB 3RD HARMONIC = 61.6dB TPC 17. Spectrum: fS = 200 MSPS, fIN = 19.7 MHz MHz dB 0 10010 20 30 40 50 60 70 80 90 –10 –90 –50 –60 –70 –80 –30 –40 –20 FUNDAMENTAL = –0.5dBFS SNR = 44.6dB SINAD = 37.6dB 2ND HARMONIC = –63.1dB 3RD HARMONIC = –39.1dB TPC 18. Spectrum: fS = 200 MSPS, fIN = 70.1 MHz
–11–REV. D dB MHz 0 10010 20 30 40 50 60 70 80 90 –10 –90 –50 –60 –70 –80 –30 –40 –20 –100 F1 = 55.0MHz F2 = 56.0MHz F1 = F2 = –7.0dBFS TPC 19. Two-Tone Intermodulation Distortion IOH – mA VOH – Volts 5.0 2.0 0.0 4.5 2.5 1.5 0.5 3.5 3.0 1.0 4.0 TPC 20. Output Voltage HIGH vs. Output Current VOL – Volts IOL – mA 1.0 0.0 0.9 0.6 0.4 0.2 0.1 0.8 0.7 0.5 0.3 TPC 21. Output Voltage LOW vs. Output Current TC – /H11543C ns –60 100–40 –2 00 2 04 06 08 0 tPD tV TPC 22. Output Delay vs. Temperature IREF OUT – mA 2.55 2.48 2.45 2.54 2.49 2.47 2.46 2.53 2.51 2.52 2.50 VREF OUT – Volts TPC 23. Reference Voltage vs. Reference Load VDD – Volts VREF OUT – Volts 2.502 2.501 2.498 2.500 2.499 TPC 24. Reference Voltage vs. Power Supply Voltage
–12– REV. D APPLICATION NOTES THEORY OF OPERATION The AD9054A combines Analog Devices’ patented MagAmp bit-per-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an on-board reference and input logic that accepts TTL, CMOS or PECL levels. The analog input signal is buffered by a high-speed differential amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the ENCODE input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MagAmp string. The residue signal is then encoded by a flash comparator string to generate the four Least Significant Bits (LSBs). The comparator outputs are decoded and com- bined into the 8-bit result. If the user has selected Single Channel Mode ( DEMUX = HIGH), the 8-bit data word is directed to the Channel A out- put bank. Data are strobed to the output on the rising edge of the ENCODE input with four pipeline delays. If the user has selected Dual Channel Mode ( DEMUX = LOW) the data are alternately directed between the A and B output banks and have five pipeline delays. At power-up, the N sample data can appear at either the A or B port. To align the data in a known state the user must strobe DATA SYNC (DS, DS) per the conditions described in the Timing section. Graphics Applications The high bandwidth and low power of the AD9054A make it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another and is relatively stable for a period of time. Examples of these include digitizing the output of computer graphic display systems and very high speed solid state imagers. These applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the A/D must settle and sample the input in well under one pixel time. The architec- ture of the AD9054A is vastly superior to older flash architectures, that not only exhibit excessive input capacitance (which is very hard to drive), but can make major errors when fed a very rap- idly slewing signal. The AD9054A’s extremely wide bandwidth Track/Hold circuit processes these signals without difficulty. Using the AD9054A Good high speed design practices must be followed when using the AD9054A. To obtain maximum benefit, decoupling capaci- tors should be physically as close to the chip as possible. We recommend placing a 0.1 µF capacitor at each power-ground pin pair (9 total) for high frequency decoupling, and including one 10 µF capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0.1 µF capacitor. The part should be located on a solid ground plane and output trace lengths should be short (<1 inch) to minimize transmis- sion line effects. This avoids the need for termination resistors on the output bus and reduces the load capacitance that needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. We have obtained optimum performance on our evaluation board by tying all V DD pins to a quiet analog power supply system, and tying all GND pins to a quiet analog system ground. Minimum Encode Rate The minimum sampling rate for the AD9054A is 25 MHz. To achieve very high sampling rates, the track/hold circuit employs a very small hold capacitor. When operated below the minimum guaranteed sampling rate, the T/H droop becomes excessive. This is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. Lower effective sampling rates may be easily supported by oper- ating the converter in dual port output mode and using only one output channel. A majority of the power dissipated by the AD9054A is static (not related to conversion rate) so the penalty for clocking at twice the desired rate is not high. Reference The AD9054A internal reference, VREF, provides a simple, cost effective reference for many applications. It exhibits reasonable accuracy and excellent stability over power supply and tempera- ture variations. The VREF OUT pin can simply be strapped to the VREF IN pin. The internal reference can be used to drive additional loads (up to several mA), including multiple A/D con- verters as might be required in a triple video converter application. When an external reference is desired for accuracy or other requirements, the AD9054A should be driven directly by the external reference source connected to pin VREF IN (VREF OUT can be left floating). The external reference can be set to 2.5 V ± 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the analog full-scale range will increase by 10% to 1.024 × 1.1 = 1.1264 V. The new input range will then be AIN ±0.5632 V. TAMB – /H11543C VREF OUT – Volts 2.502 2.501 2.498 –40 100–20 0 20 40 60 80 2.500 2.499 TPC 25. Reference Voltage vs. Temperature
tion on the rising edge can be ignored. ment produces a tight timing window at higher encode rates. may be provided at the beginning of each graphics line or frame. parallel by adding a register stage to the output. sample is taken (five pipeline delays). time the A Port with the synchronizing latch. Figure 11. Dual Port Mode—Aligned Output Data
- DC-Coupled Analog Input
- Demuxed Outputs
- Differential Clocks
- Internal Voltage Reference. VREF OUT VREF IN AIN AIN DEMUX AD9054A DS DS ENC ENC B PORT '574 A PORT '574 DAC CLK A CLK BCLOCKING ENC ENC S102 VREF EXT S103 DC BIAS 50/H9024 AIN D FF D C RESET BUTTON CLK A CLK B S104 S105 ENC 50/H9024 ENC 50/H9024
Figure 12. PCB Block Diagram
2.5 V in one of two ways:
- DC-coupled through an AD9631 op amp; this is the mode in
- Differential TTL, CMOS, or PECL; it is shipped in this
- Single-ended TTL or CMOS. To use in this mode, remove
input, and insert a 0.1 µF ceramic capacitor into the C5 slot. tors to 1.5 V, but it can be externally driven to any dc voltage. Dual Port). The maximum speed in this mode is 200 MSPS. board’s latch clocks with the data coming out of the AD9054A. A only. Output Port B is not reconstructed.
- Check that all jumpers are in the correct position for the desired mode of operation.
- Push the reset button. This will align the AD9054A’s data output with the half speed latch clocks.
- Switch the jumper S105 from A-R to R-B or vice-versa, then push the reset button. In demuxed mode, this will have the effect of inverting the half speed latch clocks.
- At high encode rates, the evaluation board’s clock generation circuitry is sensitive to the 5 V digital power supply. At high encode rates, the 5 V digital power should be kept below 5.2 V. This is an evaluation board sensitivity and not an AD9054A sensitivity. The AD9054A Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
Figure 13. Evaluation Board Schematic
–18– REV. D BILL OF MATERIALS GS00104 REV. D ITEM QTY PART NUMBER REFERENCE DESCRIPTION MFG/DISTRIBUTOR 11 30 GRM40Z5U104M050BL C1, C2, C4, C6–C8, 0.1 µF CER CHIP CAP 0805 TTI C10–C22, C24–C29, C31–C35 12 1 P10FBK-ND R5 10 Ω SURFACE MT RES 1206 DIGI-KEY 13 21 P100FBK-ND R3, R9, R21–R39 100 Ω SURFACE MT RES 1206 DIGI-KEY 14 4 T491C106M016AS C3, C9, C23, C30 10 µF TANTALUM CHIP CAP TTI 15 2 P140FBK-ND R2, R4 140 Ω SURFACE MT RES 1206 DIGI-KEY 16 1 P1KFBK-ND R12 1 k Ω SURFACE MT RES 1206 DIGI-KEY 17 3 P2KFBK-ND R6, R8, R14 2 k Ω SURFACE MT RES 1206 DIGI-KEY 18 1 3296W-102-ND R7 1k TRIM POT TOP ADJ, 25 TURN DIGI-KEY 19 1 K44-C37S-QJ J6 37P D CONN RT ANG PCMT FEM CENTURY ELEC 10 5 P49.9FBK-ND R1, R10, R11, 49.9 Ω SURFACE MT RES 1206 DIGI-KEY R15, R16 11 1 CSC06A-01-511G RP1 510 Ω 6P BUSED RES NETWORK TTI 12 1 51F54113 TB1 8291Z 3-PIN TERMINAL BLOCK NEWARK 13 1 51F54112 TB1 8291Z 2-PIN TERMINAL BLOCK NEWARK 14 4 AMP-227699-2 J1–J4 BNC COAX CONN PCMT 5 LEAD TIME ELEC 15 1 MC10H131P U6 DIP-16 DUAL D FLIP-FLOP HAMILTON/HALLMARK 16 1 MC10H125P U7 DIP-16 QUAD ECL TO TTL TRANS HAMILTON/HALLMARK 17 1 74F74SC-ND U2 SO-14 FAST TTL DUAL D FLIP-FLOP DIGI-KEY 18 1 TSW-120-08-G-S J5 HEADER STRIP 20P GOLD MALE SAMTEC ALT: 1/2 90F3987 J5 40P HEADER NEWARK 19 1 AD96685BR U3 HIGH SPEED COMP SOIC-16 ANALOG DEVICES, INC. 20 7 S90F9280 S101–S107 SHORTING JUMPER NEWARK 21 8 89F4700 S101–S107, GND 3-PIN HEADER (DIVIDE 1 OF THE NEWARK
8 FOR 3 GND HOLES)
22 2 MC74F574DW U4, U5 SO-20 OCTAL D TYPE FLIP-FLOP HAMILTON/HALLMARK 23 1 AD9631AR U1 SOIC-8 OP AMP ANALOG DEVICES, INC. 24 1 AD9760AR U8 10-BIT CMOS DAC SOIC-28 ANALOG DEVICES, INC. 25 1 AD9054ABST UA1 8-BIT ADC IN 44-LEAD LQFP ANALOG DEVICES, INC. 26 1 P8002SCT-ND B1 SURFACE MOUNT MOMENTARY DIGI-KEY PUSHBUTTON 27 4 90F1533 – BUMPON PROTECTIVE BUMPER NEWARK PARTS NOT ON BILL OF MATERIALS, AND NOT TO BE INSTALLED: C5, C36, C37, R17–R20.
–19–REV. D 44-Lead Plastic Thin Quad Flatpack (LQFP) (ST-44) TOP VIEW (PINS DOWN) 2333 0.031 (0.80) BSC 0.472 (12.00) BSC SQ 0.394 (10.0) BSC SQ 0.018 (0.45) 0.012 (0.30) 0.063 (1.60) MAX SEATING PLANE 0.030 (0.75) 0.018 (0.45) 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35) OUTLINE DIMENSIONS Dimensions shown in inches and (mm).
–20– REV. D C00560–0–7/01(D) PRINTED IN U.S.A. Location Page Data Sheet changed from REV. C to REV. D. –Revision History