AD9051BRS-2V

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REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9051 Tel: 781/329-4700 www.analog.com Fax: © Analog Devices, Inc., 10-Bit, 60 MSPS A/D Converter FUNCTIONAL BLOCK DIAGRAM ENCODE AD9051 T/H SUM AMP DAC ADC DECODE LOGIC TIMING AIN AINB 5V GND REFERENCE CIRCUITS BWSEL ADC IN OUT

FEATURES

60 MSPS Sampling Rate

9.3 Effective Number of Bits at f

IN = 10.3 MHz 250 mW Total Power at 60 MSPS Selectable Input Bandwidth of 50 MHz or 130 MHz On-Chip T/H and Voltage Reference Single 5 V Supply Voltage

5 V or 3 V Logic I/O Compatible

Input Range and Output Coding Options Available

APPLICATIONS

The AD9051 is a complete 10-bit monolithic sampling analog- to-digital converter (ADC) with an onboard track-and-hold and reference. The unit is designed for low cost, high performance applications and requires only 5 V and an encode clock to achieve 60 MSPS sample rates with 10-bit resolution. The encode clock is TTL compatible and the digital outputs are CMOS; both can operate with 5 V/3 V logic. The two-step architecture used in the AD9051 is optimized to provide the best dynamic performance available while maintaining low power consumption. A 2.5 V reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. Fabricated on a state-of-the-art BiCMOS process, the AD9051 is packaged in a space saving surface mount package (SSOP) and is specified over the industrial tem- perature range (–40°C to +85°C). 2010 781/461-3113 C

8.76 9.3 9.0 8.8 56.5 55.5 56.5 9.1 8.8 8.6 56.5 56.5 55.5 53.5 54.5 8.59 52.5 53.5 REV. C

REV. C

REV. AD9051 –4– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9051 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS * *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at 25 °C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25 °C; guaranteed by design and characterization testing for industrial temperature range. Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND) OR Digital Output Analog Input Voltage Level (Out of Range) MSB... L S B 3.126 (3.50)* Positive Full Scale + 1 LSB 1 1111111111

2.5 Midscale 0 0111111111

1.874 (1.50)* Negative Full Scale – 1 LSB 1 0000000000 *(BRS-2V Version) C

4 VREFIN Input to Reference Amplifier. Voltage reference for ADC is connected here.

9 AINB Complementary Analog Input Pin (Analog Input Bar)

10 AIN Analog Input Pin

on rising edge of encode signal. analog input is out of nominal range.

15 D9 (MSB) Most Significant Bit of ADC Output

28 D0 (LSB) Least Significant Bit of ADC Output

Figure 1. Timing Diagram Figure 2. Equivalent Circuits

REV. AD9051 –6– CLOCK RATE – MSPS 255 DISSIPATION – mW 250 245 240 235 230 225 220 215 210 20 25 30 35 40 45 50 55 60 TPC 1. Power Dissipation vs. Clock Rate FREQUENCY – MHz 50 0 9010 SNR/SINAD – dB 20 30 40 50 60 70 80 SNR @ 40MSPS SINAD @ 40MSPS SINAD @ 60MSPS SNR @ 60MSPS TPC 2. SNR/SINAD vs. AIN Frequency FREQUENCY – MHz –50 –100 0 9010 dB 20 30 40 50 60 70 80 –55 –75 –85 –90 –95 –60 –65 –80 –70 2ND @ 40MSPS 2ND @ 60MSPS 3RD @ 60MSPS 3RD @ 40MSPS TPC 3. Harmonics vs. AIN Frequency ANALOG INPUT FREQUENCY – MHz ADC GAIN – dB 201 40 52 80 118 141 BWSEL ENABLED BWSEL DISABLED TPC 4. ADC Gain vs. AIN Frequency TEMPERATURE – /H11543C –40 SNR – dB 57.5 ENCODE = 40MSPS 56.5 55.5 45250–20 ENCODE = 60MSPS 58.5 AIN = 10.3MHz TPC 5. SNR vs. Temperature ENCODE – MSPS SNR – dB 40302010 50 60 AIN = 10.3MHz TPC 6. SNR vs. Clock Rate C

REV. AD9051 –7– FREQUENCY – MHz –10 –40 –100 –30 –90 –20 –50 –80 –70 –60 dB AIN = 10.3MHz ENCODE = 40MSPS SNR = 58.6dB SINAD = 57.69dB TPC 7. FFT Plot 40 MSPS, 10.3 MHz FREQUENCY – MHz –10 –40 –100 –30 –90 –20 –50 –80 –70 –60 dB AIN = 15.2MHz ENCODE = 40MSPS SNR = 58.47dB SINAD = 57.04dB TPC 8. FFT Plot 40 MSPS, 15.2 MHz FREQUENCY – MHz –10 –40 –100 –30 –90 –20 –50 –80 –70 –60 dB AIN = 10.3MHz ENCODE = 60MSPS SNR = 58.15dB SINAD = 57.25dB TPC 9. FFT Plot 60 MSPS, 10.3 MHz FREQUENCY – MHz –10 –40 –100 –30 –90 –20 –50 –80 –70 –60 dB AIN = 15.2MHz ENCODE = 60MSPS SNR = 58.29dB SINAD = 57.23dB TPC 10. FFT Plot 60 MSPS, 15.2 MHz FREQUENCY – MHz –10 –40 –100 –30 –90 –20 –50 –80 –70 –60 dB AIN = 21.7MHz ENCODE = 60MSPS SNR = 57.76dB SINAD = 56.27dB TPC 11. FFT Plot 60 MSPS, 21.7 MHz FREQUENCY – MHz –10 –40 –100 –30 –90 –20 –50 –80 –70 –60 dB AIN1 = 9.5MHz, –7dBFS AIN2 = 9.9MHz, –7dBFS IMD = –65dBc ENCODE = 60MSPS TPC 12. Two-Tone IMD C

REV. AD9051 –8– ENCODE – MSPS 1.2 0 6010 % GAIN ERROR 20 30 40 50 1.0 0.8 0.6 0.4 0.2 TPC 13. Gain vs. Clock Rate ENCODE – MSPS 0 6010 OFFSET – mV 20 30 40 50 TPC 14. Offset vs. Clock Rate DUTY CYCLE – % 25 5530 SNR – dB 35 40 45 50 60 65 70 75 SNR @ 40MSPS SNR @ 60MSPS TPC 15. SNR vs. Duty Cycle TEMPERATURE – /H11543C 6.5 –40 tPD – ns 3V FALLING 4.5 45250–20 3V RISING 5.5 5V FALLING 5V RISING TPC 16. tPD vs. Temperature 3 V/5 V SOURCE CURRENT – mA 2.51REF VOLTAGE 2.50 2.44 2.42 2.45 2.43 2.46 VOUT 2.47 2.48 2.49 TPC 17. Reference Load Regulation CODE 80% OCCURRANCE 512 513 514 515 516 517 518 TPC 18. Midscale Histogram (Inputs Tied) C

Refer to the block diagram on the front page. true 10-bit accuracy at the digital outputs of the converter. coarse and then a fine conversion of the T/H output signal.

3 V System

signals. All components are powered from a single 5 V supply. to the level required by the AD9051. differ entially into the AD9051. Figure 3. Single Supply, Single-Ended, DC-Coupled Figure 4. Single-Ended, Capacitively-Coupled AD9051 Figure 5. Differentially Driven AD9051 Using Trans- by the internal biasing of the AD9051 differential input (Pin 9). Figure 6. Level-Shifting with the AD830

REV. AD9051 –10– Overdrive of the Analog Input Special care was taken in the design of the analog input section of the AD9051 to prevent damage and corruption of data when the input is overdriven. The nominal input range is 1.875 V to 3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range compara- tors detect when the analog input signal is out of this range and the input buffer is clamped. The digital outputs are locked at their maximum or minimum value (i.e., all “0” or all “1”). This precludes the digital outputs changing to an invalid value when the analog input is out of range. The input is protected to one volt outside the power supply rails. For nominal power (5 V and ground), the analog input will not be damaged with signals from +5.5 V to –0.5 V. Timing The performance of the AD9051 is very insensitive to the duty cycle of the clock. Pulsewidth variations of as much as ±15% for encode rates of 40 MSPS and ±10% for encode rates of 60 MSPS will cause no degradation in performance. (See Figure 17, SNR vs. Duty Cycle.) The AD9051 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (t PD) after the rising edge of the encode command (refer to Figure 1, Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce tran- sients within the AD9051; these transients can detract from the converter’s dynamic performance. Power Dissipation The power dissipation specification in the parameter table is measured under the following conditions: encode is 60 MSPS, analog input is –FS. As shown in Figure 3, the actual power dissipation varies based on these conditions. For instance, reducing the clock rate will reduce power as expected for CMOS-type devices. The loading determines the power dissipated in the output stages. The analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. Power dissipation increases as more data bits switch at faster rates. For instance, if the input is a dc signal that is out of range, no output bits will switch. This minimizes power in the output stages, but is not realistic from a usage standpoint. The dissipation in the output stages can be minimized by inter- facing the outputs to 3 V logic (refer to Using the AD9051, 3 V System). The lower output swings minimize power consumption as follows: (1/2 C LOAD × VDD 2 × Update Rate). Voltage Reference A stable and accurate 2.5 V voltage reference is built into the AD9051 (Pin 3, VREFOUT). In normal operation the internal reference is used by strapping together Pins 3 and 4 of the AD9051. The internal reference has 500 µA of extra drive cur- rent that can be used for other circuits. Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain of the AD9051, which cannot be obtained by using the internal refer- ence. For these applications, an external 2.5 V reference can be used to connect to Pin 4 of the AD9051. The VREFIN requires 2 µA of drive current. The input range can be adjusted by varying the reference voltage applied to the AD9051. No appreciable degradation in performance occurs when the reference is adjusted ±5%. The full-scale range of the ADC tracks reference voltage changes linearly. C

REV. C –11– OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MO-150-AH 060106-A 28 15 10.50 10.20 9.90 8.20 7.80 7.40 5.60 5.30 5.00 SEATING PLANE

0.05 MIN

0.65 BSC

2.00 MAX

0.38 0.22COPLANARITY 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 Figure 7.28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD9051BRS −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRS-2V −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSRL −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSZ −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSZRL −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSRL-2V −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSZ-2V −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRSZRL-2V −40°C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 1 Z = RoHS Compliant Part.

REVISION HISTORY

11/10—Rev. B to Rev. C 7/01—Rev. A to Rev. B ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00558-0-11/10(C)