AD9051-2V

AD9051 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9051 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 10-Bit, 60 MSPS A/D Converter FUNCTIONAL BLOCK DIAGRAM ENCODE AD9051 T/H SUM AMP DAC ADC +5V DECODE LOGIC TIMING AIN AINB +5V GND REFERENCE CIRCUITS BWSEL ADC IN OUT

FEATURES

60 MSPS Sampling Rate

9.3 Effective Number of Bits at f IN = 10.3 MHz 250 mW Total Power at 60 MSPS Selectable Input Bandwidth of 50 MHz or 130 MHz On-Chip T/H and Voltage Reference Single +5 V Supply Voltage +5 V or +3 V Logic I/O Compatible Input Range and Output Coding Options Available

APPLICATIONS

The AD9051 is a complete 10-bit monolithic sampling analog- to-digital converter (ADC) with an onboard track-and-hold and reference. The unit is designed for low cost, high performance applications and requires only +5 V and an encode clock to achieve 60 MSPS sample rates with 10-bit resolution. The encode clock is TTL compatible and the digital outputs are CMOS; both can operate with +5 V/+3 V logic. The two-step architecture used in the AD9051 is optimized to provide the best dynamic performance available while maintaining low power consumption. A +2.5 V reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. Fabricated on a state-of-the-art BiCMOS process, the AD9051 is packaged in a space saving surface mount package (SSOP) and is specified over the industrial tem- perature range (–40°C to +85°C).

–2– REV. A AD9051–SPECIFICATIONS (VD = +5 V, VDD = +3 V; external reference = 2.50 V; ENCODE = 60 MSPS unless otherwise noted) Test AD9051BRS AD9051BRS-2V Parameter Temp Level Min Typ Max Min Typ Max Units RESOLUTION 10 10 Bits DC ACCURACY Differential Nonlinearity +25 °C I 0.75 1.50 0.75 1.50 LSB Full V 0.90 0.90 LSB Integral Nonlinearity +25 °C I 0.75 1.50 0.75 1.50 LSB Full V 0.90 0.90 LSB No Missing Codes +25 °C I ␣␣␣␣␣ GUARANTEED ␣␣␣␣␣G UARANTEED ␣ ␣ ␣ Gain Error1 +25°CI – 0.3 – 2.5 – 0.3 – 3.0 % FS Full VI – 5.0 – 5.5 % FS Gain Tempco1 Full V – 10 – 10 ppm/ °C ANALOG INPUT Input Voltage Range 2 +25°C V 1.25 2.0 V p-p Input Offset Voltage +25 °C I –14 5.0 26 –14 5.0 26 LSB Input Resistance +25 °C I 4.0 6.0 4.0 6.0 k W Input Capacitance +25 °CV 5 5 p F Analog Bandwidth (BW SEL +V D/NC)3 +25°C V 50/130 50/130 MHz BANDGAP REFERENCE Temperature Coefficient Full V – 33 – 33 ppm/ °C Power Supply Sensitivity Full V 6.2 6.2 mV/V Reference Input Current (V IN = 2.50 V) Full VI 2.0 25 2.0 25 mA SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 60 60 MSPS Minimum Conversion Rate 4 Full IV 2.0 5.0 2.0 5.0 MSPS Aperture Delay (t A) +25 °CV 2 . 5 2 . 5 n s Aperture Uncertainty (Jitter) +25 °C V 5 5 ps, rms Output Valid Time (t V)5 Full VI 4.0 4.0 ns Output Propagation Delay (t PD)5 Full VI 5.5 10 5.5 10 ns DYNAMIC PERFORMANCE 6 Transient Response +25 °C V 10 10 ns Overvoltage Recovery Time +25 °C V 10 10 ns ENOBS fIN = 1.20 MHz +25 °C V 9.6 9.6 ENOB fIN = 29.0 MHz +25 °C V 9.1 9.1 ENOB Signal-to-Noise Ratio (SINAD) fIN = 1.20 MHz +25 °C V 58.5 57.5 dB fIN = 10.3 MHz +25 °C I 55 57 54 56 dB fIN = 29.0 MHz +25 °C V 55 54 dB Signal-to-Noise Ratio (Without Harmonics) fIN = 1.20 MHz +25 °C V 59 59 dB fIN = 10.3 MHz +25 °C I 56 58 56 58 dB fIN = 29.0 MHz +25 °C V 56.5 56.5 dB 2nd Harmonic Distortion fIN = 1.20 MHz +25 °C V –74 –68 dBc fIN = 10.3 MHz +25 °C I –73 –60 –64 –58 dBc fIN = 29.0 MHz +25 °C V –67 –60 dBc 3rd Harmonic Distortion fIN = 1.20 MHz +25 °C V –74 –69 dBc fIN = 10.3 MHz +25 °C I –70 –60 –65 –60 dBc fIN = 29.0 MHz +25 °C V –65 –60 dBc Two-Tone Intermodulation Distortion (IMD) +25 °C V –65 –65 dBc Differential Phase +25 °C V 0.1 0.1 Degrees Differential Gain +25 °CV 0 . 5 0 . 5 %

–3–REV. A AD9051 Test AD9051BRS AD9051BRS-2V Parameter Temp Level Min Typ Max Min Typ Max Units ENCODE INPUT Logic “1” Voltage Full VI 2.0 2.0 V Logic “0” Voltage Full VI 0.8 0.8 V Logic “1” Current Full VI 1 1 mA Logic “0” Current Full VI 1 1 mA Input Capacitance +25 °CV 7 . 5 7 . 5 p F Encode Pulsewidth High (t EH) +25 °CI V 7 . 5 7 . 5 n s Encode Pulsewidth Low (t EL) +25 °CI V 7 . 5 7 . 5 n s DIGITAL OUTPUTS Logic “1” Voltage (5.0 V DD) Full VI 4.95 4.95 V Logic “0” Voltage (5.0 V DD) Full VI 0.05 0.05 V Logic “1” Voltage (3.0 V DD) Full VI 2.95 2.95 V Logic “0” Voltage (3.0 V DD) Full VI 0.05 0.05 V Output Coding7 Offset Binary Offset Binary POWER SUPPLY VD, VDD Supply Current Full VI 50 63 50 63 mA Power Dissipation 8 Full VI 250 315 250 315 mW Power Supply Rejection Ratio (PSRR)9 +25°CI – 2 – 10 – 7 – 15 mV/V NOTES 1Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 2Contact factory or authorized sales agent for information concerning the availability of expanded input voltage range devices. 33 dB bandwidth with full-power input signal. 4Minimum conversion rate at which all data sheet specifications remain stable. 5tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels 0.5 V and 2.4 V of the digital outputs with V DD = 3.0 V. The output ac load during test is 5 pF. 6SNR/harmonics tested with an analog input voltage of –0.5 dBfs. All tests performed at 60 MSPS. 7Contact factory or authorized sales agent for information concerning the availability of alternative output coding and input ra nge devices. 8Power dissipation is measured under the following conditions: analog input = –FS at 60 MSPS ENCODE. 9A change in input offset voltage with respect to a change in V D. Specifications subject to change without notice.

–4– REV. A ORDERING GUIDE Model Temperature Range Package Description Package Options AD9051BRS –40 °C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051BRS-2V –40 °C to +85°C 28-Lead Shrink Small Outline Package (SSOP) RS-28 AD9051/PCB +25 °C Evaluation Board AD9051-2V/PCB +25 °C Evaluation Board EXPLANATION OF TEST LEVELS Test Level I. 100% production tested. II. 100% production tested at +25 °C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at +25 °C; guaranteed by design and characterization testing for industrial temperature range. ABSOLUTE MAXIMUM RATINGS* *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9051 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND) OR Digital Output Analog Input Voltage Level (Out of Range) MSB␣ .␣ .␣ .␣ ␣ LSB 3.126 (3.50)* Positive Full Scale + 1 LSB 1 1111111111

2.5 Midscale 0 0111111111

1.874 (1.50)* Negative Full Scale – 1 LSB 1 0000000000 *(BRS-2V Version)

Refer to the block diagram on the front page. true 10-bit accuracy at the digital outputs of the converter. coarse and then a fine conversion of the T/H output signal.

3 V System

3 V logic supply, the AD9051 will supply 3 V output levels. signals. All components are powered from a single +5 V supply. to the level required by the AD9051. Figure 21. Single Supply, Single-Ended, DC-Coupled ␣ ␣ Figure 22. Single-Ended, Capacitively-Coupled AD9051 Figure 23. Differentially Driven AD9051 Using Trans- by the internal biasing of the AD9051 differential input (Pin 9). Figure 24. Level-Shifting with the AD830

–10– REV. A Overdrive of the Analog Input Special care was taken in the design of the analog input section of the AD9051 to prevent damage and corruption of data when the input is overdriven. The nominal input range is +1.875 V to 3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range com- parators detect when the analog input signal is out of this range and the input buffer is clamped. The digital outputs are locked at their maximum or minimum value (i.e., all “0” or all “1”). This precludes the digital outputs changing to an invalid value when the analog input is out of range. The input is protected to one volt outside the power supply rails. For nominal power (+5 V and ground), the analog input will not be damaged with signals from +5.5 V to –0.5 V. Timing The performance of the AD9051 is very insensitive to the duty cycle of the clock. Pulsewidth variations of as much as – 15% for encode rates of 40 MSPS and – 10% for encode rates of 60 MSPS will cause no degradation in performance. (See Fig- ure 17, SNR vs. Duty Cycle.) The AD9051 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (t PD) after the rising edge of the encode command (refer to Fig- ure 1, Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce tran- sients within the AD9051; these transients can detract from the converter’s dynamic performance. Power Dissipation The power dissipation specification in the parameter table is measured under the following conditions: encode is 60 MSPS, analog input is –FS. As shown in Figure 3, the actual power dissipation varies based on these conditions. For instance, reducing the clock rate will reduce power as expected for CMOS-type devices. The loading determines the power dissipated in the output stages. The analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. Power dissipation increases as more data bits switch at faster rates. For instance, if the input is a dc signal that is out of range, no output bits will switch. This minimizes power in the output stages, but is not realistic from a usage standpoint. The dissipation in the output stages can be minimized by inter- facing the outputs to 3 V logic (refer to Using the AD9051, 3 V System). The lower output swings minimize power consump- tion as follows: (1/2 C LOAD · VDD 2 · Update Rate). Voltage Reference A stable and accurate +2.5 V voltage reference is built into the AD9051 (Pin 3, VREFOUT). In normal operation the internal reference is used by strapping together Pins 3 and 4 of the AD9051. The internal reference has 500 mA of extra drive cur- rent that can be used for other circuits. Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain of the AD9051, which cannot be obtained by using the internal refer- ence. For these applications, an external +2.5 V reference can be used to connect to Pin 4 of the AD9051. The VREFIN requires 2 mA of drive current. The input range can be adjusted by varying the reference volt- age applied to the AD9051. No appreciable degradation in performance occurs when the reference is adjusted – 5%. The full-scale range of the ADC tracks reference voltage changes linearly. EVALUATION BOARD The AD9051 evaluation board is a convenient and easy way to evaluate the performance of the AD9051. Analog Input The evaluation board requires a 1.25 V p-p input. The signal is buffered by an AD9631 op amp in the unity gain configuration. The signal is then ac coupled before entering the AD9051 where a dc offset is internally generated. Leave E3 unconnected to E4 for usage with the AD9631. To evaluate performance without this buffer, remove the AD9631 and connect E3 to E4. Keep E1 connected to E2 for use in the low bandwidth mode (50 MHz). Removing this connector will enable high band- width mode (130 MHz). Low bandwidth is the recommended mode of operation in order to minimize any high frequency noise coupling into the input of the AD9051. Encode The evaluation board is driven with a TTL or CMOS clock into a clock buffer of ac type CMOS logic. This buffer will drive the encode to the AD9051, the data latches, and a “data ready.” Data Out The digital data is captured by a pair 74ACQ574 latches. Any unused connector pins should be grounded to the device that is capturing data from the evaluation board. This minimizes any grounding loops that may degrade performance. A separate power plane is provided for supplying the latches, clock buffer, and digital outputs of the AD9051. This supply can be 3 V or 5V . Layout The AD9051 is not layout sensitive if some important guide- lines are met. The evaluation board layout provides an ex- ample where these guidelines have been followed to optimize performance.

• Provide a solid ground plane connecting both analog and digital sections. Cuts in this plane near the AD9051 should be kept to a minimum.
• Excellent bypassing is essential. All capacitors should be placed as close as possible to the AD9051. No vias should be used to connect capacitors to the AD9051 as this may create a parasitic inductance that can reduce bypassing effectiveness. The AD9051 evaluation board is provided as a design example for customers of Analog Devices. ADI makes no warranties express, statutory, or implied regarding merchantability of fitness for a particular purpose.

C3321a–0–11/98PRINTED IN U.S.A. Figure 29. Evaluation Board Schematic Dimensions shown in inches and (mm).