AD9049

AD9049 9-Bit, 30 MSPS ADC

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Technical content

+5V DECODE LOGIC TIMING AIN AINB +5V GND REFERENCE CKTS REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 9-Bit, 30 MSPS ADC AD9049

FEATURES

Low Power: 300 mW On-Chip T/H, Reference Single +5 V Power Supply Operation Selectable 5 V or 3 V Logic I/O Wide Dynamic Performance

APPLICATIONS

The AD9049 is a complete 9-bit monolithic sampling analog- to-digital converter (ADC) with an onboard track-and-hold and reference. The unit is designed for low cost, high performance applications and requires only +5 V and an encode clock to achieve 30 MSPS sample rates with 9-bit resolution. The encode clock is TTL compatible and the digital outputs are CMOS; both can operate with 5 V/3 V logic, selected by the user. The two-step architecture used in the AD9049 is opti- mized to provide the best dynamic performance available while maintaining low power consumption. A 2.5 V reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. Fabricated on an advanced BiCMOS process, the AD9049 is packaged in space saving surface mount pack- ages (SOIC, SSOP) and is specified over the industrial (–40°C to +85°C) temperature range. Figure 1. Typical Connections

9 BITS

AD9049–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Temp Level Min Typ Max Units RESOLUTION 9 Bits DC ACCURACY Differential Nonlinearity +25 °C I 0.5 1.0 LSB Full V 0.5 LSB Integral Nonlinearity +25 °C I 0.5 1.0 LSB Full V 0.5 LSB No Missing Codes Full IV GUARANTEED Gain Error +25 °CI ± 1.0 ± 7.5 % FS Gain Tempco1 Full V ± 100 ppm/ °C ANALOG INPUT Input Voltage Range +25 °C V 1.024 V p-p Input Offset Voltage +25 °C I –10 +7 +25 mV Full IV –32 +51 mV Input Resistance +25 °C I 3.5 5.0 6.5 k Ω Input Capacitance +25 °CV 5 p F Analog Bandwidth +25 °C V 100 MHz BANDGAP REFERENCE Output Voltage +25 °C I 2.4 2.5 2.6 V Temperature Coefficient 1 Full V ± 50 ppm/ °C SWITCHING PERFORMANCE Maximum Conversion Rate +25 °C I 30 MSPS Minimum Conversion Rate +25 °C IV 1.5 3 MSPS Aperture Delay (tA) +25 °C V 2.7 ns Aperture Uncertainty (Jitter) +25 °C V 5 ps, rms Output Propagation Delay (t PD)2 Full IV 5 15 ns DYNAMIC PERFORMANCE Transient Response +25 °CV 1 0 n s Overvoltage Recovery Time +25 °CV 1 0 n s ENOBS fIN = 2.3 MHz +25 °C V 8.56 ENOBs fIN = 10.3 MHz +25 °C I 8.01 8.51 ENOBs Signal-to-Noise Ratio (SINAD) 3 fIN = 2.3 MHz +25 °C V 53.3 dB fIN = 10.3 MHz +25 °C I 50 53 dB Signal-to-Noise Ratio (Without Harmonics) fIN = 2.3 MHz +25 °C V 53.5 dB fIN = 10.3 MHz +25 °C I 51 53.3 dB 2nd Harmonic Distortion fIN = 2.3 MHz +25 °C V –69 dBc fIN = 10.3 MHz +25 °C I –67 –60 dBc 3rd Harmonic Distortion fIN = 2.3 MHz +25 °C V –75 dBc fIN = 10.3 MHz +25 °C I –66 –58 dBc Two-Tone Intermodulation Distortion (IMD)4 +25°C V 65 dBc Differential Phase +25 °C V 0.15 Degrees Differential Gain +25 °C V 0.35 % REV. A–2– (VD, VDD = +5 V; internal reference; ENCODE = 30 MSPS unless otherwise noted)

Parameter Temp Level Min Typ Max Units ENCODE INPUT Logic “1” Voltage Full IV 2.0 V Logic “0” Voltage Full IV 0.8 V Logic “1” Current Full IV 1 µA Logic “0” Current Full IV 1 µA Input Capacitance +25 °C V 10 pF Encode Pulse Width High (t EH) +25 °C IV 10 166 ns Encode Pulse Width Low (t EL) +25 °C IV 10 166 ns DIGITAL OUTPUTS Logic “1” Voltage Full IV 4.95 V Logic “0” Voltage Full IV 0.05 V Logic “1” Voltage (3.0 V DD) Full IV 2.95 V Logic “0” Voltage (3.0 VDD) Full IV 0.05 V Output Coding Offset Binary Code POWER SUPPLY VD, VDD Supply Current5 Full IV 40 60 80 mA Power Dissipation5 Full IV 300 400 mW Power Supply Rejection Ratio (PSRR)6 +25°CI ± 10 mV/V NOTES 1“Gain Tempco” is for converter only; “Temperature Coefficient” is for bandgap reference only. 2Output propagation delay (t PD) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF maximum loads. 3RMS signal to rms noise with analog input signal 0.5 dB below full scale at specified frequency. 4Intermodulation measured relative to either tone with analog input frequencies of 9.5 MHz and 9.9 MHz at 7 dB below full scale. 5Power dissipation is measured at 30 MSPS with AIN of 10.3 MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at other conditions. 6Measured as the ratio of the change in offset voltage for 5% change in +V D. Specifications subject to change without notice. AD9049 REV. A –3– EXPLANATION OF TEST LEVELS Test Level I – 100% Production Tested. IV – Parameter is guaranteed by design and characteriza- tion testing. V – Parameter is a typical value only. ABSOLUTE MAXIMUM RATINGS* Operating Temperature *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ORDERING GUIDE Model Temperature Range Package Option* AD9049BR –40 °C to +85°C R-28 AD9049BRS –40 °C to +85°C RS-28 *R = Small Outline (SO); RS = Shrink Small Outline (SSOP).

REV. A–4– Table I. AD9049 Digital Coding (Single Ended Input AIN, AINB Bypassed to GND) Digital Output Analog Input Voltage Level MSB . . . LSB Digital Output

3.810 Positive Full Scale 111111111

3.300 Midscale 011111111

2.790 Negative Full Scale 000000000

1, 7, 12, 21, 23 GND Ground. 2, 8, 11 V D Analog +5 V ± 5% power supply. 3 VREF OUT Internal bandgap voltage reference (nominally +2.5 V). 4 VREF IN Input to reference amplifier. Voltage reference for ADC is connected here. 5 COMP Internal compensation pin, 0.1 µF bypass connected here to V D (+5 V). 6 REF BP External connection for (0.1 µF) reference bypass capacitor. 9 AINB Complementary analog input pin (Analog input bar). 10 AIN Analog input pin. 13 ENCODE Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding) on rising edge of encode signal. 14 NC Not internally connected. 15 D8 (MSB) Most significant bit of ADC output. 16–19 D7–D4 Digital output bits of ADC. 20, 22 V DD Digital output power supply (only used by digital outputs). 24–26 D3–D1 Digital output bits of ADC. 27 D0 (LSB) Least significant bit of ADC output. 28 NC Not internally connected. PIN CONNECTIONS TOP VIEW (Not to Scale) AD9049 GND D0 (LSB) NC VD VREF OUT VREF IN VDD GND D3COMP REF BP GND VD AINB AIN D4 VDD GND VD GND ENCODE NC D8 (MSB) NC = NO CONNECT WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9049 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Refer to the block diagram on the front page. true 9-bit accuracy at the digital outputs of the converter. coarse and then a fine conversion of the T/H output signal.

3 V System

3 V logic supply, the AD9049 will supply 3 V output levels. signals. All components are powered from a single +5 V supply. to the level required by the AD9049. Figure 16. Single Supply, Single Ended, DC Coupled Figure 17. Single Ended, Capacitively Coupled AD9049 Figure 18. Differentially Driven AD9049 Using Trans- by the internal biasing of the AD9049 differential input (Pin 9). Figure 19. Level Shifting with the AD830

REV. A –9– Overdrive of the Analog Input Special care was taken in the design of the analog input section of the AD9049 to prevent damage and corruption of data when the input is overdriven. The nominal input range is +2.788 V to 3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range com- parators detect when the analog input signal is out of this range and shut the T/H off. The digital outputs are locked at their maximum or minimum value (i.e., all “0” or all “1”). This pre- cludes the digital outputs from changing to an invalid value when the analog input is out of range. When the analog input signal returns to the nominal range, the out-of-range comparators switch the T/H back to the active mode and the device recovers in approximately 10 ns. The input is protected to one volt outside the power supply rails. For nominal power (+5 V and ground), the analog input will not be damaged with signals from +6.0 V to –1.0 V. Timing The performance of the AD9049 is very insensitive to the duty cycle of the clock. Pulse width variations of as much as ± 10% will cause no degradation in performance (see Figure 13, SNR vs. Clock Pulse Width). The AD9049 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (t PD) after the rising edge of the encode command (refer to the AD9049 Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce tran- sients within the AD9049; these transients can detract from the converter’s dynamic performance. The minimum guaranteed conversion rate of the AD9049 is 3 MSPS. Below a nominal of 1.5 MSPS the internal T/H switches to a track function only. This precludes the T/H from drooping to the rail during the conversion process and mini- mizes saturation issues. At clock rates below 3 MSPS dynamic performance degrades. The AD9049 will operate in burst mode operation, but the user must flush the internal pipeline each time the clock stops. This requires 5 clock pulses each time the clock is restarted for the first valid data output (refer to Fig- ure 2 Timing Diagram). Power Dissipation The power dissipation specification in the parameter table is measured under the following conditions: encode is 30 MSPS, analog input is –1 dBFS at 10.3 MHz, the digital outputs are loaded with approximately 7 pF (10 pF maximum), and V DD is 5 V. These conditions intend to reflect actual usage of the device. As shown in Figure 4, the actual power dissipation varies based on these conditions. For instance, reducing the clock rate will reduce power as expected for CMOS type devices. Also the loading determines the power dissipated in the output stages. From an ac standpoint, the capacitive loading will be the key (refer to Equivalent Output Stage). The analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. Power dissipation increases as more data bits switch at faster rates. For instance, if the input is a dc signal that is out of range, no output bits will switch. This minimizes power in the output stages but is not realistic from a usage standpoint. The dissipation in the output stages can be minimized by inter- facing the outputs to 3 V logic (refer to USING THE AD9049, 3 V System). The lower output swings minimize consumption. Refer to Figure 4 for performance characteristics. Voltage Reference A stable and accurate +2.5 V voltage reference is built into the AD9049 (Pin 3, VREF Output). In normal operation the internal reference is used by strapping Pins 3 and 4 of the AD9049 to- gether. The internal reference has 500 µA of extra drive current that can be used for other circuits. Some applications may require greater accuracy, improved tem- perature performance or adjustment of the gain of the AD9049, which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can be used to connect to Pin 4 of the AD9049. The VREF IN requires 5 µA of drive current. The input range can be adjusted by varying the reference volt- age applied to the AD9049. No appreciable degradation in per- formance occurs when the reference is adjusted ± 5%. The full-scale range of the ADC tracks reference voltage changes linearly.

Figure 23. Evaluation Board Schematic

REV. A–12– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead SOIC (R-28) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45° 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 29 15 141 28-Lead SSOP (RS-28) 28 15 141 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) PIN 1 SEATING PLANE 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) BSC 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) C2104a–2–12/96PRINTED IN U.S.A.