AD9048KJ

AD9048 AD | Alldatasheet

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REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Monolithic 8-Bit Video A/D Converter AD9048 FUNCTIONAL BLOCK DIAGRAM R 127 R R/2 R/2 128 R 254 255 R E N C O D I N G L O G I C 19 256 10 7 8 9 115 L A T C H VCC VEE DGND AGND D1 (MSB) D8 (LSB) NLINV NMINV V IN R T R M R B CONVERT AD9048 GENERAL DESCRIPTION The AD9048 is an 8-bit, 35 MSPS flash converter, made on a high speed bipolar process, which is an alternate source for the TDC1048 unit, offers enhancements over its predecessor. Lower power dissipation makes the AD9048 attractive for a variety of system designs. Because of its wide bandwidth, it is an ideal choice for real-time conversion of video signals. Input bandwidth is flat with no missing codes. Clocked latching comparators, encoding logic and output buffer registers operating at minimum rates of 35 MSPS preclude a need for a sample-and-hold (S/H) or track-and-hold (T/H) in most system designs using the AD9048. All digital control in- puts and outputs are TTL compatible. Devices operating over two ambient temperature ranges and with two grades of linearity are available. Linearities of either 0.5 LSB or 0.75 LSB can be ordered for a commercial range of 0°C to +70°C or extended case temperatures of –55 °C to +125°C. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 Commercial versions are packaged in 28-lead DIPs; extended temperature versions are available in ceramic DIP and ceramic LCC packages. Both commercial units and MIL-STD-883 units are standard products. The AD9048 A/D converter is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Prod- ucts Databook or current AD9048/883B data sheet for detailed specifications.

FEATURES

35 MSPS Encode Rate

MIL-STD-883 Compliant Versions Available

APPLICATIONS

Professional Video Systems Special Effects Generators Electro-Optics Digital Radio Electronic Warfare (ECM, ECCM, ESM)

ELECTRICAL CHARACTERISTICS

Test AD9048JJ/JQ AD9048KJ/KQ AD9048SE/SQ AD9048TE/TQ Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 8 8 8 8 Bits DC ACCURACY Full VI 1.0 0.75 1.0 0.75 LSB Full VI 1.0 0.75 1.0 0.75 LSB No Missing Codes Full VI GUARANTEED GUARANTEED GUARANTEED GUARANTEED INITIAL OFFSET ERROR Top of Reference Ladder +25 °C I 51 2 5 1 2 51 2 5 1 2m V Full VI 12 12 12 12 mV Bottom of Reference Ladder +25 °C I 48 4 8 48 4 8 m V Full VI 8 8 8 8 mV Offset Drift Coefficient Full V 20 20 20 20 mV/°C ANALOG INPUT Input Voltage Range Full V –2.1; –2.1; –2.1; –2.1; Input Bias Current 7 +25°C I 36 60 36 60 36 60 36 60 mA Full VI 100 100 100 100 mA Input Resistance +25 °C I 200 300 200 300 200 300 200 300 k W Full VI 40 40 40 40 k W Input Capacitance +25 °C I V 1 62 0 1 6 2 0 1 62 0 1 6 2 0 p F Full Power Bandwidth 8 +25°C I V 1 0 1 51 0 1 51 0 1 51 0 1 5 M H z REFERENCE INPUT Positive Reference Voltage 9 Full V 0.0 0.0 0.0 0.0 V Negative Reference Voltage 9 Full V –2.0 –2.0 –2.0 –2.0 V Differential Reference Voltage Full V 2.0 2.0 2.0 2.0 V Reference Ladder Resistance Full VI 30 60 125 30 60 125 30 60 125 30 60 125 W Ladder Temperature Coefficient Full V 0.22 0.22 0.22 0.22 W /°C Reference Ladder Current Full VI 23 40 23 40 23 40 23 40 mA Reference Input Bandwidth +25 °C V 10 10 10 10 MHz DYNAMIC PERFORMANCE 10 Conversion Rate +25 °C I 35 38 35 38 35 38 35 38 MHz Aperture Delay +25 °C IV 2.4 5 2.4 5 2.4 5 2.4 5 ns Aperture Uncertainty (Jitter) +25 °C I V 2 55 0 2 5 5 0 2 55 0 2 5 5 0 p s Output Delay (t PD) +25 °C I 13 15 9 15 9 15 9 15 ns Output Hold Time (t OH)11 +25°C I 58 5 8 58 5 8 n s Transient Response 12 +25°C IV 6 20 6 20 6 20 6 20 ns Overvoltage Recovery Time 13 +25°C V 88 88 n s Rise Time +25 °CI 9 9 9 9 n s Fall Time +25 °C I 14 14 14 14 ns Output Time Skew 14 +25°C I 4.5 7 4.5 7 4.5 7 4.5 7 ns NMINV and NLINV INPUTS +0.4 V Input Current Full VI 200 200 200 200 mA +2.4 V Input Current Full VI 150 150 150 150 mA +5.5 V Input Current Full VI 150 150 150 150 mA CONVERT INPUT Logic “1” Voltage Full VI 2.0 2.0 2.0 2.0 V Logic “0” Voltage Full VI 0.8 0.8 0.8 0.8 V Logic “1” Current Full VI 150 150 150 150 mA Logic “0” Current Full VI 500 500 500 500 mA Input Capacitance +25 °C I V 4 64 6 4 64 6 p F Convert Pulsewidth (LOW) +25 °C I 18 18 18 18 ns Convert Pulsewidth (HIGH) +25 °C I 10 10 10 10 ns REV. C–2– ABSOLUTE MAXIMUM RATINGS 1 V CONV, NMINV or NLINV to DGND –0.5 V dc to +5.5 V dc Applied Output Current, Externally Forced Operating Temperature Range (Ambient) AD9048–SPECIFICATIONS(typical with nominal supplies unless otherwise noted) (VCC = +5.0 V; VEE = –5.2 V; Differential Reference Voltage = 2.0 V, unless otherwise noted)

Test AD9048JJ/JQ AD9048KJ/KQ AD9048SE/SQ AD9048TE/TQ Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units AC LINEARITY In-Band Harmonics dc to 2.438 MHz 15 +25°C I 47 50 49 55 47 50 49 55 dBc dc to 9.35 MHz 16 +25°C V 48 48 48 48 dBc Signal-to-Noise Ratio (SNR) 15 1.248 MHz Input Frequency 17 +25°C I 43.5 44 45 46 43.5 44 45 46 dB

2.438 MHz Input Frequency 17 +25°C I 43 44 44 46 43 44 44 46 dB

1.248 MHz Input Frequency 18 +25°C I 52.5 53 54 55 52.5 53 54 55 dB

2.438 MHz Input Frequency 18 +25°C I 52 53 53 55 52 53 53 55 dB

Signal-to-Noise Ratio (SNR) 16 1.248 MHz Input Frequency 17 +25°C I 43.5 44 45 46 43.5 44 45 46 dB Noise Power Ratio (NPR) 19 +25°C IV 36.5 39 36.5 39 36.5 39 36.5 39 dB Differential Phase 20 +25°C IV 1 1 1 1 Degree Differential Gain 20 +25°CI V 2 2 2 2 % DIGITAL OUTPUTS Logic “1” Voltage Full VI 2.4 2.4 2.4 2.4 V Logic “0” Voltage Full VI 0.5 0.5 0.5 0.5 V Short Circuit Current 5 Full VI 30 30 30 30 mA POWER SUPPLY Positive Supply Current +25 °C I 34 56 34 56 34 56 34 56 mA Full VI 58 58 58 58 mA Negative Supply Current +25 °C I 90 110 90 110 90 110 90 110 mA Full VI 120 120 120 120 mA Nominal Power Dissipation +25 °C V 550 550 550 550 mW Reference Ladder Dissipation +25 °C V 45 45 45 45 mW NOTES 1Maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the device may be impaired. Functional operation under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2Applied voltage must be current-limited to specified range. 3Forcing voltage must be limited to specified range. 4Current is specified as negative when flowing into the device. 5Output High; one pin to ground; one second duration. 6Typical thermal impedances (no air flow) are as follows: Ceramic DIP: qJA = 49°C/W; qJC = 15°C/W LCC: qJA = 69°C/W; qJC = 21°C/W JLCC: qJA = 59°C/W; qJC = 19°C/W To calculate junction temperature (T J), use power dissipation (PD) and thermal impedance: TJ = PD (qJA) + TAMBIENT = PD (qJC) = + T CASE. 7Measured with V IN = 0 V and CONVERT low (sampling mode). 8Determined by beat frequency testing for no missing codes. 9VRT ‡ VRB under all circumstances. 10Outputs terminated with 40 pF and eight 10 W pull-up resistors. 11Interval from 50% point of leading edge CONVERT pulse to change in output data. 12For full-scale step input, 8-bit accuracy attained in specified time. 13Recovers to 8-bit accuracy in specified time after –3 V input overvoltage. 14Output time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences. 15Measured at 20 MHz encode rate with analog input 1 dB below full scale. 16Measured at 35 MHz encode rate with analog input 1 dB below full scale. 17RMS signal to rms noise. 18Peak signal to rms noise. 19DC to 8 MHz noise bandwidth with 1.248 MHz slot; four sigma loading; 20 MHz encode. 20Clock frequency = 4 · NTSC = 14.32 MHz. Measured with 40-IRE modulated ramp. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level V – Parameter is a typical value only. Test Level VI – All devices are 100% production tested at +25°C. 100% production tested at tempera- ture extremes for military temperature de- vices; sample tested at temperature extremes for commercial/industrial devices. Test Level I – 100% production tested. Test Level II – 100% production tested at +25 °C and sample tested at specific temperatures. Test Level III – Sample tested only. Test Level IV – Parameter is guaranteed by design and characterization testing. AD9048 –3–REV. C

–4– REV. C ORDERING GUIDE Package Model Linearity Temperature Option 1 AD9048JJ 0.75 LSB 0 °C to +70°C J-28A AD9048KJ 0.5 LSB 0 °C to +70°C J-28A AD9048JQ 0.75 LSB 0 °C to +70°CQ - 2 8 AD9048KQ 0.5 LSB 0 °C to +70°CQ - 2 8 AD9048SE2 0.75 LSB –55 °C to +125°C E-28A AD9048TE2 0.5 LSB –55 °C to +125°C E-28A AD9048SQ2 0.75 LSB –55 °C to +125°CQ - 2 8 AD9048TQ2 0.5 LSB –55 °C to +125°CQ - 2 8 NOTES 1E = Leadless Ceramic Chip Carrier; J = J-Leaded Ceramic; Q = Cerdip. 2For temperature designation only. MIL-STD-883 and Standard Military Drawing available. PIN DESIGNATIONS EE MECHANICAL INFORMATION DIP (Q Package) TOP VIEW (Not to Scale) AD9048 NC = NO CONNECT NMINV R M R B AGND NC V IN NC NC NC AGND R T CONVERT D8 (LSB) (MSB) D1 DGND V CC VEE VEE VEE VCC DGND NLINV LCC (E Package) 28 2712342 6 12 13 14 15 16 17 18 TOP VIEW (Not to Scale) NC = NO CONNECT AGND NC VIN NC NC NC AGND DGND V CC VEE VEE VEE VCC DGND D1 (MSB) NLINV (LSB) D8 CONVERT R T NMINV R M R B AD9048 J-Leaded Ceramic (J Package) 1151 06789 1921 2025 24 2223 TOP VIEW (Not to Scale) TOP VIEW (Not to Scale) CONVERT D8 (LSB) NLINV R B R M NMINV (MSB) D1 AGND NC VIN NC NC AGND DGND VCC VEE VEE VEE VCC DGND NC = NO CONNECT R T NC AD9048 Bonding Diagram RLOW RMID NMINV MSB DGND RTOP CONV NLINV DGND V CC VCC VEE VEE VEE VCC VCC DGND AGND AIN AGND CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9048 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

–5–REV. C PIN FUNCTION DESCRIPTIONS Burn-In Diagram Pin Description D1–D8 Eight digital outputs. D1 (MSB) is the most significant bit of the digital output word; D8 (LSB) is the least significant bit. AGND One of two analog ground returns. Both grounds should be connected together and to low impedance ground plane near the AD9048. DGND One of two digital ground returns. Both grounds should be connected together and to low impedance ground plane near the AD9048. V CC Positive supply terminals; nominally +5.0 V. VEE Negative supply terminals; nominally –5.2 V. CONVERT Input for conversion signal; sample of analog input signal taken on rising edge of this pulse. Pin Description RB Most negative reference voltage for internal reference ladder. RM Midpoint tap on internal reference ladder. RT Most positive reference voltage for internal reference ladder. VIN Analog input signal pin. NMINV “Not Most Significant Bit Invert.” In normal operation, this pin floats high; logic LOW at NMINV inverts most significant bit of digital output word [D1 (MSB)]. NLINV “Not Least Significant Bit Invert.” In normal operation, this pin floats high; logic LOW at NLINV inverts the seven least significant bits of the digital output word.

–8– REV. C C1212a–0–1/99PRINTED IN U.S.A. Table I. Truth Table Offset Twos Binary Complement Step Range True Inverted True Inverted –2.000 V FS –2.0480 V FS NMINV = 1 0 0 1 7.8431 mV Step 8.000 mV Step NLINV = 1 0 1 0 000 0.0000 V 0.0000 V 00000000 11111111 10000000 01111111 001 –0.0078 V –0.0080 V 00000001 11111110 10000001 01111110 127 –0.9961 V –1.0160 V 01111111 10000000 11111111 00000000 128 –1.0039 V –1.0240 V 10000000 01111111 00000000 11111111 129 –1.0118 V –1.0320 V 10000001 01111110 00000001 11111110 254 –1.9921 V –2.0320 V 11111110 00000001 01111110 10000001 255 –2.0000 V –2.0400 V 11111111 00000000 01111111 10000000 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Ceramic Side-Brazed DIP 11 4 0.610 (15.24) 0.500 (14.43) PIN 1 SEATING PLANE0.023 (0.508) 0.014 (0.381) 0.105 (2.67) 0.095 (2.42) 0.225 (5.72) MAX 0.175 (4.45) 0.125 (3.18) 0.065 (1.66) 0.038 (0.965) 1.418 (36.02) 1.38 (35.06) 0.12 (3.05) 0.06 (1.53) 0.620 (15.4) 0.590 (14.74) 0.015 (0.305) 0.008 (0.203) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE GOLD PLATED (50 MICROINCHES MIN) KOVAR OR ALLOY 42 28-Terminal Leadless Chip Carrier 511 18 26 BOTTOM VIEW 25 0.028 (0.71) (1.27 –0.13) 0.040 (1.02) x 45° REF 3 PLCS 0.055 (1.40) NO 1 PIN INDEX 0.020 (0.51) x 45° REF 1 PLC 0.458 (11.63) 0.442 (11.23) SQ 0.100 (2.54) 0.064 (1.63) NOTES

1 THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS

2 APPLIES TO ALL FOUR SIDES

ALL TERMINALS ARE GOLD PLATED 28-Lead J-Lead Package 0.171 (4.34) MAX 0.019 –0.002 (0.483 –0.051) 0.006 –0.0006 (0.152 –0.015) 0.039 –0.005 (0.991 –0.127) 0.028 –0.002 (0.711 –0.051) 0.420 –0.010 (10.668 –0.254) 0.102 –0.010 (1.448 –0.254) PIN 1 TOP VIEW (PINS DOWN) 25 19 0.050 (1.27) BSC 0.300 (7.62) TYP 0.450 –0.006 (11.43 –0.152) SQ 0.488 –0.010 (11.43 –0.254) SQ BOTTOM VIEW 0.022 –0.003 (0.559 –0.076)