AD9042AST

AD9042 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 12-Bit, 41 MSPS Monolithic A/D Converter

FEATURES

41 MSPS Minimum Sample Rate

80 dB Spurious-Free Dynamic Range 595 mW Power Dissipation Single +5 V Supply On-Chip T/H and Reference Twos Complement Output Format CMOS-Compatible Output Levels

APPLICATIONS

Cellular/PCS Base Stations GPS Anti-Jamming Receivers Communications Receivers Spectrum Analyzers Electro-Optics Medical Imaging ATE FUNCTIONAL BLOCK DIAGRAM AIN ENCODE VREF DV CCAV CC AD9042 ADC VOFFSET DAC TH2A1 TH1 +2.4V REFERENCE INTERNAL TIMING D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB TH3 A2 ADC DIGITAL ERROR CORRECTION LOGIC ENCODE GND © Analog Devices, Inc., 1996 Tel: 617/329-4700 Fax: 617/326-8703 PRODUCT DESCRIPTION The AD9042 is a high speed, high performance, low power, monolithic 12-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference are included on chip to provide a complete conversion solution. The AD9042 runs off of a single +5 V supply and provides CMOS-compatible digital outputs at 41 MSPS. Designed specifically to address the needs of wideband, multichannel receivers, the AD9042 maintains 80 dB spurious-free dynamic range (SFDR) over a bandwidth of 20 MHz. Noise performance is also exceptional; typical signal-to-noise ratio is 68 dB. The AD9042 is built on Analog Devices’ high speed complemen- tary bipolar process (XFCB) and uses an innovative multipass architecture. Units are packaged in a 28-pin DIP; this custom AD9042AD PIN DESIGNATIONS NC = NO CONNECT GND D10 D11 (MSB) DV CC GND ENCODE D7ENCODE GND GND AIN VOFFSET VREF D2 GND AV CC GND AV CC NC NC D0 (LSB) TOP VIEW (Not to Scale) AD9042 cofired ceramic package forms a multilayer substrate to which internal bypass capacitors and the 9042 die are attached and a 44-pin TQFP low profile surface mount package. The AD9042 industrial grade is specified from –40 °C to +85°C. However, the AD9042 was designed to perform over the full military temperature range (–55°C to +125°C); consult factory for military grade product options. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate is 41 MSPS. 2. Dynamic performance specified over entire Nyquist band; spurious signals typ. 80 dBc for –1 dBFS input signals. 3. Low power dissipation: 595 mW off a single +5 V supply. 4. Reference and track-and-hold included on chip. 5. Packaged in 28-pin ceramic DIP and 44-pin TQFP. AD9042AST PIN DESIGNATIONS AD9042 40 39 3841424344 36 35 34 37 12 13 14 15 16 17 18 19 20 21 22 PIN 1 TOP VIEW (Not to Scale) AV CC AV CC AV CC AV CC AV CC AD9042 DV CC DV CC ENCODE ENCODE GND GND AIN NC = NO CONNECT VOFFSET VREF AV CC D0 (LSB) GND NC D11 (MSB) GND GND GND GND D10 GND GND GND GND GND DV CC DV CC DV CC DV CC GND

Test AD9042AST Test AD9042AD Parameter Temp Level Min Typ Max Level Min Typ Max Units RESOLUTION 12 12 Bits DC ACCURACY No Missing Codes Full VI Guaranteed VI Guaranteed Offset Error Full VI –10 ± 3 +10 VI –10 ± 3 +10 mV Offset Tempco Full V 25 V 25 ppm/ °C Gain Error Full VI –6.5 0 +6.5 VI –6.5 0 +6.5 % FS Gain Tempco Full V –50 V –50 ppm/ °C REFERENCE OUT (VREF)2 +25°C V 2.4 V 2.4 V ANALOG INPUT (AIN) Input Voltage Range V REF ± 0.500 V REF ± 0.500 V Input Resistance Full IV 200 250 300 IV 200 250 300 Ω Input Capacitance +25 °C V 5.5 V 7 pF ENCODE INPUT3 Logic Compatibility4 TTL/CMOS TTL/CMOS Logic “1” Voltage Full VI 2.0 5.0 VI 2.0 5.0 V Logic “0” Voltage Full VI 0 0.8 VI 0 0.8 V Logic “1” Current (VINH = 5 V) Full VI 450 625 800 VI 450 625 800 µA Logic “0” Current (VINL = 0 V) Full VI –400 –300 –200 VI –400 –300 –200 µA Input Capacitance +25 °C V 2 V 2.5 pF DIGITAL OUTPUTS Logic Compatibility CMOS CMOS Logic “1” Voltage (IOH = 10 µA) +25 °C I 3.5 4.2 I 3.5 4.2 V Full IV 3.5 IV 3.5 V Logic “0” Voltage (IOL = 10 µA) +25 °C I 0.75 0.80 I 0.75 0.80 V Full IV 0.85 IV 0.85 V Output Coding Twos Complement Twos Complement POWER SUPPLY AVCC Supply Voltage Full VI 5.0 VI 5.0 V I (AVCC) Current Full V 109 V 109 mA DVCC Supply Voltage Full VI 5.0 VI 5.0 V I (DVCC) Current Full V 10 V 10 mA ICC (Total) Supply Current Full VI 119 147 VI 119 147 mA Power Dissipation Full VI 595 735 VI 595 735 mW Power Supply Rejection +25 °C I –20 ± 1 +20 I –20 ± 1 +20 mV/V (PSRR) Full V ± 5V ± 5 mV/V NOTES 1C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 µF capacitor. 2VREF is normally tied to V OFFSET through 50 Ω . If VREF is used to provide dc offset to other circuits, it should first be buffered. 3ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor. 4ENCODE may also be driven differentially in conjunction with ENCODE; see “Encoding the AD9042” for details. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Test AD9042AST Test AD9042AD Parameter (Conditions) Temp Level Min Typ Max Level Min Typ Max Units Maximum Conversion Rate Full VI 41 VI 41 MSPS Minimum Conversion Rate Full IV 5 IV 5 MSPS Aperture Delay (tA) +25 °C V –250 V –250 ps Aperture Uncertainty (Jitter) +25 °C V 0.7 V 0.7 ps rms ENCODE Pulse Width High +25 °C I V1 0 I V1 0 n s ENCODE Pulse Width Low +25 °C I V1 0 I V1 0 n s Output Delay (tOD) Full IV 5 9 14 IV 5 9 14 ns NOTE 1C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 µF capacitor. REV. A (AVCC = DVCC = +5 V; VREF tied to VOFFSET through 50 Ω ; TMIN = –408C, TMAX = +858C)1 –2– (AVCC = DVCC = +5 V; ENCODE & ENCODE = 41 MSPS; VREF tied to VOFFSET through 50 Ω ; TMIN = –408C, TMAX = +858C)1 AD9042–SPECIFICATIONS

Test AD9042AST Test AD9042AD Parameter (Conditions) Temp Level Min Typ Max Level Min Typ Max Units SNR3 Analog Input 1.2 MHz +25 °CV 6 8 I 6 5 6 8 d B @ –1 dBFS Full V 67.5 V 67.5 dB 9.6 MHz +25 °C V 67.5 I 64.5 67.5 dB Full V 67 V 67 dB

19.5 MHz +25 °C I 64 67 I 64 67 dB

Full V 66.5 V 66.5 dB SINAD4 Analog Input 1.2 MHz +25 °C V 67.5 I 64 67.5 dB @ –1 dBFS Full V 67 V 67 dB 9.6 MHz +25 °C V 67.5 I 64 67.5 dB Full V 67 V 67 dB Full V 66.5 V 66.5 dB Worst Spur5 Analog Input 1.2 MHz +25 °C V 80 I 74 80 dBc @ –1 dBFS Full V 78 V 78 dBc

9.6 MHz +25 °C V 80 I 74 80 dBc

19.5 MHz +25 °C I 73 80 I 73 80 dBc

Small Signal SFDR (w/Dither) 6 Analog Input @1.2 MHz Full V 90 V 90 dBFS

9.6 MHz Full V 90 V 90 dBFS

19.5 MHz Full V 90 V 90 dBFS

F1, F2 @ –7 dBFS Full V 80 V 80 dBc Two-Tone SFDR (w/Dither) 8 Full V 90 V 90 dBFS Thermal Noise +25 °C V 0.33 V 0.33 LSB rms (ENCODE = 20 MSPS) Full V ± 0.4 VI –1.0 +1.25 LSB Integral Nonlinearity (ENCODE = 20 MSPS) Full V ± 0.75 V ± 0.75 LSB Analog Input Bandwidth +25 °C V 100 V 100 MHz Transient Response +25 °CV 1 0 V 1 0 n s Overvoltage Recovery Time +25 °CV 2 5 V 2 5 n s NOTES 1All ac specifications tested by driving ENCODE and ENCODE differentially; see “ENCODING the AD9042” for details. 2C1 (Pin 10 on AD9042AST only) tied to GND through 0.01 µF capacitor. 3Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). 4Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD ) is the ratio of signal level to total noise + harmonics. 5Analog input signal power at –1 dBFS; worst spur is the ratio of the signal level to worst spur, usually limited by harmonics. 6Analog input signal power swept from –20 dBFS to –95 dBFS; dither power = –32.5 dBm; dither circuit used on input signal (see “Overcoming Static Nonlinearities with Dither”); SFDR is ratio of converter full scale to worst spur. 7Tones at –7 dBFS (F1 = 15.3 MHz, F2 = 19.5 MHz); two tone intermodulation distortion (IMD) rejection is ratio of either tone to worst third order intermod product. 8Both input tones swept from –20 to –95 dBFS; Dither power = –32.5 dBm; dither circuit used on input signal (see “Overcoming Static Nonlinearities with Dither); two tone spurious-free dynamic range (SFDR) is the ratio of converter full scale to worst spur. Specifications subject to change without notice. REV. A –3– AD9042 (AVCC = DVCC = +5 V; ENCODE & ENCODE = 41 MSPS; VREF tied to VOFFSET through 50 Ω ; TMIN = –408C, TMAX = +858C)2

–4– REV. A ORDERING GUIDE Model Temperature Range Package Description Package Option AD9042AST –40 °C to +85°C (Ambient) 44-Pin TQFP (Thin Quad Plastic Flatpack) ST-44 AD9042AD –40 °C to +85°C (Ambient) 28-Pin 600 Mil Hermetic Ceramic DIP (DH-28) DH-28 AD9042CHIPS –40 °C to +85°C (Ambient) Unpackaged Die AD9042ST/PCB Evaluation Board with AD9042AST AD9042D/PCB Evaluation Board with AD9042AD WAFER TEST LIMITS1 AD9042CHIPS Parameter Temp Min Max Units POWER SUPPLY ICC Supply Current +25 °C 90 147 mA ENCODE Input Logic “1” Current +25 °C 450 800 µA Logic “0” Current +25 °C –400 –200 µA DC ACCURACY Offset Error +25 °C– 8 8 m V Gain Error +25 °C –6 6 % FS No Missing Codes +25 °C Guaranteed Differential Nonlinearity @ 5.3 MSPS +25 °C –0.995 LSB NOTES 1Electrical test is performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. 2Die substrate is connected to 0 V. ABSOLUTE MAXIMUM RATINGS 1 Parameter Min Max Units ELECTRICAL AVCC Voltage 0 7 V DVCC Voltage 0 7 V Analog Input Voltage 0.5 4.5 V Analog Input Current 20 mA Digital Input Voltage (ENCODE) 0 AV CC V ENCODE, ENCODE Differential Voltage 4 V Digital Output Current –40 40 mA ENVIRONMENTAL2 Operating Temperature Range (Ambient) –40 +85 °C Maximum Junction Temperature AD9042AD +175 °C AD9042AST +150 °C Lead Temperature (Soldering, 10 sec) +300 °C Storage Temperature Range (Ambient) –65 +150 °C NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2Typical thermal impedances for “D” package (custom ceramic 28-pin DIP): θJC = 14°C/W; θJA = 34°C/W. For “ST” package (44-pin TQFP) ; θJA = 55°C/W. (AVCC = DVCC = +5 V; ENCODE = 10.3 MSPS unless otherwise noted) WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9042 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. II – 100% production tested at +25 °C, and sample tested at specified temperatures. AC testing done on sample basis. III – Sample tested only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25 °C; sample tested at temperature extremes.

REV. A –5– AD9042AST PIN DESCRIPTIONS Pin No. Name Function 1, 2 DV CC +5 V Power Supply (Digital). Powers output stage only. 3 ENCODE Encode input. Data conversion initiated on rising edge. 4 ENCODE Complement of ENCODE. Drive differentially with ENCODE or bypass to Ground for single-ended clock mode. 5, 6 GND Ground. 7 AIN Analog Input. OFFSET Voltage Offset Input. Sets mid- point of analog input range. Normally tied to VREF through 50 Ω resistor. 9V REF Internal Voltage Reference. Nominally +2.4 V; normally tied to VOFFSET through 50 Ω resistor. Bypass to Ground with 0.1 µF + 0.01 µF microwave chip cap. 10 C1 Internal Bias Point. Bypass to ground with 0.01 µF cap. 11, 12 AV CC +5 V Power Supply (Analog). 13, 14 GND Ground. 15, 16 AV CC +5 V Power Supply (Analog). 17, 18 GND Ground. 19, 20 AV CC +5 V Power Supply (Analog). 21 GND Ground. 22 GND Ground. 23 NC No Connects. 24 GND Ground.

25 D0 (LSB) Digital Output Bit

(Least Significant Bit) 26–33 D1–D8 Digital Output Bits 34, 35 GND Ground. 36, 37 DV CC +5 V Power Supply (Digital). Powers output stage only. 38, 39 GND Ground. 40, 41 DV CC +5 V Power Supply (Digital). Powers Output Stage only. 42, 43 D9–D10 Digital Output Bits.

44 D11 (MSB)1 Digital Output Bit

(Most Significant Bit). NOTE 1Output coded as twos complement. AD9042AD PIN DESCRIPTIONS Pin No. Name Function 1 GND Ground. 2D V CC +5 V Power Supply (Digital). Powers output stage only. 3 GND Ground. 4 ENCODE Encode input. Data conversion initiated on rising edge. ENCODE Complement of ENCODE. Drive differentially with ENCODE or bypass to Ground for single-ended clock mode. 6, 7 GND Ground. 8 AIN Analog Input. OFFSET Voltage Offset Input. Sets mid- point of analog input range. Normally tied to VREF through 50 Ω resistor. 10 V REF Internal Voltage Reference. Nominally +2.4 V; normally tied to VOFFSET through 50 Ω resistor. Bypass to Ground with 0.1 µF cap. 11 GND Ground. 12 AV CC +5 V Power Supply (Analog). 13 GND Ground. 14 AV CC +5 V Power Supply (Analog). 15, 16 NC No Connects. 17 D0 (LSB) Digital Output Bit. (Least Significant Bit). 18–27 D1–D10 Digital Output Bits. D11 (MSB)1 Digital Output Bit (Most Significant Bit). NOTE 1Output coded as twos complement. AD9042 CUSTOM 28-PIN DIP PACKAGE

–6– REV. A Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels. Overvoltage Recovery Time The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal 150% of full scale is reduced to midscale. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale). Transient Response The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels is lowered), or in dBFS (always related back to converter full scale). DIE LAYOUT AND MECHANICAL INFORMATION DIE LAYOUT W/PAD LABELS DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic “1” state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle.

AD9042 is negligible in most cases. Figure 30. Sine Source – Differential Encode capacitors but do not need to be of the low inductance variety. Figure 31. Differential ECL for Encode Figure 32. ECL Comparator for Encode inverting mode (ref. Equivalent Circuits: Analog Input Stage). inputs to the same voltage, the inverting input is also at 2.4 volts. cuit shifts over temperature.

50 OHMS

Figure 33. Analog Input Offset by +2.4 V Reference sampled; in most cases, a 0.1 µF chip capacitor will work well. Figure 34. AC-Coupled Analog Input Signal Figure 35. Transformer-Coupled Analog Input Signal where Z is desired impedance.

used. The AD9631 and OP279 run off ± 5 V. Figure 36. DC-Coupled Analog Input Circuit closely to the package as possible using 0.1µF chip capacitors. the evaluation board schematics shown in Figures 37 and 38. dynamic switching currents of the AD9042. chip capacitor as referenced previously in the data sheet. Care should be taken when placing the digital output runs. capacitive loading on the digital outputs should be minimized. encode; all the user must supply is power and an analog signal. Power to the analog supply pins is connected via banana jacks. where Z is desired input impedance.

that U5 requires TTL levels to function properly. converter output, and strobes the external data register over J3. logic section of the evaluation board. Figure 37. AD9042D/PCB Schematic

Figure 38. AD9042ST/PCB Schematic

Figure 54. Using the AD9042 with Dither provide a good approximation. overall contribution to receiver sensitivity calculated. Figure 55. Receiver Analysis this is an equivalent SNR (with respect to full scale) of 56.5 dB.

40.96 MSPS, the SNR through processing gain is increased by

range and reduce the carrier-to-noise ratio (C/N)* to 54.8 dB. –74.8 dBm. Referenced to the antenna, this is –104.8 dBm. power level so that AGC can be kept near the maximum gain. tone) would limit receiver performance in this example. sensitivity nearly to that limited by thermal noise. Figure 56. Multitone Performance **C/N is the ratio of signal to inband noise. **C/I is the ratio of signal to inband interferer.

filters and other devices, reducing cost and power dissipation. 1.4 MHz. Figure 57 shows performance under these conditions. Figure 57. IF-Sampling a 21.4 MHz Input variable gain amplifier with the gain set by the AD7226 DAC. ation of signal level in the body.

14 TO 20dB

Figure 58. Using the AD9042 in Ultrasound Applications presented to the digital system for processing.

–24– REV. A C2080a–10–5/96PRINTED IN U.S.A. AD9042AST OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 44-Pin Thin Quad Flatpack (ST-44) TOP VIEW (PINS DOWN) 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) BSC 0.393 (10.0) BSC SQ 0.472 (12.00) BSC SQ 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.008 (0.20) 0.003 (0.09) 0.039 (1.00) REF AD9042AD OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Pin Hermetic Ceramic DIP (DH-28) 11 4 0.595 ± 0.010 (15.11 ± 0.25) PIN 1 IDENTIFIERS SEATING PLANE 0.225 (5.72) MAX 0.150 (3.81) MIN 0.600 (15.24) REF 0.010 ± 0.002 (0.25 ± 0.05) 1.400 ± 0.014 (35.56 ± 0.35) 0.018 ± 0.002 (0.46 ± 0.05) 0.100 (2.54) TYP 0.050 ± 0.010 (1.27 ± 0.25) 0.05 (1.27) TYP