AD9020

REV.C

Document overview

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Technical content

REV.C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 10-Bit 60 MSPS A/D Converter AD9020 FUNCTIONAL BLOCK DIAGRAM 1024 10 D E C O D E L O G I C R R R R R R R R ANALOG IN 512 384 C O M P A R A T O R L A T C H E S 257 256 129 128 MSB INVERT LSBS INVERT OVERFLOW OVERFLOW D9 (MSB) D0 (LSB) OVERFLOW 385 GROUND+VS–VS R/2 R/2 R/2 R/2 R/2 R/2 R/2 R/2 –VREF –VSENSE ENCODE 1/4REF 1/2REF 3/4REF +VSENSE +VREF AD9020 L A T C H

FEATURES

Monolithic 10-Bit/60 MSPS Converter TTL Outputs Bipolar ( /H115501.75 V) Analog Input 56 dB SNR @ 2.3 MHz Input Low (45 pF) Input Capacitance MIL-STD-883-Compliant Versions Available

APPLICATIONS

Radar Warning/Guidance Systems Infrared Systems GENERAL DESCRIPTION The AD9020 A/D converter is a 10-bit monolithic converter capable of word rates of 60 MSPS and above. Innovative archi- tecture using 512 input comparators instead of the traditional 1024 required by other flash converters reduces input capaci- tance and improves linearity. Encode and outputs are TTL-compatible, making the AD9020 an ideal candidate for use in low power systems. An over- flow bit is provided to indicate analog input signals greater than +V SENSE. Voltage sense lines are provided to insure accurate driving of the ±VREF voltages applied to the units. Quarter-point taps on the resistor ladder help optimize the integral linearity of the unit. Either 68-pin ceramic leaded (gull wing) packages or ceramic LCCs are available and are specifically designed for low thermal impedances. Two performance grades for temperatures of both 0°C to 70°C and –55°C to +125°C ranges are offered to allow the user to select the linearity best suited for each application. Dynamic performance is fully characterized and production tested at 25°C. MIL-STD-883 units are available. The AD9020 A/D Converter is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Prod- ucts Databook or current AD9020/883B data sheet for detailed specifications. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

REV. C–2– AD9020–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Test AD9020JE/JZ AD9020KE/KZ Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 10 10 Bits DC ACCURACY3 Differential Nonlinearity 25 °C I 1.0 1.25 0.75 1.0 LSB Full VI 1.5 1.25 LSB Integral Nonlinearity 25 °C I 1.25 2.75 1.0 2.25 LSB Full VI 3.0 2.50 LSB No Missing Codes Full VI Guaranteed ANALOG INPUT Input Bias Current4 25°C I 0.4 1.0 0.4 1.0 mA Full VI 2.0 2.0 mA Input Resistance 25 °C I 2.0 7.0 2.0 7.0 k Ω Input Capacitance4 25°C V 45 45 pF Analog Bandwidth 25 °C V 175 175 MHz REFERENCE INPUT Reference Ladder Resistance 25 °C I 22 37 56 22 37 56 Ω Full VI 14 66 14 66 Ω Ladder Tempco Full V 0.1 0.1 Ω/°C Reference Ladder Offset Top of Ladder 25 °C I 45 90 45 90 mV Full VI 90 90 mV Bottom of Ladder 25 °C I 45 90 45 90 mV Full VI 90 90 mV Offset Drift Coefficient Full V 50 50 µV/°C SWITCHING PERFORMANCE Conversion Rate 25 °C I 60 60 MSPS Aperture Delay (tA)2 5 °CV 1 1 n s Aperture Uncertainty (Jitter) 25 °C V 5 5 ps, rms Output Delay (tOD)5 25°C I 6 10 13 6 10 13 ns Output Time Skew5 25°C I 35 35 n s DYNAMIC PERFORMANCE Transient Response 25 °C V 10 10 ns Overvoltage Recovery Time 25 °C V 10 10 ns Effective Number of Bits (ENOB) Signal-to-Noise Ratio 6 fIN = 2.3 MHz 25 °C I 49.5 56 49.5 56 dB fIN = 10.3 MHz 25 °C I 47.5 53 47.5 53 dB fIN = 15.3 MHz 25 °C I 45.5 50 45.5 50 dB Signal-to-Noise Ratio 6 (Without Harmonics) fIN = 2.3 MHz 25 °C I 49.5 56 49.5 56 dB fIN = 10.3 MHz 25 °C I 49.5 54 49.5 54 dB fIN = 15.3 MHz 25 °C I 48 52 48 52 dB (/H11550VS = /H115505 V; /H11550VSENSE = /H115501.75 V; ENCODE = 40 MSPS unless otherwise noted) ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature

Test AD9020JE/JZ AD9020KE/KZ Parameter (Conditions) Temp Level Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE (continued) Harmonic Distortion fIN = 2.3 MHz 25 °C I 54.5 67 54.5 67 dBc fIN = 10.3 MHz 25 °C I 48.5 59 48.5 59 dBc fIN = 15.3 MHz 25 °C I 46.5 53 46.5 53 dBc Two-Tone Intermodulation Distortion Rejection 7 25°C V 70 70 dBc Differential Phase 25 °C V 0.5 0.5 Degree Differential Gain 25 °CV 1 1 % ENCODE INPUT Logic “1” Voltage Full VI 2.0 2.0 V Logic “0” Voltage Full VI 0.8 0.8 V Logic “1” Current Full VI 500 500 µA Logic “0” Current Full VI 800 800 µA Input Capacitance 25 °CV 5 5 p F Pulsewidth (High) 25 °C I 66n s Pulsewidth (Low) 25 °C I 66n s DIGITAL OUTPUTS Logic “1” Voltage (IOH = 2 mA) Full VI 2.4 2.4 V Logic “0” Voltage (IOL = 6 mA) Full VI 0.4 V POWER SUPPLY +VS Supply Current 25 °C I 440 530 440 530 mA Full VI 542 542 mA –VS Supply Current 25 °C I 140 170 140 170 mA Full VI 177 177 mA Power Dissipation 25 °C I 2.8 3.3 2.8 3.3 W Full VI 3.4 3.4 W Power Supply Rejection Ratio (PSRR)8 Full VI 6 10 6 10 mV/V NOTES 1Absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit ma y be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliab ility. 2Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: θJC = 1°C/W; θJA = 17°C/W (no air flow); θJA = 15°C/W (air flow = 500 LFM). 68-pin ceramic LCC: θJC = 2.6°C/W; θJA = 15°C/W (no air flow); θJA = 13°C/W (air flow = 500 LFM). 33/4REF, 1/2REF, and 1/4REF reference ladder taps are driven from dc sources at +0.875 V, 0 V, and –0.875 V, respectively. Accuracy of the overflow compar ator is not tested and not included in linearity specifications. 4Measured with ANALOG IN = +V SENSE. 5Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or fall ing edge of D 0–D9. Output skew measured as worst-case difference in output delay among D 0–D9. 6RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency. 7Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale. 8Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +V S or –VS. Specifications subject to change without notice. REV. C –3– AD9020

*E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier. Figure 1. Burn-In Circuit V – Parameter is a typical value only. for commercial/industrial devices.

–5–REV. C PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1 1/2 REF Midpoint of internal reference ladder. 2, 16, 28, 29, 35, 41, 42, –V S Negative supply voltage; nominally –5.0 V ± 5%. 54, 64 3, 6, 15, 18, 25, 30, 33, 34, +V S Positive supply voltage; nominally 5 V ± 5%. 37, 40, 45, 52, 55, 65, 68 4, 5, 13, 17, 27, 31, 32, GROUND All ground pins should be connected together and to low impedance ground 36, 38, 39, 43, 53, 66, 67 plane. 7 3/4 REF Three-quarter point of internal reference ladder. 8, 9 ANALOG IN Analog input; nominally between ±1.75 V. 11 +V SENSE Voltage sense line to most positive point on internal resistor ladder. Normally 1.75 V. 12 +V REF Voltage force connection for top of internal reference ladder. Normally driven to provide 1.75 V at +V SENSE. 14 ENCODE TTL-compatible convert command used to begin digitizing process. 19–23, 46–50 D 0–D4, D5–D9 TTL-compatible digital output data. 51 OVERFLOW TTL-compatible output indicating ANALOG IN > +V SENSE. 56 –V REF Voltage force connection for bottom of internal reference ladder. Normally driven to provide –1.75 V at –V SENSE. 57 –V SENSE Voltage sense line to most negative point on internal resistor ladder. Normally –1.75 V. 59 LSBs INVERT Normally grounded. When connected to +V S, lower order bits (D 0–D8) are inverted. 61 MSB INVERT Normally grounded. When connected to +V S, most significant bit (MSB; D 9) is inverted. 63 1/4 REF One-quarter point of internal reference ladder. PIN CONFIGURATION ANALOG IN MSB INVERT +VS –VS 1/4REF 1/2REF 3/4REF ANALOG IN +VS +VS +VS –VS GND GND GND GND NC LSBs INVERT OVERFLOW D9 (MSB) –VREF –VSENSE +VS –VS +VS +VS NC NC NC GND (LSB) D0 +VS +VS +VSENSE +VREF GND NC ENCODE +VS –VS GND NC NC GND –VS –VS +VS +VS +VS –VS +VS +VS –VS –VS GND GND GND GND GND GND NC = NO CONNECT AD9020 TOP VIEW (NOT TO SCALE) 9 61 6010 27 43

–6– REV. C THEORY OF OPERATION Refer to the AD9020 block diagram. As shown, the AD9020 uses a modified “flash,” or parallel, A/D architecture. The analog input range is determined by an external voltage refer- ence (+V REF and –V REF), nominally ± 1.75 V. An internal resistor ladder divides this reference into 512 steps, each rep- resenting two quantization levels. Taps along the resistor ladder (1/4REF, 1/2REF and 3/4REF) are provided to optimize linearity. Rated performance is achieved by driving these points at 1/4, 1/2, and 3/4, respectively, of the voltage reference range. The A/D conversion for the nine most significant bits (MSBs) is performed by 512 comparators. The value of the least sig- nificant bit (LSB) is determined by a unique interpolation scheme between adjacent comparators. The decoding logic processes the comparator outputs and provides a 10-bit code to the output stage of the converter. Flash architecture has an advantage over other A/D architec- tures because conversion occurs in one step. This means the performance of the converter is primarily limited by the speed and matching of the individual comparators. In the AD9020, an innovative interpolation scheme takes advantage of flash architecture but minimizes the input capacitance, power and device count usually associated with that method of conversion. These advantages occur by using only half the normal num- ber of input comparator cells to accomplish the conversion. In addition, a proprietary decoding scheme minimizes error codes. Input control pins allow the user to select from among Binary, Inverted Binary, Two’s Complement and Inverted Two’s Complement coding (see Table I). Many of the specifications used to describe analog/digital converters have evolved from system performance require- ments in these applications. Different systems emphasize particular specifications, depending on how the part is used. The following applications highlight some of the specifications and features that make the AD9020 attractive in these systems. Wideband Receivers Radar and communication receivers (baseband and direct IF digitization), ultrasound medical imaging, signal intelligence and spectral analysis all place stringent ac performance require- ments on analog-to-digital converters (ADCs). Frequency domain characterization of the AD9020 provides sig- nal-to-noise ratio (SNR) and harmonic distortion data to simplify selection of the ADC. Receiver sensitivity is limited by the Signal-to-Noise Ratio of the system. The SNR for an ADC is measured in the fre- quency domain and calculated with a Fast Fourier Transform (FFT). The SNR equals the ratio of the fundamental compo- nent of the signal (rms amplitude) to the rms value of the noise. The noise is the sum of all other spectral components, including harmonic distortion, but excluding dc. Good receiver design minimizes the level of spurious signals in the system. Spurious signals developed in the ADC are the result of imperfections (nonlinearities, delay mismatch, vary- ing input impedance, etc.) in the device transfer function. In the ADC, these spurious signals appear as Harmonic Dis- tortion. Harmonic Distortion is also measured with an FFT and is specified as the ratio of the fundamental component of the signal (rms amplitude) to the rms value of the worst-case harmonic (usually the 2nd or 3rd). Two-Tone Intermodulation Distortion (IMD) is a frequently cited specification in receiver design. In narrow-band receiv- ers, third-order IMD products result in spurious signals in the passband of the receiver. Like mixers and amplifiers, the ADC is characterized with two, equal-amplitude, pure input frequencies. The IMD equals the ratio of the power of either of the two input signals to the power of the strongest third- order IMD signal. Unlike mixers and amplifiers, the IMD does not always behave as it does in linear devices (reduced input levels do not result in predictable reductions in IMD). Performance graphs provide typical harmonic and SNR data for the AD9020 for increasing analog input frequencies. In choosing an A/D converter, always look at the dynamic range for the analog input frequency of interest. The AD9020 specifications provide guaranteed minimum limits at three analog test frequencies. Aperture Delay is the delay between the rising edge of the ENCODE command and the instant at which the analog input is sampled. Many systems require simultaneous sampling of more than one analog input signal with multiple ADCs. In these situations, timing is critical and the absolute value of the aperture delay is not as critical as the matching between devices. Aperture Uncertainty, or jitter, is the sample-to-sample variation in aperture delay. This is especially important when sampling high slew rate signals in wide bandwidth systems. Aperture uncertainty is one of the factors that degrade dynamic performance as the ana- log input frequency is increased. Digitizing Oscilloscopes Oscilloscopes provide amplitude information about an observed waveform with respect to time. Digitizing oscilloscopes must accurately sample this signal, without distorting the information to be displayed. One figure of merit for the ADC in these applications is Effective Number of Bits (ENOBs). ENOB is calculated with a sine wave curve fit and equals: ENOB = N – LOG 2 [Error (measured)/Error (ideal)] N is the resolution (number of bits) of the ADC. The measured error is the actual rms error calculated from the converter out- puts with a pure sine wave input. The Analog Bandwidth of the converter is the analog input fre- quency at which the spectral power of the fundamental signal is reduced 3 dB from its low frequency value. The analog band- width is a good indicator of a converter’s stewing capabilities.

drops by no more than 3 dB below the guaranteed limit. the correct times, as shown in Figure 2. Figure 2. Imaging Application Using AD9020 SNR or ENOB is a good measure of the noise of the AD9020. useful dynamic range of the ADC. in the analog input sufficiently fast to capture a valid sample. reduced to the full-scale range of the converter. the device is affected by reference voltages applied to the ladder.

0000000000 OUTPUT CODE

Figure 3. Effect of Reference Taps on Linearity lines will affect the accuracy of the sense line voltage.

Figure 9. Timing Diagram Two’s Complement and Inverted Two’s Complement coding. requiring a critical measure of the analog input voltage. that is capacitively coupled into the analog section of the circuit. should be matched to avoid propagation delay mismatch. provide low impedance power planes. connected to the analog ground plane.

drive amplifier, and the user can configure the gain from –1 to –15. Data Ready signal are available through a 37-pin edge connector. Figure 14. AD9020/PCB Evaluation Board Block Diagram Dimensions shown in inches and (mm). Data Sheet changed from REV. B to REV. C.