AD9012AJ

AD9012 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9012 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 High Speed 8-Bit TTL A/D Converter GENERAL DESCRIPTION The AD9012 is an 8-bit, ultrahigh speed, analog-to-digital converter. The AD9012 is fabricated in an advanced bipolar process that allows operation at sampling rates up to one hun- dred megasamples/second. Functionally, the AD9012 is com- prised of 256 parallel comparator stages whose outputs are decoded to drive the TTL compatible output latches. The exceptionally wide large-signal analog input bandwidth of

160 MHz is due to an innovative comparator design and very

close attention to device layout considerations. The wide input bandwidth of the AD9012 allows very accurate acquisition of high speed pulse inputs without an external track-and-hold. The comparator output decoding scheme minimizes false codes, which is critical to high speed linearity. The AD9012 is available in two grades: one with 0.5 LSB linear- ity and one with 0.75 LSB linearity. Both versions are offered in

FEATURES

100 MSPS Encode Rate

Very Low Input Capacitance—16 pF Low Power—1 W TTL Compatible Outputs MIL-STD-883 Compliant Versions Available

APPLICATIONS

Digital Oscilloscopes/ATE Equipment Laser/Radar Warning Receivers Digital Radio Electronic Warfare (ECM, ECCM, ESM) Communication/Signal Intelligence FUNCTIONAL BLOCK DIAGRAM 256 255 128 127 D E C O D I N G L O G I C L A T C H R R R R/2 R/2 R R OVERFLOW INHIBIT ANALOG IN 1VREF REF MID 2VREF ENCODE GND HYSTERESIS 2VS D 2 D 3 D 4 D 5 D 6 D 7 D 8 (MSB) OVERFLOW AD9012 D 1 (LSB) 1VS an industrial grade, –25°C to +85°C, packaged in a 28-lead DIP and a 28-lead JLCC. The military temperature range devices, –55°C to +125°C, are available in ceramic DIP and LCC pack- ages and are compliant to MIL-STD-883 Class B. The AD9012 is available in versions compliant with MIL-STD- 883. Refer to the Analog Devices Military Products Databook or current AD9012/883B data sheet for detailed specifications.

REV. D–2– AD9012–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (+VS = +5.0 V; –V S = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted) Test AD9012AQ/AJ AD9012BQ/BJ AD9012SQ/SE AD9012TQ/TE Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 8 8 8 8 Bits DC ACCURACY Full VI 1.0 0.75 1.0 0.75 LSB Full VI 1.2 1.2 1.2 1.2 LSB No Missing Codes Full VI GUARANTEED GUARANTEED GUARANTEED GUARANTEED INITIAL OFFSET ERROR Top of Reference Ladder +25 °C I 7 15 7 15 7 15 7 15 mV Full VI 18 18 18 18 mV Bottom of Reference Ladder +25 °C I 6 10 6 10 6 10 6 10 mV Full VI 13 13 13 13 mV Offset Drift Coefficient Full V 25 25 25 25 mV/°C ANALOG INPUT Input Bias Current 1 +25°C I 60 200 60 200 60 200 60 200 mA Full VI 200 200 200 200 mA Input Resistance +25 °C I 25 200 25 200 25 200 25 200 k W Input Capacitance +25 °C III 16 18 16 18 16 18 16 18 pF Large Signal Bandwidth 2 +25°C V 160 160 160 160 MHz Analog Input Slew Rate 3 +25°C V 440 440 440 440 V/ ms REFERENCE INPUT Reference Ladder Resistance +25 °C VI 40 80 110 40 80 110 40 80 110 40 80 110 W Ladder Temperature Coefficient V 0.25 0.25 0.25 0.25 W /°C Reference Input Bandwidth +25 °C V 10 10 10 10 MHz DYNAMIC PERFORMANCE Conversion Rate +25 °C I 75 100 75 100 75 100 75 100 MSPS Aperture Delay +25 °C V 3.8 3.8 3.8 3.8 ns Aperture Uncertainty (Jitter) +25 °C V 15 15 15 15 ps Output Delay (t PD)4, 5 +25°C I 4 4.9 11 4 4.9 11 4 4.9 11 4 4.9 11 ns Transient Response 6 +25°CV 8 8 8 8 n s Overvoltage Recovery Time 7 +25°CV 8 8 8 8 n s Output Time Skew 4, 8 +25°C V 3.0 3.0 3.0 3.0 ns ENCODE INPUT Logic “1” Voltage4 Full VI 2.0 2.0 2.0 2.0 V Logic “0” Voltage4 Full VI 0.8 0.8 0.8 0.8 V Logic “1” Current Full VI 250 250 250 250 mA Logic “0” Current Full VI 400 400 400 400 mA Input Capacitance +25 °C V 2.5 2.5 2.5 2.5 pF Encode Pulsewidth (Low) 9 +25°C I 2.5 2.5 2.5 2.5 ns Encode Pulsewidth (High) 9 +25°C I 2.5 2.5 2.5 2.5 ns OVERFLOW INHIBIT INPUT

0 V Input Current Full VI 200 250 200 250 200 250 200 250 mA

Effective Bits 11 +25°C V 7.5 7.5 7.5 7.5 Bits In-Band Harmonics dc to 1.23 MHz +25 °C I 48 55 48 55 48 55 48 55 dBc dc to 9.3 MHz +25 °C V 50 50 50 50 dBc dc to 19.3 MHz +25 °C V 44 44 44 44 dBc Signal-to-Noise Ratio 12 +25°C I 46 47.6 46 47.6 46 47.6 46 47.6 dBc Noise Power Ratio 13 +25°C V 37 37 37 37 dBc DIGITAL OUTPUT Logic “1” Voltage Full VI 2.4 2.4 2.4 2.4 V Logic “0” Voltage Full VI 0.4 0.4 0.4 0.4 V POWER SUPPLY14 Positive Supply Current (+5.0 V) +25 °C I 33 45 33 45 33 45 33 45 mA Full VI 48 48 48 48 mA Supply Current (–5.2 V) +25 °C I 152 179 152 179 152 179 152 179 mA Full VI 191 191 191 191 mA Nominal Power Dissipation +25 °C V 955 955 955 955 mW Reference Ladder Dissipation +25 °C V 44 44 44 44 mW

accumulate on the human body and test equipment and can discharge without detection. precautions are recommended to avoid performance degradation or loss of functionality. 1Measured with Analog Input = 0 V. 2Measured by FFT analysis where fundamental is –3 dBc. 3Input slew rate derived from rise time (10% to 90%) of full-scale step input. 5Measured from ENCODE into data out for LSB only. 6For full-scale step input, 8-bit accuracy is attained in specified time. 7Recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage. bit-to-bit time skew differences. 9ENCODE signal rise/fall times should be less than 30 ns for normal operation. 10Measured at 75 MSPS encode rate. Harmonic data based on worst case harmonics. 11Analog input frequency = 1.23 MHz. 14Supplies should remain stable within – 5% for normal operation. Specifications subject to change without notice. specified temperatures. AC testing done on sample basis. V – Parameter is a typical value only. characterization testing for industrial devices. 2+VREF ‡ –VREF under all circumstances. Figure 1. Load Circuit

REV. D AD9012 –4– PIN FUNCTION DESCRIPTIONS Pin # Name Description 11 DIGITAL +V S One of three positive digital supply pins (nominally +5.0 V). 12 OVERFLOW INH OVERFLOW INHIBIT controls the data output coding for overvoltage inputs (AIN ‡ + VREF).

13 HYSTERESIS The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a

change from –5.2 V to –2.2 V at the Hysteresis control pin. 14+ V REF The most positive reference voltage for the internal resistor ladder. 15 ANALOG INPUT One of two analog input pins. Both analog input pins should be connected together. 16 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together. 17 ENCODE TTL level encode command input. ENCODE is rising edge sensitive. 18 DIGITAL +V S One of three positive digital supply pins (nominally +5.0 V). 19 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together. 10 ANALOG INPUT One of two analog input pins. Both analog inputs should be connected together. 11 –V REF The most negative reference voltage for the internal resistor ladder. 12 REF MID The midpoint tap on the internal resistor ladder. 13 DIGITAL +V S One of three positive digital supply pins (nominally +5.0 V). 14 DIGITAL –V S One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be connected together. 15 D 1 (LSB) Digital data output. D 1 (LSB) is the least significant bit of the digital output word. 16–19 D 2–D5 Digital data output. 20 DIGITAL GROUND One of two digital ground pins. Both digital grounds pins should be connected together. 21, 22 ANALOG –V S One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be connected together. 23 DIGITAL GROUND One of two digital ground pins. Both digital ground pins should be connected together. 24, 25 D 6, D7 Digital data output. 26 D 8 (MSB) Digital data output D 8 (MSB) is the most significant bit of the digital output word. 27 OVERFLOW Overflow data output. Logic HIGH indicates an input overvoltage (V IN > + VREF), if OVERFLOW INHIBIT is enabled (overflow enabled, floating). See OVERFLOW INHIBIT. 28 DIGITAL –V S One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be connected together. ANALOG OVERFLOW ENABLED (FLOATING) OVERFLOW INHIBITED (GND) INPUT OF D l D2 D3 D4 D5 D6 D7 D8 OF Dl D2 D3 D4 D5 D6 D7 D8 VIN ‡ + VREF 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VIN < + VREF 0 X X X X X X X X 0 X X X X X X X X PIN CONFIGURATIONS TOP VIEW (Not to Scale) AD9012 DIGITAL VS+ REF MID –VREF ANALOG INPUT ANALOG GROUND DIGITAL VS+ DIGITAL VS+ OVERFLOW INH HYSTERESIS +VREF ENCODE ANALOG GROUND ANALOG INPUT D 1 (LSB) D 2 D 3 D 4 D 5 DIGITAL GROUND ANALOG V S– DIGITAL VS– OVERFLOW D 8 (MSB) D 7 ANALOG V S– DIGITAL GROUND D 6 DIGITAL VS– TOP VIEW (Not to Scale) 28 2712342 6 12 13 14 15 16 17 18 D 7 D 6 DIGITAL GROUND ANALOG V S– ANALOG V S– D 5 ANALOG INPUT ANALOG GROUND ENCODE DIGITAL VS+ ANALOG INPUT –VREF +VREF HYSTERESIS OVERFLOW INH DIGITAL VS+ DIGITAL VS– OVERFLOW D 8 (MSB) REF MID DIGITAL VS+ DIGITAL VS– D 1 (LSB) D 2 D 3 AD9012 DIGITAL GROUND ANALOG GROUND

Figure 2. Timing Diagram

256 COMPARATOR

Figure 3. Input Output Circuits Figure 4. Burn-In Diagram

REV. D AD9012 –6–

APPLICATION INFORMATION

The AD9012 is compatible with all standard TTL logic fami- lies. However, to operate at the highest encode rates, the sup- porting logic around the AD9012 will need to be equally fast. Two possible choices are the AS and the ALS families. Which- ever of the TTL logic families is used, special care must be exercised to keep digital switching noise away from the analog circuits around the AD9012. The two most critical items are the digital supply lines and the digital ground return. The input capacitance of the AD9012 is an exceptionally low 16 pF. This allows the use of a wide range of input amplifiers, both hybrid and monolithic. To take full advantage of the

160 MHz input bandwidth of the AD9012, a hybrid amplifier

like the AD9610/AD9611 will be required. For those applica- tions that do not require the full input bandwidth of the AD9012, some of the more traditional monolithic amplifiers, like the AD846, should work very well. Overall performance with mono- lithic amplifiers can be improved by inserting a 40 W resistor in series with the amplifier output. The output data is buffered through the TTL compatible out- put latches. In addition to the latch propagation delay (t PD), all data is delayed by one clock cycle, before becoming available at the outputs. Both the analog-to-digital conversion cycle and the data transfer to the output latches are triggered on the rising edge of the TTL-compatible ENCODE signal (see timing diagram). The AD9012 also incorporates a HYSTERESIS control pin which provides from 0 mV to 10 mV of additional hysteresis in the comparator input stages. Adjustments in the HYSTERESIS control voltage may help to improve noise immunity and overall performance in harsh environments. The OVERFLOW INHIBIT pin of the AD9012 determines how the converter handles overrange inputs (AIN ‡ + V REF). In the “enabled” state (floating at –5.2 V), the OVERFLOW out- put will be at logic HIGH and all other outputs will be at logic LOW for overrange inputs (return-to-zero operation). In the “inhibited” state (tied to ground), the OVERFLOW output will be at logic LOW for overrange inputs, and all other digital out- puts will be at logic HIGH (nonreturn-to-zero operation). The AD9012 provides outstanding error rate performance. This is due to tight control of comparator offset matching and a fault tolerant decoding stage. Additional improvements in error rate are possible through the addition of hysteresis (see HYSTER- ESIS control pin). This level of performance is extremely impor- tant in fault sensitive applications such as digital radio (QAM). Dramatic improvements in comparator design and construction give the AD9012 excellent dynamic characteristics, namely SNR (signal-to-noise ratio). The 160 MHz input bandwidth and low error rate performance give the AD9012 an SNR of 47 dB with a 1.23 MHz input. High SNR performance is particularly im- portant in broadcast video applications where signals may pass through the converter several times before the processing is complete. Pulse signature analysis, commonly performed in advanced radar receivers, is another area that is especially dependent on high quality dynamic performance. LAYOUT SUGGESTIONS Designs using the AD9012, like all high-speed devices, must follow a few basic layout rules to insure optimum performance. Essentially, these guidelines are meant to avoid many of the problems associated with high-speed designs. The first require- ment is for a substantial ground plane around and under the AD9012. Separate ground plane areas for the digital and analog components may be useful, but the separate grounds should be connected together at the AD9012 to avoid the effects of “ground loop” currents. The second area that requires an extra degree of attention involves the three reference inputs, +V REF, REFMID, and –VREF. The +VREF input and the –VREF input should both be driven from a low impedance source (note that the +V REF input is typically tied to analog ground). A low drift amplifier should provide satisfactory results, even over an extended temperature range. Adjustments at the REF MID input may be useful in im- proving the integral linearity by correcting any reference ladder skews. The reference inputs should be adequately decoupled to ground through 0.1 mF chip capacitors to limit the effects of system noise on conversion accuracy. The power supply pins must also be decoupled to ground to improve noise immunity; 0.1 mF and 0.01 mF chip capacitors should be very effective. The analog input signal is brought into the AD9012 through two separate input pins. It is very important that the two input pins be driven symmetrically with equal length electrical connections. Otherwise, aperture delay errors may degrade converter performance at high frequencies. 100V 2N3906 OVERFLOW D 8 (MSB) D 7 D 6 D 5 D 4 D 3 D 2 D 1 (LSB) –5.2V+5.0V 0.01mF0.1mF0.01mF ENCODE A IN A IN –VREF +VREF 0.1mF 10V 0.1mF AD741 AD9611 40V AD9012 EQUAL DISTANCE 50V TTL ENCODE INPUT ANALOG INPUT (0 TO +2V) 1kV 4kV –15V 1.5kV 50V 0.1mF NYQUEST FILTER Figure 5. Typical Application

25 PIN

Figure 6. Evaluation Circuit Figure 7. Dynamic Performance

REV. D AD9012 –8– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C1169c–0–8/99PRINTED IN U.S.A. 28-Lead JLCC (J-28A) 0.0066 (0.167) 0.0054 (0.137) 0.171 (4.34) MAX 0.044 (1.118) 0.034 (0.864) 0.030 (0.762) 0.026 (0.660) 0.021 (0.534) 0.017 (0.432) 0.430 (10.922) 0.410 (10.414) 0.112 (1.702) 0.092 (1.194) BOTTOM VIEW 0.025 (0.635) 0.019 (0.483) PIN 1 TOP VIEW (PINS DOWN) 25 19 0.050 (1.27) BSC 0.300 (7.62) TYP SQ0.498 (12.649) 0.478 (12.141) SQ0.456 (11.582) 0.444 (11.278) 28-Lead Cerdip (Q-28) 11 4 0.525 (13.33) 0.515 (13.08) 1.490 (37.84) MAX PIN 1 158 0.62 (15.74) 0.59 (14.93) 0.012 (0.305) 0.008 (0.203) SEATING PLANE 0.22 (5.59) MAX 0.18 (4.57) MAX 0.02 (0.5) 0.016 (0.406) 0.11 (2.79) 0.099 (2.28) 0.06 (1.52) 0.05 (1.27) 0.125 (3.175) MIN GLASS SEALANT LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN PLATED KOVAR OR ALLOY 42 28-Terminal Leadless Chip Carrier (E-28A) 0.100 (2.54)1 0.064 (1.63) 28 5 BOTTOM VIEW 0.028 (0.71) 0.022 (0.56) 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) REF 0.020 3 458 (0.51 3 458) REF PIN 1 INDEX 0.040 3 458 (1.02 3 458) REF 3 PLCS 0.055 (1.40) 0.045 (1.14) 0.458 (11.63)2 0.442 (11.23) TOP VIEW NOTES 1THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS. 2APPLIES TO ALL FOUR SIDES. TERMINALS ARE GOLD PLATED OR SOLDER DIPPED.