AD9002SE/883B

AD9002 AD | Alldatasheet

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REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a High Speed 8-Bit Monolithic A/D Converter AD9002 FUNCTIONAL BLOCK DIAGRAM 256 255 128 127 D E C O D I N G L O G I C L A T C H R R R R/2 R/2 R R OVERFLOW INHIBIT ANALOG IN +VREF REF MID –VREF ENCODE ENCODE GND HYSTERESIS –VS BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 (MSB) OVERFLOW AD9002 BIT 1 (LSB)

FEATURES

150 MSPS Encode Rate

Low Input Capacitance: 17 pF Low Power: 750 mW –5.2 V Single Supply MIL-STD-883 Compliant Versions Available

APPLICATIONS

Digital Oscilloscopes/ATE Equipment Laser/Radar Warning Receivers Digital Radio Electronic Warfare (ECM, ECCM, ESM) Communication/Signal Intelligence GENERAL DESCRIPTION The AD9002 is an 8-bit, high speed, analog-to-digital converter. The AD9002 is fabricated in an advanced bipolar process that allows operation at sampling rates in excess of 150 megasamples/ second. Functionally, the AD9002 is comprised of 256 parallel comparator stages whose outputs are decoded to drive the ECL compatible output latches. An exceptionally wide large signal analog input bandwidth of

160 MHz is due to an innovative comparator design and very

close attention to device layout considerations. The wide input bandwidth of the AD9002 allows very accurate acquisition of high speed pulse inputs, without an external track-and-hold. The comparator output decoding scheme minimizes false codes, which is critical to high speed linearity. The AD9002 provides an external hysteresis control pin that can be used to optimize comparator sensitivity to further im- prove performance. Additionally, the AD9002’s low power dissipation of 750 mW makes it usable over the full extended temperature range. The AD9002 also incorporates an overflow bit to indicate overrange inputs. This overflow output can be disabled with the overflow inhibit pin. The AD9002 is available in two grades, one with 0.5 LSB lin- earity and one with 0.75 LSB linearity. Both versions are offered in an industrial grade, –25°C to +85°C, packaged in a 28-lead DIP and a 28-leaded JLCC. The military temperature range devices, –55°C to +125°C, are available in ceramic DIP and LCC packages and comply with MIL-STD-883 Class B. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999

ELECTRICAL CHARACTERISTICS (–VS = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted) AD9002AD/AJ AD9002BD/BJ AD9002SD/SE AD9002TD/TE Parameter Temp Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 8 8 8 8 Bits DC ACCURACY Full 1.0 0.75 1.0 0.75 LSB Full 1.2 1.2 1.2 1.2 LSB No Missing Codes Full GUARANTEED GUARANTEED GUARANTEED GUARANTEED INITIAL OFFSET ERROR Top of Reference Ladder +25 °C 8 14 8 14 8 14 8 14 mV Full 17 17 17 17 mV Bottom of Reference Ladder +25 °C 4 10 4 10 4 10 4 10 mV Full 12 12 12 12 mV Offset Drift Coefficient Full 20 20 20 20 mV/°C ANALOG INPUT Input Bias Current 1 +25°C 60 200 60 200 60 200 60 200 mA Full 200 200 200 200 mA Input Resistance +25 °C 25 200 25 200 25 200 25 200 k W Input Capacitance +25 °C 1 72 2 1 72 2 1 72 2 1 72 2 p F Large Signal Bandwidth 2 +25°C 160 160 160 160 MHz Input Slew Rate 3 +25°C 440 440 440 440 V/ ms REFERENCE INPUT Reference Ladder Resistance +25 °C 40 80 110 40 80 110 40 80 110 40 80 110 W Ladder Temperature Coefficient 0.25 0.25 0.25 0.25 W /°C Reference Input Bandwidth +25 °C 1 0 1 01 01 0 M H z DYNAMIC PERFORMANCE Conversion Rate +25 °C 125 150 125 150 125 150 125 150 MSPS Aperture Delay +25 °C 1.3 1.3 1.3 1.3 ns Aperture Uncertainty (Jitter) +25 °C 1 5 1 51 51 5 p s Transient Response 6 +25°C 6 666 n s Overvoltage Recovery Time 7 +25°C 6 666 n s Output Rise Time 4 +25°C 3.0 3.0 3.0 3.0 ns Output Fall Time 4 +25°C 2.5 2.5 2.5 2.5 ns Output Time Skew 4, 8 +25°C 0.6 0.6 0.6 0.6 ns ENCODE INPUT Logic “1” Voltage4 Full –1.1 –1.1 –1.1 –1.1 V Logic “0” Voltage4 Full –1.5 –1.5 –1.5 –1.5 V Logic “1” Current Full 150 150 150 150 mA Logic “0” Current Full 120 120 120 120 mA Input Capacitance +25 °C 3 333 p F Encode Pulsewidth (Low) 9 +25°C 1.5 1.5 1.5 1.5 ns Encode Pulsewidth (High) 9 +25°C 1.5 1.5 1.5 1.5 ns OVERFLOW INHIBIT INPUT

0 V Input Current Full 144 300 144 300 144 300 144 300 mA

Effective Bits 11 +25°C 7.6 7.6 7.6 7.6 Bits In-Band Harmonics dc to 1.23 MHz +25 °C 4 85 5 4 85 5 4 85 5 4 85 5 d B dc to 9.3 MHz +25 °C 5 0 5 05 05 0 d B dc to 19.3 MHz +25 °C 4 4 4 44 44 4 d B Signal-to-Noise Ratio 12 +25°C 46 47.6 46 47.6 46 47.6 46 47.6 dB Two Tone Intermod Rejection 13 +25°C 6 0 6 06 06 0 d B DIGITAL OUTPUTS 4 Logic “1” Voltage Full –1.1 –1.1 –1.1 –1.1 V Logic “0” Voltage Full –1.5 –1.5 –1.5 –1.5 V POWER SUPPLY14 Supply Current (–5.2 V) +25 °C 145 175 145 175 145 175 145 175 mA Full 200 200 200 200 mA Nominal Power Dissipation +25 °C 750 750 750 750 mW Reference Ladder Dissipation +25 °C 5 0 5 05 05 0 m W REV. D–2– AD9002–SPECIFICATIONS NOTES 1Measured with AIN = 0 V. 2Measured by FFT analysis where fundamental is –3 dBc. 3Input slew rate derived from rise time (10 to 90%) of full scale input. 40utputs terminated through 100 W to –2 V. 5Measured from ENCODE in to data out for LSB only. 6For full-scale step input, 8-bit accuracy is attained in specified time. 7Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage. 8Output time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences. 9ENCODE signal rise/fall times should be less than 10 ns for normal operation. 10Measured at 125 MSPS encode rate. 11Analog input frequency = 1.23 MHz. 12RMS signal to rms noise, with 1.23 MHz analog input signal. 13Input signals 1 V p-p @ 1.23 MHz and 1 V p-p @ 2.30 MHz. 14Supplies should remain stable within – 5% for normal operation. 15Measured at –5.2 V – 5%. Specifications subject to change without notice.

–3–REV. D ABSOLUTE MAXIMUM RATINGS 1 S to +0.5 V Operating Temperature Range Junction Temperature NOTES 1Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2+VREF ‡ –VREF under all circumstances. 3Maximum junction temperature (t J max) should not exceed +175 °C for ceramic packages, and +150 °C for plastic packages: tJ = PD (qJA) + tA PD ( qJC) + t C where PD = power dissipation q JA = thermal impedance from junction to ambient ( °C/W) qJC = thermal impedance from junction to case ( °C/W) tA = ambient temperature ( °C) tC = case temperature ( °C) Typical thermal impedances are: Ceramic DIP qJA = 56°C/W; qJC = 20°C/W Ceramic LCC qJA = 69°C/W; qJC = 23°C/W PLCC qJA = 60°C/W; qJC = 19°C/W. Recommended Operating Conditions Input Voltage Parameter Min Nominal Max +VREF –VREF 0.0 V +0.1 –VREF –2.1 –2.0 +V REF Analog Input –V REF +VREF EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. Test Level II – 100% production tested at +25 °C, and sample tested at specified temperatures. Test Level III – Sample tested only. Test Level IV – Parameter is guaranteed by design and characterization testing. Test Level V – Parameter is a typical value only. Test Level VI – All devices are 100% production tested at +25°C. 100% production tested at tempera- ture extremes for extended temperature devices; sample tested at temperature ex- tremes for commercial/industrial devices. ORDERING GUIDE Package Model Linearity Temperature Range Option * AD9002AD 0.75 LSB –25 °C to +85°C D-28 AD9002BD 0.50 LSB –25 °C to +85°C D-28 AD9002AJ 0.75 LSB –25 °C to +85°C J-28 AD9002BJ 0.50 LSB –25 °C to +85°C J-28 AD9002SD/883B 0.75 LSB –55 °C to +125°C D-28 AD9002SE/883B 0.75 LSB –55 °C to +125°C E-28A AD9002TD/883B 0.50 LSB –55 °C to +125°C D-28 AD9002TE/883B 0.50 LSB –55 °C to +125°C E-28A *D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Chip Carrier, J-Formed Leads. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9002 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

–4– REV. D FUNCTIONAL DESCRIPTION Pin # Name Description 1 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together. 2 OVERFLOW INH OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs. tupnIgolanA delbanEwolfrevO )V2.5–rognitaolF( Dfo8 D–1 wolfrevO) DNG(detibihnI Dfo8 D–1 V NI V+> FER 0000000011 11111110 V NI £ V+ FER XXXXXXXX0X XXXXXXX0 3 HYSTERESIS The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change 4+ V REF The most positive reference voltage for the internal resistor ladder. 5 ANALOG INPUT One of two analog input pins. Both analog input pins should be connected together. 6 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together. 7 ENCODE Noninverted input of the differential encode input. This pin is driven in conjunction with ENCODE. Data is latched on the rising edge of the ENCODE signal. 8 ENCODE Inverted input of the differential encode input. This pin is driven in conjunction with ENCODE. 9 ANALOG GROUND One of two analog ground pins. Both analog ground pins should be connected together. 10 ANALOG INPUT One of two analog input pins. Both analog inputs should be connected together. 11 –V REF The most negative reference voltage for the internal resistor ladder. 12 REF MID The midpoint tap on the internal resistor ladder. 13 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together.

14 DIGITAL –V

S One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be con- nected together. 15 D1 (LSB) Digital data output. 16–19 D2–D5 Digital data output. 20 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together. 21, 22 ANALOG –V S One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be con- nected together. 23 DIGITAL GROUND One of four digital ground pins. All digital ground pins should be connected together. 24, 25 D6, D7 Digital data output. 26 D8 (MSB) Digital data output. 27 OVERFLOW Overflow data output. Logic high indicates an input overvoltage (V IN > +VREF) if OVERFLOW INHIBIT is enabled (overflow enabled, –5.2 V). See OVERFLOW INHIBIT. 28 DIGITAL –V S One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be connected together. DIP TOP VIEW (Not to Scale) AD9002 DIGITAL GROUND REF MID –VREF ANALOG INPUT ANALOG GROUND ENCODE DIGITAL GROUND OVERFLOW INH HYSTERESIS +VREF ENCODE ANALOG GROUND ANALOG INPUT D1(LSB) DIGITAL GROUND ANALOG –V S DIGITAL –VS OVERFLOW D8(MSB) ANALOG –V S DIGITAL GROUND DIGITAL –VS LCC 28 2712342 6 12 13 14 15 16 17 18 TOP VIEW (Not to Scale) DIGITAL GROUND ANALOG –V S ANALOG –V S ANALOG INPUT ANALOG GROUND ENCODE ENCODE ANALOG INPUT –VREF +VREF HYSTERESIS OVERFLOW INH DIGITAL GROUND DIGITAL –VS OVERFLOW D8(MSB) REF MID DIGITAL GROUND DIGITAL –VS D1(LSB) AD9002 DIGITAL GROUND ANALOG GROUND JLCC TOP VIEW (Not to Scale) TOP VIEW (Not to Scale) 25 24 23 22 21 20 19 5 6 7 8 9 10 11 D1(LSB) DIGITAL –VS REF MID D8(MSB) OVERFLOW DIGITAL –VS DIGITAL GROUND OVERFLOW INH HYSTERESIS +VREF DIGITAL GROUND ANALOG –V S DIGITAL GROUND ANALOG INPUT ANALOG GROUND ENCODE ENCODE ANALOG GROUND ANALOG INPUT –VREF ANALOG –V S AD9002 DIGITAL GROUND PIN DESIGNATIONS

–6– REV. D LAYOUT SUGGESTIONS Designs using the AD9002, like all high speed devices, must follow a few basic layout rules to insure optimum performance. Essentially, these guidelines are meant to avoid many of the problems associated with high speed designs. The first require- ment is for a substantial ground plane around and under the AD9002. Separate ground plane areas for the digital and analog components may be useful, but these separate grounds should be connected together at the AD9002 to avoid the effects of “ground loop” currents. The second area that requires an extra degree of attention in- volves the three reference inputs, +V REF, REFMID, and –VREF. The +VREF input and the –VREF input should both be driven from a low impedance source (note that the +V REF input is typically tied to analog ground). A low drift amplifier should provide satisfactory results, even over an extended temperature range. Adjustments at the REF MID input may be useful in im- proving the integral linearity by correcting any reference ladder skews. The application circuit shown below demonstrates a simple and effective means of driving the reference circuit. The reference inputs should be adequately decoupled to ground through 0.1 mF chip capacitors to limit the effects of system noise on conversion accuracy. The power supply pins must also be decoupled to ground to improve noise immunity; 0.1 mF and 0.01 mF chip capacitors are recommended. The analog input signal is brought into the AD9002 through two separate input pins. It is very important that the two input pins be driven symmetrically with equal length electrical con- nections. Otherwise, aperture delay errors may degrade con- verter performance at high frequencies.

APPLICATION INFORMATION

The AD9002 is compatible with all standard ECL logic families, including 10K and 10KH. 100K ECL’s logic levels are tempera- ture compensated, and are therefore compatible with the AD9002 (and most other ECL device families) only over a limited temperature range. To operate at the highest encode rates, the supporting logic around the AD9002 will need to be equally fast. Whichever of the ECL logic families is used, special care must be exercised to keep digital switching noise away from the analog circuits around the AD9002. The two most critical items are digital supply lines and digital ground return. The input capacitance of the AD9002 is an exceptionally low 17 pF. This allows the use of a wide range of input amplifiers, both hybrid and monolithic. To take full advantage of the wide input bandwidth of the AD9002, a hybrid amplifier such as the AD9610 will be required. For those applications that do not require the full input bandwidth of the AD9002, more tradi- tional monolithic amplifiers, such as the AD846, will work very well. Overall performance with any amplifier can be improved by inserting a 10 W resistor in series with the amplifier output. The output data is buffered through the ECL compatible output latches. All data is delayed by one clock cycle, in addition to the latch propagation delay (t PD), before becoming available at the outputs. Both the analog-to-digital conversion cycle and the data transfer to the output latches are triggered on the rising edge of the differential, ECL compactible ENCODE signal (see timing diagram). In applications where only a single-ended signal is available, the AD96685, a high speed, ECL voltage comparator, can be employed to generate the differential sig- nals. All ECL signals (including the overflow bit) should be terminated properly to avoid ringing and reflection. The AD9002 also incorporates a HYSTERESIS control pin which provides from 0 mV to 10 mV of additional hysteresis in the comparator input stages. Adjustments in the HYSTERESIS control voltage may help improve noise immunity and overall performance in harsh environments. The OVERFLOW INHIBIT pin of the AD9002 determines how the converter handles overrange inputs (AIN ‡ +V REF). In the “enabled” state (floating at –5.2 V), the OVERFLOW out- put will be at logic HIGH and all other outputs will be at logic LOW for overrange inputs (return-to-zero operation). In the “inhibited” state (tied to ground), the OVERFLOW output will be at logic LOW, and all other outputs will be at logic HIGH for overrange inputs (nonreturn-to-zero operation). The AD9002 provides outstanding error rate performance. This is due to tight control of comparator offset matching and a fault tolerant decoding stage. Additional improvements in error rate are possible through the addition of hysteresis (see HYSTER- ESIS control pin). This level of performance is extremely im- portant in fault-sensitive applications such as digital radio (QAM). Dramatic improvements in comparator design and construction give the AD9002 excellent dynamic characteristics, especially SNR (signal-to-noise ratio). The 160 MHz input bandwidth and low error rate performance give the AD9002 an SNR of 48 dB with a 1.23 MHz input. High SNR performance is par- ticularly important in wide bandwidth applications, such as pulse signature analysis, commonly performed in advanced radar receivers. 100V 2N3906 OVERFLOW D8 (MSB) D1 (LSB)–5.2D–5.2A 0.01mF0.1mF0.1mF0.01mF ENCODE ENCODE A IN A IN –VREF +VREF 0.1mF 10V 0.1mF AD741 AD9611 AD96685 40V AD9002 EQUAL DISTANCE 50V ENCODE INPUT (GROUND THRESHOLD) ANALOG INPUT (0V TO +2V) 1kV 4kV –15V 1.5kV 50V NYQUEST FILTER Figure 5. Typical Application

100114 LINE DRIVER OUTPUTS

37 PIN

Figure 6. AD9002 Evaluation Circuit

125 MSPS ENCODE RATE

Figure 7. Dynamic Performance

–8– REV. D OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C1043d–0–11/99PRINTED IN U.S.A. 28-Lead Ceramic Side-Brazed DIP (D-28) 11 4 PIN 1 0.005 (0.13) MIN 0.310 (7.87) 0.220 (5.59) 0.098 (2.49) MAX SEATING PLANE0.110 (2.79) 0.090 (2.29) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) MIN 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) MAX 1.490 (37.85) MAX 0.606 (15.4) 0.58 (14.74) 0.015 (0.38) 0.008 (0.20) 28-Lead Ceramic Leadless Chip Carrier (E-28A) 0.458 (11.63) 0.442 (11.23) SQ TOP VIEW 28 5 BOTTOM VIEW 0.028 (0.71) 0.022 (0.56)

458 TYP

0.015 (0.38) MIN 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) BSC 0.075 (1.91) REF 0.011 (0.28) 0.007 (0.18) R TYP 0.095 (2.41) 0.075 (1.90) 0.150 (3.51) BSC 0.300 (7.62) BSC 0.200 (5.08) BSC 0.075 (1.91) REF 0.458 (11.63) MAX SQ 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37)28-Leaded JLCC (J-28) 0.171 (4.34) MAX 0.019 60.002 (0.483 60.051) 0.006 60.0006 (0.152 60.015) 0.039 60.005 (0.991 60.127) 0.028 60.002 (0.711 60.051) 0.420 60.010 (10.668 60.254) 0.102 60.010 (1.448 60.254) PIN 1 TOP VIEW (PINS DOWN) 25 19 0.050 (1.27) BSC 0.300 (7.62) TYP 0.450 60.006 (11.43 60.152) SQ SQ BOTTOM VIEW 0.022 60.003 (0.559 60.076) 0.488 60.010 (11.43 60.254)