AD9000

AD9000 High Speed 6-Bit A/D Converter

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Technical content

REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD9000 Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 High Speed 6-Bit A/D Converter FUNCTIONAL BLOCK DIAGRAM

FEATURES

77 MSPS Encode Rate

MIL-STD-883 Compliant Versions Available

APPLICATIONS

Electronic Warfare (ECM, ECCM, ESM) Radar Guidance DigitizersGENERAL DESCRIPTION The AD9000 is a 6-bit, high speed, analog-to-digital converter with ECL compatible outputs and a bipolar input stage. The AD9000 is fabricated in a high performance bipolar process that allows encode rates up to 77 MSPS. The AD9000 employs the standard flash converter architecture based on 64 individual comparators which simultaneously determine the precise analog signal level. The comparators are followed by two stages of decoding logic, allowing the AD9000 to operate with a very low error rate. The low 35 pF input capacitance of the AD9000 greatly simplifies the analog driver stage. An overflow output bit is also incorporated into the AD9000 design as is a hysteresis control pin to modify compara- tor sensitivity. The AD9000 is offered as both a commercial temperature range device, 0°C to +70°C, and as an extended temperature range device, –55°C to +125°C. Both versions are available packaged in a 16-pin ceramic DIP. The extended temperature range device is also available in a 28-pin ceramic LCC package. The extended temperature range versions are offered as fully compli- ant MIL-STD-883 Class B devices.

AD9000–SPECIFICATIONS –2– REV. A

ELECTRICAL CHARACTERISTICS

08C to +708C –55 8C to +1258C AD9000JD AD9000SD/SE Parameter Temp Min Typ Max Min Typ Max Units RESOLUTION 6 6 Bits DC ACCURACY Differential Linearity +25 °C 0.25 0.5 0.25 0.5 LSB Full 1.0 1.0 LSB Integral Linearity +25 °C 0.25 0.5 0.25 0.5 LSB Full 1.0 1.0 LSB No Missing Codes Full GUARANTEED GUARANTEED INITIAL OFFSET ERROR Top of Reference Ladder +25 °C 0.3 7/8 0.3 7/8 LSB Full 1.5 1.5 LSB Bottom of Reference Ladder +25 °C 0.25 7/8 0.25 7/8 LSB Full 1.5 1.5 LSB Offset Drift Coefficient Full 145 145 µV/°C ANALOG INPUT Input Voltage Range Full ± 2.0 V ± 2.0 V V Input Bias Current (Sampling) 1 Full 800 800 µA Input Bias Current (Latched) 1 Full 20 20 µA Input Resistance +25 °C 3.0 3.0 k Ω Input Capacitance +25 °C3 5 5 0 3 5 5 0 p F Full Power Bandwidth2 +25°C 20 20 MHz REFERENCE INPUT3, 4 Reference Ladder Resistance +25 °C 80 200 80 200 Ω Ladder Temperature Coefficient 0.275 0.275 Ω /°C Reference Input Bandwidth +25 °C 20 20 MHz DYNAMIC PERFORMANCE5 Conversion Rate +25 °C 5 07 0 7 57 7 M H z Conversion Time (+ 1 Clock) +25 °C 20 13.3 ns Aperture Delay (tD) +25 °C2 2 n s Aperture Uncertainty (Jitter) +25 °C2 5 2 5 p s Output Propagation Delay (t PD)6 +25°C8 1 2 8 1 2 n s Output Hold Time (tOH)7 +25°C8 1 4 8 1 4 n s Transient Response8 +25°C1 3 1 3 n s Overvoltage Recovery Time 9 +25°C1 1 1 1 n s Output Rise Time10 +25°C 5.0 4.5 ns Output Fall Time10 +25°C 5.0 4.5 ns Output Time Skew +25 °C 0.4 0.4 ns ENCODE INPUT Logic “l” Voltage Full –1.1 –1.1 V Logic “0” Voltage Full –1.5 –1.5 V Logic “1” Current Full 100 100 µA Logic “0” Current Full 100 100 µA Input Capacitance +25 °C 2.5 5.0 2.5 5.0 pF ENCODE Pulse Width High (t PWH) +25 °C 6.6 6.6 ns ENCODE Pulse Width Low (t PWL) +25 °C 6.6 6.6 ns (Supply Voltages = –5.2 V and +5.0 V; Differential Reference Voltage = 2.0 V unless otherwise noted)

08C to +708C –55 8C to +1258C AD9000JD AD9000SD/SE Parameter Temp Min Typ Max Min Typ Max Units AC LINEARITY11 Dynamic Linearity12 +25°C 0.5 0.5 LSB In-Band Harmonics (DC to l MHz) +25 °C 44 44 dBc (l MHz to 5 MHz) +25 °C 42 42 dBc (5 MHz to 8 MHz) +25 °C 38 38 dBc Signal-to-Noise Ratio 13 +25°C 3 13 3 3 13 3 d B Signal-to-Noise Ratio 14 +25°C 4 04 2 4 04 2 d B Two Tone Intermodulation Rejection15 +25°C 46 46 dBc Noise Power Ratio (NPR) 16 +25°C 30 30 dBc DIGITAL OUTPUTS5 Logic “l” Voltage Full –1.1 –1.1 V Logic “0” Voltage Full –1 .5 –1.5 V POWER SUPPLY17 Positive Supply Current (+5.0 V) +25 °C6 0 7 0 6 0 7 0 m A Full 75 75 mA Negative Supply Current (–5.2 V) +25 °C6 8 8 0 6 8 8 0 m A Full 85 85 mA Nominal Power Dissipation +25 °C 675 675 mW Reference Ladder Dissipation +25 °C2 0 2 0 m W AD9000 –3–REV. A (Continued) NOTES 1 AIN = +VREF. 2 Determined by 3 dB reduction in reconstructed output at 75 MSPS.

3 Under normal operating conditions, the analog input voltages should not

exceed nominal ± 2 V operating range, nor the supply voltages (+V S and –VS), whichever is smaller.

4 Under normal operating conditions the differential reference voltage may

range from ± 0.5 V to ± 2 V; +V REF ≥ –VREF. 5 Output terminated with 100 Ω resistors to –2.0 V. 6 Measured from the leading edge of ENCODE to data out on Bit 1 (MSB). 7 Measured from the trailing edge of ENCODE to data out on Bit 1 (MSB). 8 For full-scale step input, 6-bit accuracy is attained in specified time.

9 Recovers to 6-bit accuracy in specified time, after 150% full-scale input

overvoltage. 10 Measured on Bit 1 (MSB) only. 11 Measured at 50 MSPS encode rate. 12 Analog input frequency = 15 MHz. 13 RMS signal to RMS noise, with 540 kHz analog input signal. 14 Peak-to-peak signal to rms noise, with 540 kHz analog input signal. 15 f1 = 9.3 MHz, f 2 = 7.6 MHz; Encode = 42 MHz. 16 DC to 8.2 MHz noise bandwidth with 3.886 MHz slot. 17 Supply voltage should remain stable within ± 5% for normal operation. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 Analog Input Voltages (A Operating Temperature Range NOTES 1Absolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional oper- ability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Under normal operating conditions, the analog input voltages should not exceed nominal +2 V operating range, nor the supply voltages (+V S and –VS), whichever is smaller. 3Under normal operating conditions the differential reference voltage may range from ± 0.5 V to ± 2 V; +VREF ≥ –VREF. 4Typical thermal impedances . . . 16-Pin Ceramic θJA = 67°C/W; θJC = 7°C/W 28-Pin LCC θJA = 62°C/W; θJC = 14°C/W

–4– REV. A WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9000 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. DIE LAYOUT MECHANICAL INFORMATION or 1 mil Gold; Gold Ball Bonding ORDERING GUIDE 1 Temperature Package Device Range Description Option 2 AD9000JD 0 °C to +70°C 16-Pin DIP, Industrial D-16 AD9000SD –55 °C to +125°C 16-Pin DIP D-16 AD9000SE –55 °C to +125°C 28-Pin LCC E-28A NOTES 1MIL-STD-883 versions available, contact factory. 2D = Ceramic DIP; E = Leadless Ceramic Chip Carrier. PIN DESIGNATIONS PIN DESCRIPTIONS Pin Name Description –VS Negative supply terminal, nominally –5.2 V. ANALOG GROUND Analog ground return. All grounds should be connected together near the AD9000. VH The hysteresis control voltage varies the comparator hysteresis from 15 mV to 50 mV, for a change of 0 V to +3 V at the hysteresis control pin. ENCODE The ENCODE pin controls the conversion cycle. Encode is rising edge sensitive and should be driven with a 50% duty-cycle waveform under normal conditions. REF The most negative reference voltage for the internal resistor ladder. AIN Analog input pin. +VS Positive supply terminal, nominally +5.0 V. +VREF Most positive reference voltage of the internal resistor ladder. BIT 6 (LSB) One of six digital outputs. BIT 6 (LSB) is the least-significant-bit of the digital output. BIT 5 – BIT 2 One of six digital outputs. BIT 1 (MSB) One of six digital outputs. BIT 1 (MSB) is the most-significant-bit of the digital output. OVERFLOW Overflow data output. Logic high indicates an input overvoltage (A IN ≥ +VREF). DIGITAL GROUND Digital ground return. All grounds should be connected together near the AD9000.

–7–REV. A TYPICAL APPLICATION The AD9000 is a relatively flexible device that can be config- ured in a number of ways. One very useful feature of the AD9000 is the open emitter outputs. The open emitters allow the outputs of several AD9000s to be OR-wired in stacking applications for increased resolution. This kind of application depends on the return-to-zero nature of the output bits when AIND≥ + V REF (overflow). In circuits that employ only one AD9000, this is not always an advantage. The circuit below illustrates one method of converting the outputs to nonreturn- to-zero. The 10197 (standard 10K ECL logic) hex-AND group senses the active OVERFLOW output and forces all other bits to logic HIGH. The 10151 latch is not required for AD9000 applica- tions, but it may ease data transfer sensitivities in asynchronous data collection systems. The reference driver circuits should provide a low source im- pedance to prevent noise on the reference inputs from affecting the AD9000’s accuracy. This is accomplished to a large extent by adequately decoupling the reference pins to ground. An improved method is employed below. The reference voltages (+V REF, –VREF) are buffered by a transistor/amplifier combina- tion. This has the advantages of wide bandwidth (hence low impedance over a wide frequency range to eliminate high frequency noise components), and improved temperature stability. Figure 6.

C807a–21–8/87PRINTED IN U.S.A. or an extended temperature range device installed. Figure 7. PCB Block Diagram Dimensions shown in inches and (mm).