AD890

AD890 AD | Alldatasheet

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| ANALOG Precision, Wideband DEVICES Channel Processing Element FEATURES ‘AD890 LOCK ‘An 80 MHz Bandwidth Permitting a 50 Mb/s Data FUNCTIONAL BLOCK DIAGRAM Transfer Rate A Variable Gain Amplifier with 30 dB max Gain soon and 40 dB Control Range “ = | fal a ‘Two Gain of 4 RF Buffers cna, | fee 200 © Differential Load Drive Capability ese a Ly rou A Pair of Precision Rectifiers cums, | ott SS Y7 mone AGC Level and Threshold Outputs Fs} CF siete [> f=] "sont An Averaging, High Gain Sample-and-Hold for ebtien EE} romero [=] emits Accurate AGC Operation wa pom ba) ewe Typical Gain Drift in Hold Mode: 0.2 dB/ms worn +E Gains Trimmed and Temperature Compensated oa C {oF bail AGC Operation Independent of AGC Level seas Eh ones fa] are Symmetrical AGC Attack/Decay Times ae HH Vane om 11s AGC Attack/Decay Times Using a 1000 pF ale | | (Ee External Capacitor seo" ees fa) "sso Suitable for Use as an Accurate Video Programmable “conor fy] Sia) aay Gain Amplifier poet P<) Dynamic Clamp Ensures Fast Recovery After Write to ee Read Transients AGC AF Output Level Is Internally Preset 3 | the “Qualifier Threshold” output may be used for creating a PRODUCT DESCRIPTION data qualification level. A second rectifier is used to drive the ‘The ADE90 is primarily intended for high performance disk sample-and-hold circuitry. subsystem use, and as such it is configured around the classic ‘The 80 MHz bandwidth of the AD890 ensures good phase lin- read channel processing block diagram. Tt is intended to be con- —egrity up to 50 MHz. Thus, data transfer rates in excess of nected between the head preamplifier and the qualification cit- So stive can be supported with good error rates and predictable cuitry required for digital data recovery. When used with the ahaiet behaviors ‘AD891 rigid disk data qualifier, data transfer rates in excess of - 50 Mb/s can be processed. The ADI is vale in bth Hpi imine edi pack A temperature-compensated AGC loop, with an exponential Ee eC Package and is specified to operate transfer characteristic, permits optimal settling and allows for over the 0 to +70°C commercial temperature range. predictable performance in the classic single integrator control Joop configuration. Fast acquisition and low droop while in the hold mode allow for AGC operation to be performed within the sector header without compromising channel behavior when reading data ‘The ADB90 processing element has the flexibility to perform both continuous and sampled AGC functions; itis also ideal for embedded, dedicated, or mixed servo applications. Two user- defined filter/equalizer stages may be employed, thus allowing maximum design flexibility. This greatly simplifies the design of the overall channel characteristics. Using the AD890, the de- signer no longer needs to resort to passive techniques to isolate network functions; this avoids problems of signal loss and inter action. Two low offset, 100 MHz, full wave rectifiers provide the capability to track a 1 V peak signal. The rectifier generating MASS STORAGE COMPONENTS 9-7

SPECIFICATIONS (@ +25°C and +5 V de, unless otherwise noted) ADS) Parameter Conditions Min Typ Max Units VARIABLE GAIN AMPLIFIER Maximum Gain! 29.0 30.0 31.0 &B +3 dB Bandwidth Up to 40 dB Gain Reduction 100 MHz Input Resistance Differential n 18 ko Input Capacitance Differential 1 s pF Input Voltage Noise 0 4B Gain Reduction 5 aViy Ha Input Signal Range Recommended p-p Differential 10 200 mV ‘Max Output Signal Level 10 Load, p-p Differential 24 v Output Impedance 5 a Output DC Level 35 v Harmonic Distortion 0 dB Gain Reduction os % 26 dB Gain Reduction Ls % INPUT CLAMP? Tum-On Time ns Tum-Off Time ns Input Signal Attenuation 4B ‘On-State Input Impedance Differential a GAIN OF 4 BUFFER Nominal Gain 12.25 12.75 13.25 4B Gain Variation Trin 10 Trae £0.25 B +3 dB Bandwidth Up to 26 dB Gain Reduction 160 MHz Input Resistance Differential 100 ko Input Capacitance Differential 1 5 pF Input Voltage Noise* 100 MHz ~ 0 dB Gain Reduction 7 aViVAiz Input Common-Mode Range 15 +S v Output Impedance 10 a Output Signal Level Recommended p-p Differential 13 v ‘Max Output Signal Level 200. Load, p-p Differential 48 v Output DC Level 25 v Harmonic Distortion 300 mV Peak Output, 200 £ Load 0.20 * FULL WAVE RECTIFIER Input Signal Level p-p Differential 03 3 v —3 dB Bandwidth 100 mV @1 V Peak Input 100 MHz Max Output Signal Level Ls v Output Impedance* 25 2 DC Offsec* Relative to Ground 10 #20 mV AGC CONTROL SECTION Attack Time 26 dB Gain Step ~ 1000 pF Csaqpre 10 hs 26 dB Gain Step - <S0 pF Csaqpte 120 ns Hold Time 1. dB Gain Change - 1000 pF Csampre 10 ms AGC Charge Current 08 mA AGC Control Range 36 40 B AGC Control Sensitivity Per 20 mV Input 1 aB AGC Control Linearity 26 dB AGC Range +025 | 4B Set Level Input Range For Specified Accuracy o 300 mV Nondestructive Input Range ~03 Vox Vv MODE CONTROL SECTION TTL Compatible Vu 20 v Vie 08 v lin Vin = 2.7 Volts 1 HA In Vin = 0.4 Volts 45 -12.0 | pA Mode Switching Times so 2s POWER SUPPLY REQUIREMENTS Operating Range Voc +45 455 v Operating Range Vee 468 0-52 52 | Vv Quiescent Current Trin 10 Tmax Voc Hold/Acquire/Set Gain Mode 4 60 76 mA Vee Hold/Acquire/Set Gain Mode 18 28 40 mA Voc Clamp Mode 31 R 88 mA Ver ‘Clamp Mode 7 27 39 mA 9-8 MASS STORAGE COMPONENTS

a ‘NOTES ‘Gain calibrated in gain set mode with 0 volts applied to the Gain Set Pin. Clamp operation is specified with a source impedance of 200 (1 in series with 0.1 uF. Over the full 100 MHz bandwidth of the AD890, the worst-case rms signal-to-noise ratio is 40 dB or better with a 40 dB AGC range. “Measured using a4 KA? resistor connected between the Qualifier Threshold Pin and Vpx. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are teed wo calculate outgoing quality levels Specifications subject to change without notice. 5 Amigamcans [Bx [Bat ABSOLUTE MAXIMUM RATINGS* ’ 7 "AGC Acquire 0 Storage Temperature Range Input Clamp 1 Operating Temperature Range! "Bepin PLOC cat: Oa cue Model Package Options* 24-pin cerdip package: 64 =: 7 sSunsces above those listed under “Absolute Maximum Ratings” may cause "AD890Q | 24-PinCerdip | Q24 permanent damage to the device. This is a stress rating only, and functional AD890JP_ (28-Pin PLCC P-28A, ‘operation of the device at these or any other conditions above those indicated ow penton of he devo hee or tion above ad See Section 20 for package outline information. broke maximum rating conditions for extended periods may affect device CONNECTION DIAGRAMS 28-Pin PLCC Package bE Ls | er 5 aOR 24-Pin Cerdip Package Rig: # FB AF) fl 1) fe) Pl une La wo. CT = | fe] “mer ase E [te Sart "a oe = OT Ss \\o/ baasses cums wi fa) Sat sa ae S> MEE: came =O ‘conan [as den Ef eomceraton [=] asses ~E owe fz] = -w« Ge some fa) esr . . eo irae az Gf Tace= | dts | wy Je wate 7 sexs a Patsmate [eh rie 1 ll eijal) Mes w/e Op SL: ana Repo wee i= = REE’ REG i ai xe REE EGE MASS STORAGE COMPONENTS 3-9

Figure 7. X4 Buffer Gain vs. Figure 8. X4 Buffer Voltage Noise Figure 9. Hold-Mode Droop

910 MASS STORAGE COMPONENTS

GENERAL LAYOUT REQUIREMENTS 6 Almost 60 dB of total gain is available at 100 MHz. Care must FARES TT be taken to ensure good RF practice in the PC layout to avoid " . oscillations in the 150 MHz-350 MHz region. A parallel combi- TT CELT nation of 0.1 wF and 0.01 wF ceramic bypass capacitors should e' be used as close to the supply pins as possible. Bo CELA Additionally, a single pole RC filter applied at the input of each } LETT stage, with a cutoff in the region of 100 MHz~-150 MHz, will “ eee lion pian Ara gael le, ep cor SCO CHIL nections to interstage components as short as possible; itis also ” \\ acne ee: momen wr COMIN required by the system be performed between the VGA stage * tnd the fst X4 buffer ampli. A round plane shouldbe COUT used to surround any interstage components wherever possible. mary 188 cory ry If these simple rules are followed, stable operation should be FrequENCr He assured. Figure 10. X4 Buffer Frequency Response (100 2 BIASING THE RF GAIN STAGES in Series with 1 uF Load) The VGA Stage ‘The 30 dB variable gain stage is biased at a potential of one di- OPERATING THE FULL WAVE RECTIFIERS ode drop above analog ground. No additional de bias is re- ‘The full wave rectifiers consist of two nearly identical stages. quired, but ac coupling is necessary. The bias voltage is Full wave rectification is performed in each stage using two maintained during normal operation and during operation of the ‘transistors whose emitters are connected together. The inputs to clamp. In order for the clamp to operate correctly with an emit- _the two full wave rectifiers are biased at one diode drop above ter follower driven input, 50 9-100 1 resistors should be placed analog ground; therefore, ac coupling is recommended. The in series with the input coupling capacitors. These resistors can full wave rectifier outputs ~ “AGC Rectifier” and “Qualifier be used in conjunction with a $.1 pF shunt capacitor to limit Threshold” — are connected directly to these commoned emit- the input bandwidth to 150 MHz. In the case of an open collec- _ters. Thus, the normal output voltage with zero input signal ap- 3 | tor driven input with resistive termination, no additional series plied is close to analog ground. The “AGC Rectifier” pin allows resistors are required. access to the output of the rectifier which drives the AGC ‘The differential outputs have a nominal de value of 1.5 V less sample-and-hold section of the ADS90. The "Qualifier than the postive suppl. Internal 1300 @ resistors provide bias Threshold” pin allows acess ro the ourput of the chreshold current to the output emitter followers which operate with recufier. 2.7 mA nominal current. Output drive can be increased by an ‘The AGC rectifier has an internal 2 kf resistive pull-down con- additional 2.5 mA by paralleling external resistors to either the nected between analog ground and the negative power supply analog ground or the negative power supply. However, caution pin. The threshold line has no built in pull-down, in order to should be exercised in order to avoid causing excess dissipation allow for a peak hold capability during thresholding. If a well for the package. The recommended output level for the VGA is controlled rectifier offset is required, an external 4 k pull- 300 mV p-p differential into 200 11 loads. down resistor at the “Qualifier Threshold” pin is recommended ‘The X4Boffers and will produce a nominal 10 mV offset. The inputs of these stages have no committed de biasing, and an input bias current path must be provided. This path can nor- THe age SAME AND HOLD sng of the ‘mally be supplied via shunt resistors to analog ground which are sampiean Section performs averaging generally part of the interstage filter termination networks. The "put waveform to set the RF’ average output level 19 200 mV inputs can be biased successfully within 1.5 V of analog single ended, or 330 mV peak for a sinusoidal signal. Thus, ground, without a peak hold capacitor at the “AGC Rectifier” pin, accu- rate AGC operation only occurs with sinusoidal input signals. Output drive can be increased in a similar manner to that de- ‘An approximate 2 mA pull-down current is permanently present scribed for the VGA stage. The nominal de ourput level is 2.5 Vat the “AGC Rectifier” pin, and a capacitor may be added here with the internal 500 © load resistors connected to analog to provide a degree of peak hold for AGC operation within non- ground which provides a nominal standing current of 5 mA to sinusoidal fields. A capacitance value of less than 0.03 uF or the output emitter followers. This current can be increased by Jess per 1s of transition spacing is recommended. The addition up to an additional 5 mA by paralleling external resistors to ¢i- of the capacitor alters the symmetry of the attack and decay ther analog ground or the negative power supply. As before, rates of the rectifier, which is otherwise symmetric in operation. precautions to limit excessive overall power dissipation apply In order to ensure that the overall AGC response is the same for when steps are taken to increase the output drive capability. both high-to-low and low-to-high input level steps, it is neces- sary to make the rectifier attack and decay times at least a factor of two less than the AGC response time. MASS STORAGE COMPONENTS 9-11

tional 12.75 dB from each X4 buffer, total nominal gain is current by an additional 12 mA or so. VGA Gain (4B) = (30 - Vear ser X 50) decoupling capacitance such as 3.3 4 F value may be desirable. PEATE permits this mode of operation. Figure 11. Frequency Response of VGA Gain for Different Gaussian-t0-6 dB transitional filter plus a second-order RLC readily achieved. Figure 12 shows the AD890 configured for Brounds should be connected at the power supply common.

Figure 13. Typical AD890/AD891 Connection for a 30 MHz Channel simple resistive dividers. wy. changed. To alter +, the reactive element should be scaled pro- and, hence, improved distortion in stages prior to the equalizer. and t= 12 ns. are shown in Figures 15 and 16, respectively.