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Tel: Fax: REV. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 8-Bit Octal, 4-Quadrant Multiplying, CMOS TrimDAC

FEATURES

50 kHz 4-Quadrant Multiplying Bandwidth Low Zero Output Error Eight Individual Channels 3-Wire Serial Input 500 kHz Update Data Loading Rate ±3 V Output Swing Midscale Preset, Zero Volts Out

APPLICATIONS

Vertical Deflection Amplitude Adjustment Waveform Generation and Modulation GENERAL DESCRIPTION The AD8842 provides eight general purpose digitally controlled voltage adjustment devices. The TrimDAC® capability allows replacement of the mechanical trimmer function in new designs. The AD8842 is ideal for ac or dc gain control of up to 50 kHz bandwidth signals. The four-quadrant multiplying capability is useful for signal inversion and modulation often found in video vertical deflection circuitry. Internally the AD8842 contains eight voltage output digital-to- analog converters, each with separate voltage inputs. A new current conveyor amplifier design performs the four-quadrant multiplying function with a single amplifier at the output of the current steering digital-to-analog converter. This approach of- fers an improved constant input resistance performance versus previous voltage switched DACs used in TrimDAC circuits, eliminating the need for additional input buffer amplifiers. Each DAC has its own DAC register that holds its output state. These DAC registers are updated from an internal serial-to- parallel shift register that is loaded from a standard 3-wire serial input digital interface. Twelve data bits make up the data word clocked into the serial input register. This data word is decoded where the first 4 bits determine the address of the DAC register to be loaded with the last 8 bits of data. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple DAC applications without additional exter- nal decoding logic. TrimDAC is a registered trademark of Analog Devices, Inc. The current conveyor amplifier is a patented circuit belonging to Analog Devices, Inc. The AD8842 consumes only 95 mW from ± 5 V power supplies. For single 5 V supply applications consult the DAC-8841. The AD8842 is pin compatible with the 1 MHz multiplying band- width DAC8840. The AD8842 is available in 24-pin plastic DIP and surface mount SOL-24 packages. Figure 1. Functional Circuit of One 4-Quadrant Figure 2. Actual Current Conveyor Implementation of

8 X 8

8 DAC A8

AD8842–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units STATIC ACCURACY—All Specifications Apply for DACs A, B, C, D, E, F, G, H Resolution N 8 Bits Integral Nonlinearity Error INL ± 0.2 ± 1 LSB Differential Nonlinearity DNL All Devices Monotonic ± 0.4 ± 1 LSB Full-Scale Gain Error GFSE 2 LSB Output Offset VBZE PR = 0, Sets D = 80 H 52 5 m V Output Offset Drift TCVBZ PR = 0, Sets D = 80 H 5 µV/°C VOLTAGE INPUTS—Applies to All Inputs V INx Input Voltage Range 1 IVR ± 3 ± 4V Input Resistance R IN 12 19 kΩ Input Capacitance CIN 9p F DAC OUTPUTS—Applies to All Outputs V OUTx Voltage Range 1 OVR R L = 10 kΩ± 3 ± 4V Output Current I OUT ΔVOUT < 1.5 LSB ± 3m A Capacitive Load CL No Oscillation 500 pF DYNAMIC PERFORMANCE—Applies to All DACs Full Power Gain Bandwidth 1 GBW V INx = ± 3 VP, RL = 2 kΩ , CL = 10 pF 10 50 kHz Slew Rate Measured 10% to 90% Positive SR+ ΔVOUTx = +5.5 V 0.5 1.0 V/µs Negative SR– ΔVOUTx = –5.5 V 1.0 1.8 V/µs Total Harmonic Distortion THD V INx = 4 V p-p, D = FF H, f = 1 kHz, 0.01 % fLPF = 80 kHz, RL = 1 kΩ Spot Noise Voltage e N f = 1kHz, VIN = 0 V 78 nV/√Hz Output Settling Time t S ± 1 LSB Error Band, D = 00 H to FFH 2.9 µs D = FF H to 00H 5.4 µs Channel-to-Channel Crosstalk C T Measured Between Adjacent Channels, f = 100 kHz 72 dB Digital Feedthrough Q V INx = 0 V, D = 0 to 255 10 5 nV-s POWER SUPPLIES Positive Supply Current IDD PR = 0 V 10 14 mA Negative Supply Current I SS PR = 0 V 9 13 mA Power Dissipation 2 PDISS 95 135 mW Power Supply Rejection PSRR PR = 0 V, ΔVDD = ± 5% 0.0001 0.01 %/% Power Supply Range PSR V DD, |VSS| 4.75 5.00 5.25 V DIGITAL INPUTS Logic High VIH 2.4 V Logic Low VIL 0.8 V Input Current I L ± 10 µA Input Capacitance C IL 7p F Input Coding Offset Binary DIGITAL OUTPUT Logic High V OH IOH = –0.4 mA 3.5 V Logic Low VOL IOL = 1.6 mA 0.4 V TIMING SPECIFICATIONS 1 Input Clock Pulse Width tCH, tCL 60 ns Data Setup Time tDS 40 ns Data Hold Time tDH 20 ns CLK to SDO Propagation Delay t PD 80 ns DAC Register Load Pulse Width t LD 70 ns Preset Pulse Width tPR 50 ns Clock Edge to Load Time tCKLD 30 ns Load Edge to Next Clock Edge t LDCK 60 ns NOTES 1Guaranteed by design, not subject to production test. 2Calculated limit = 5 V × (IDD + ISS). Specifications subject to change without notice. REV. –2– (VDD = +5 V, VSS = –5 V, All V INx = +3 V, TA = –40°C to +85°C, unless otherwise noted.) A

0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 3. Timing Diagram accumulate on the human body and test equipment and can discharge without detection. precautions are recommended to avoid performance degradation or loss of functionality.

(Not to Scale) 12 13 AD8842

REV. –5– Table I. Serial Input Decode Table Table II. Input Logic Control Truth Table CLK LD PR Input Shift Register Operation L L H No Operation ↑ L H Shift One Bit in from SDI (Pin 20), Shift One Bit* Out from SDO (Pin 18) X L L All DAC Registers = 80 H X Η H Load Serial Register Data into DAC(X) Register X H X Serial Data Input Register Loading Disabled *Data shifted into the SDI pin appears twelve clocks later at the SDO pin. LSB D0 D1 D2 D3 D4 D5 D6 MSB LSB A0 A1 A2 MSB LAST FIRST A3 A2 A1 A0 ADDRESSDATA MSB LSB DAC UPDATED NO OPERATION DAC A DAC B DAC C DAC D DAC H NO OPERATION NO OPERATION D7 D6 D5 D4 D3 D2 D1 D0 DAC OUTPUT VOLTAGE VOUT = (D/128 –1) x VIN MSB LSB –VIN (1/128–1) x VIN (127/128–1) x VIN (128/128–1) x VIN = 0V; (PRESET VALUE) (129/128–1) x VIN (254/128–1) x VIN (255/128–1) x VIN » VIN

  • ••
  • •• A

135 CROSSTALK – dB

Figure 4. Linearity Error vs. Figure 5. Linearity Error vs. Figure 6. V OUT Half Scale (80H) Figure 7. Input Resistance (V IN) Figure 8. Total Harmonic Distortion Figure 9. VOUT Slew Rate Figure 10. Gain and Phase vs. Figure 11. DAC Crosstalk Figure 12. Voltage Noise Density

IN are summarized in this table. when the DAC register is loaded with 255 (in binary = all ones). tion 2 to describe circuit performance. form adjustment and amplitude control. supply bypass for most frequencies encountered. and can easily drive several AD8842s. data interface setup is shown in Figure 30. Figure 30. Basic Three-Wire Serial Interface package LD strobe which is being used as a chip select.

REV. A –13– ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD8842AN −40°C to +85°C 24-Lead PDIP N-24-1 AD8842ANZ −40°C to +85°C 24-Lead PDIP N-24-1 AD8842AR −40°C to +85°C 24-Lead SOIC_W RW-24 AD8842AR-REEL −40°C to +85°C 24-Lead SOIC_W RW-24 AD8842ARZ −40°C to +85°C 24-Lead SOIC_W RW-24 AD8842ARZ-REEL −40°C to +85°C 24-Lead SOIC_W RW-24 1 Z = RoHS Compliant Part.

REVISION HISTORY

10/11—Rev. 0 to Rev. A 4/94—Revision 0: Initial Version ©1994–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D01904-0-10/11(A)