AD883B

AD526 AD | Alldatasheet

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REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Software Programmable Gain Amplifier AD526

FEATURES

Digitally Programmable Binary Gains from 1 to 16 Two-Chip Cascade Mode Achieves Binary Gain from 1 to 256 Gain Error: 0.01% Max, Gain = 1, 2, 4 (C Grade) 0.02% Max, Gain = 8, 16 (C Grade) 0.5 ppm/ 8C Drift Over Temperature Fast Settling Time

10 V Signal Change:

0.01% in 4.5 ms (Gain = 16) Gain Change: 0.01% in 5.6 ms (Gain = 16) Low Nonlinearity: 60.005% FSR Max (J Grade) Excellent DC Accuracy: Offset Voltage: 0.5 mV Max (C Grade) Offset Voltage Drift: 3 mV/8C (C Grade) TTL-Compatible Digital Inputs PRODUCT DESCRIPTION The AD526 is a single-ended, monolithic software program- mable gain amplifier (SPGA) that provides gains of 1, 2, 4, 8 and 16. It is complete, including amplifier, resistor network and TTL-compatible latched inputs, and requires no external components. Low gain error and low nonlinearity make the AD526 ideal for precision instrumentation applications requiring programmable gain. The small signal bandwidth is 350 kHz at a gain of 16. In addition, the AD526 provides excellent dc precision. The FET- input stage results in a low bias current of 50 pA. A guaranteed maximum input offset voltage of 0.5 mV max (C grade) and low gain error (0.01%, G = 1, 2, 4, C grade) are accomplished using Analog Devices’ laser trimming technology. To provide flexibility to the system designer, the AD526 can be operated in either latched or transparent mode. The force/sense configuration preserves accuracy when the output is connected to remote or low impedance loads. The AD526 is offered in one commercial (0 °C to +70°C) grade, J, and three industrial grades, A, B and C, which are specified from –40°C to +85°C. The S grade is specified from –55 °C to +125°C. The military version is available processed to MIL- STD 883B, Rev C. The J grade is supplied in a 16-lead plastic DIP, and the other grades are offered in a 16-lead hermetic side-brazed ceramic DIP. PIN CONFIGURATION TOP VIEW (Not to Scale) DIG GND A1 AD526 NULL A0 VIN CS NULL CLK ANALOG GND 2 A2 ANALOG GND 1 B –VS +VS VOUT SENSE V OUT FORCE Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 ORDERING GUIDE Temperature Package Package Model Range Descriptions Options AD526JN Commercial 16-Lead Plastic DIP N-16 AD526AD Industrial 16-Lead Cerdip D-16 AD526BD Industrial 16-Lead Cerdip D-16 AD526CD Industrial 16-Lead Cerdip D-16 AD526SD Military 16-Lead Cerdip D-16 AD526SD/883B Military 16-Lead Cerdip D-16 5962-9089401MEA* Military 16-Lead Cerdip D-16 *Refer to official DESC drawing for tested specifications. APPLICATION HIGHLIGHTS 1. Dynamic Range Extension for ADC Systems: A single AD526 in conjunction with a 12-bit ADC can provide 96 dB of dynamic range for ADC systems . 2. Gain Ranging Preamps: The AD526 offers complete digital gain control with precise gains in binary steps from 1 to 16. Additional gains of 32, 64, 128 and 256 are possible by cas- cading two AD526s.

AD526J AD526A AD526B/S AD526C Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units GAIN Gain Range (Digitally Programmable) 1, 2, 4, 8, 16 1, 2, 4, 8, 16 1, 2, 4, 8, 16 1, 2, 4, 8, 16 Gain Error Gain = 1 0.05 0.02 0.01 0.01 % Gain = 2 0.05 0.03 0.02 0.01 % Gain = 4 0.10 0.03 0.02 0.01 % Gain = 8 0.15 0.07 0.04 0.02 % Gain = 16 0.15 0.07 0.04 0.02 % Gain Error Drift Over Temperature Gain Error (T MIN to TMAX) Gain = 1 0.06 0.03 0.02 0.015 % Gain = 2 0.06 0.04 0.03 0.015 % Gain = 4 0.12 0.04 0.03 0.015 % Gain = 8 0.17 0.08 0.05 0.03 % Gain = 16 0.17 0.08 0.05 0.03 % Nonlinearity Gain = 1 0.005 0.005 0.005 0.0035 % FSR Gain = 2 0.001 0.001 0.001 0.001 % FSR Gain = 4 0.001 0.001 0.001 0.001 % FSR Gain = 8 0.001 0.001 0.001 0.001 % FSR Gain = 16 0.001 0.001 0.001 0.001 % FSR Nonlinearity (T MIN to TMAX) Gain = 1 0.01 0.01 0.01 0.007 % FSR Gain = 2 0.001 0.001 0.001 0.001 % FSR Gain = 4 0.001 0.001 0.001 0.001 % FSR Gain = 8 0.001 0.001 0.001 0.001 % FSR Gain = 16 0.001 0.001 0.001 0.001 % FSR VOLTAGE OFFSET, ALL GAINS Input Offset Voltage Drift Over Temperature 5 20 3 10 3 10 3 10 mV/°C Input Offset Voltage TMIN to TMAX 2.0 1.0 0.8 0.8 mV Input Offset Voltage vs. Supply (VS – 10%) 80 80 84 90 dB INPUT BIAS CURRENT Over Input Voltage Range – 10 V 50 150 50 150 50 150 50 150 pA ANALOG INPUT CHARACTERISTICS Voltage Range (Linear Operation) 610 – 12 610 – 12 610 – 12 610 – 12 V Capacitance 5555 p F RATED OUTPUT Voltage 610 – 12 610 – 12 610 – 12 610 – 12 V Current (VOUT = – 10 V) – 10 65 – 10 65 – 10 65 – 10 mA Short-Circuit Current 15 30 15 30 15 30 15 30 mA DC Output Resistance 0.002 0.002 0.002 0.002 W Load Capacitance (For Stable Operation) 700 700 700 700 pF AD526–SPECIFICATIONS(@ VS = 615 V, RL = 2 kV and TA = +258C unless otherwise noted) REV. D–2–

AD526J AD526A AD526B/S AD526C Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units NOISE, ALL GAINS Voltage Noise, RTI

0.1 Hz to 10 Hz 3 3 3 3 mV p-p

Voltage Noise Density, RTI f = 10 Hz 70 70 70 70 nV ÖHz f = 100 Hz 60 60 60 60 nV ÖHz f = 1 kHz 30 30 30 30 nV ÖHz f = 10 kHz 25 25 25 35 nV ÖHz DYNAMIC RESPONSE –3 dB Bandwidth (Small Signal) G = 1 4.0 4.0 4.0 4.0 MHz G = 2 2.0 2.0 2.0 2.0 MHz G = 4 1.5 1.5 1.5 1.5 MHz G = 8 0.65 0.65 0.65 0.65 MHz G = 16 0.35 0.35 0.35 0.35 MHz Signal Settling Time to 0.01% (DV OUT = – 10 V) G = 1 2.1 4 2.1 4 2.1 4 2.1 4 ms G = 2 2.5 5 2.5 5 2.5 5 2.5 5 ms G = 4 2.7 5 2.7 5 2.7 5 2.7 5 ms G = 8 3.6 7 3.6 7 3.6 7 3.6 7 ms G = 16 4.1 7 4.1 7 4.1 7 4.1 7 ms Full Power Bandwidth G = 1, 2, 4 0.10 0.10 0.10 0.10 MHz G = 8, 16 0.35 0.35 0.35 0.35 MHz Slew Rate G = 1, 2, 4 4 6 4 6 4 6 4 6V / ms G = 8, 16 18 24 18 24 18 24 18 24 V/ ms DIGITAL INPUTS (TMIN to TMAX) Input Current (V H = 5 V) 60 100 140 60 100 140 60 100 140 60 100 140 mA Logic “1” 2 6 2 6 2 6 2 6 V Logic “0” 0 0.8 0 0.8 0 0.8 0 0.8 V TIMING1 (VL = 0.2 V, VH = 3.7 V) A0, A1, A2 TC 50 50 50 50 ns TS 30 30 30 30 ns TH 30 30 30 30 ns B TC 50 50 50 50 ns TS 40 40 40 40 ns TH 10 10 10 30 ns TEMPERATURE RANGE Specified Performance 0 +70 –40 +85 –40/–55 +85/+125 –40 +85 °C Storage –65 +125 –65 +150 –65 +150 –65 +150 °C POWER SUPPLY Positive Supply Current 10 14 10 14 10 14 10 14 mA Negative Supply Current 10 13 10 13 10 13 10 13 mA PACKAGE OPTIONS Plastic (N-16) AD526JN Ceramic DIP (D-16) AD526AD AD526BD AD526SD AD526CD AD526SD/883B NOTES 1Refer to Figure 25 for definitions. FSR = Full Scale Range = 20 V. RTI = Referred to Input. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. All min and max specifications are guaranteed, although only thos e shown in boldface are tested on all production units. –3–REV. D

Figure 28. Gain Change Settling Figure 29. Gain Change Settling

7000 SERIES

Figure 30. Wideband Noise Test Circuit Figure 31. Settling Time Test Circuit

give the timing requirements for loading new gain codes. GAIN CODE, CS, AND CLK IS 1.4V. Figure 35. AD526 Timing

1 X X 1 0 16 Transparent

1 X X 1 1 16 Latched

causing spikes to occur at the signal output. code in an external bank of latches (Figure 36). serial-in/parallel-out latch, such as the 54LS594. Figure 36. Using an External Latch to Minimize Digital

accuracy, improve system resolution or increase dynamic range. put rates, alternative conversion techniques must be employed. rate and dynamic range of a system. and full scale for the maximum usable resolution. anger and the 12-bit output of the AD7572. The A/D converter in Figure 42 has a dynamic range of 96 dB. monolithic converter divided by the maximum gain of the PGA. Figure 42. Floating-Point A/D Converter

mented only during periods of converter inactivity. Figure 43. High Accuracy A/D Converter

REV. D–14– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Plastic PIN 1 SEATING PLANE 0.100 (2.54) 0.87 (22.1) MAX 0.31 (7.87) 0.25 (6.25) 0.125 (3.18) MIN 0.18 (4.57) 0.035 (0.89) 0.018 (0.46) 0.033 (0.84) 0.3 (7.62) 0.18 (4.57) MAX 0.011 (0.28) 16-Lead Sided-Brazed Ceramic Package (D-16) 1 8 PIN 1 0.265 (6.73) 0.290 60.010 (7.37 60.254) 0.430 (10.922) 0.040R 0.180 60.03 (4.57 60.762) 0.800 60.010 (20.32 60.254) 0.100 (2.54) BSC SEATING PLANE 0.095 (2.41) 0.310 60.01 (7.874 60.254) 0.047 60.007 (1.19 60.18) 0.700 (17.78) BSC +0.003 –0.0020.017 +0.076 –0.05(0.43 ) 0.035 60.01 (0.889 60.254) 0.125 (3.175) MIN 0.300 (7.62) REF 0.085 (2.159) 0.010 60.002 (0.254 60.05) PRINTED IN U.S.A. C1103d–0–8/99