AD8802ARU

AD8802ARZ AD | Alldatasheet

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R VDD DAC DAC REG #12 R DAC O10 O11 O12 VREFH GND RS (AD8802 ONLY) VREFL (AD8804 ONLY) REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 12 Channel, 8-Bit TrimDACs with Power Shutdown AD8802/AD8804 © Analog Devices, Inc., 1995 Tel: 617/329-4700 Fax: 617/326-8703 GENERAL DESCRIPTION The 12-channel AD8802/AD8804 provides independent digitally- controllable voltage outputs in a compact 20-lead package. This potentiometer divider TrimDAC® allows replacement of the mechanical trimmer function in new designs. The AD8802/ AD8804 is ideal for dc voltage adjustment applications. Easily programmed by serial interfaced microcontroller ports, the AD8802 with its midscale preset is ideal for potentiometer replacement where adjustments start at a nominal value. Appli- cations such as gain control of video amplifiers, voltage con- trolled frequencies and bandwidths in video equipment, geometric correction and automatic adjustment in CRT com- puter graphic displays are a few of the many applications ideally suited for these parts. The AD8804 provides independent con- trol of both the top and bottom end of the potentiometer divider allowing a separate zero-scale voltage setting determined by the V REFL pin. This is helpful for maximizing the resolution of devices with a limited allowable voltage control range. Internally the AD8802/AD8804 contains 12 voltage-output digital-to-analog converters, sharing a common reference- voltage input. TrimDAC is a registered trademark of Analog Devices, Inc.

FEATURES

Replaces 12 Potentiometers Individually Programmable Outputs 3-Wire SPI Compatible Serial Input Power Shutdown <55 mWatts Including I DD & IREF Midscale Preset, AD8802 Separate V REFL Range Setting, AD8804 +3 V to +5 V Single Supply Operation

APPLICATIONS

Video and Audio Equipment Gain and Offset Adjustment Portable and Battery Operated Equipment Each DAC has its own DAC latch that holds its output state. These DAC latches are updated from an internal serial-to- parallel shift register that is loaded from a standard 3-wire serial input digital interface. The serial-data-input word is decoded where the first 4 bits determine the address of the DAC latches to be loaded with the last 8 bits of data. The AD8802/ AD8804 consumes only 10 µA from 5 V power supplies. In ad- dition, in shutdown mode reference input current consumption is also reduced to 10 µA while saving the DAC latch settings for use after return to normal operation. The AD8802/AD8804 is available in the 20-pin plastic DIP, the SOIC-20 surface mount package, and the 1 mm thin TSSOP-20 package.

Parameter Symbol Conditions Min Typ 1 Max Units STATIC ACCURACY Specifications apply to all DACs Resolution N 8 Bits Differential Nonlinearity Error DNL Guaranteed Monotonic –1 ± 1/4 +1 LSB Integral Nonlinearity Error INL –1.5 ± 1/2 +1.5 LSB Full-Scale Error G FSE –1 1/2 +1 LSB Zero Code Error V ZSE –1 1/4 +1 LSB DAC Output Resistance R OUT 35 8 k Ω Output Resistance Match Δ R/RO 1.5 % REFERENCE INPUT Voltage Range2 VREFH 0V DD V VREFL Pin Available on AD8804 Only 0 V DD V REFH Input Resistance R REFH Digital Inputs = 55 H, VREFH = VDD 1.2 k Ω REFL Input Resistance 3 RREFL Digital Inputs = 55 H, VREFL = VDD 1.2 k Ω Reference Input Capacitance 3 CREF0 Digital Inputs all Zeros 32 pF CREF1 Digital Inputs all Ones 32 pF DIGITAL INPUTS Logic High V IH VDD = +5 V 2.4 V Logic Low V IL VDD = +5 V 0.8 V Logic High V IH VDD = +3 V 2.1 V Logic Low V IL VDD = +3 V 0.6 V Input Current I IL VIN = 0 V or + 5 V ± 1 µA Input Capacitance 3 CIL 5p F POWER SUPPLIES 4 Power Supply Range V DD Range 2.7 5.5 V Supply Current (CMOS) I DD VIH = VDD or VIL = 0 V 0.01 10 µA Supply Current (TTL) I DD VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V 1 4 mA Shutdown Current I REFH SHDN = 0 0.2 10 µA Power Dissipation P DISS VIH = VDD or VIL = 0 V, VDD = +5.5 V 55 µW Power Supply Sensitivity PSRR V DD = +5 V ± 10% 0.001 0.002 %/% DYNAMIC PERFORMANCE 3 VOUT Settling Time t S ± 1/2 LSB Error Band 0.6 µs Crosstalk CT Between Adjacent Outputs 5 50 dB SWITCHING CHARACTERISTICS 3, 6 Input Clock Pulse Width t CH, tCL Clock Level High or Low 15 ns Data Setup Time t DS 5n s Data Hold Time t DH 5n s CS Setup Time t CSS 10 ns CS High Pulse Width t CSW 10 ns Reset Pulse Width t RS 90 ns CLK Rise to CS Rise Hold Time t CSH 20 ns CS Rise to Clock Rise Setup t CS1 10 ns NOTES 1Typicals represent average readings at +25 °C. 2VREFH can be any value between GND and V DD, for the AD8804 V REFL can be any value between GND and V DD. 3Guaranteed by design and not subject to production test. 4Digital Input voltages V IN = 0 V or V DD for CMOS condition. DAC outputs unloaded. P DISS is calculated from (I DD × VDD). 5Measured at a VOUT pin where an adjacent V OUT pin is making a full-scale voltage change (f = 100 kHz). 6See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. AD8802/AD8804–SPECIFICATIONS REV. 0–2– (VDD = +3 V 6 10% or +5 V 6 10%, VREFH = +VDD, VREFL = 0 V, –40 8C ≤TA ≤ +858C unless otherwise noted)

REV. 0 –3– ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted) Maximum Junction Temperature (T Thermal Resistance θJA, AD8802 PIN DESCRIPTIONS Pin Name Description 1V REF Common DAC Reference Input

2 O1 DAC Output #1, addr = 0000 2

3 O2 DAC Output #2, addr = 0001 2

4 O3 DAC Output #3, addr = 0010 2

5 O4 DAC Output #4, addr = 0011 2

6 O5 DAC Output #5, addr = 0100 2

7 O6 DAC Output #6, addr = 0101 2

8 SHDN Reference input current goes to zero. DAC latch settings maintained 9 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded into the target DAC register

10 GND Ground

11 CLK Serial Clock Input, Positive Edge Triggered

12 SDI Serial Data Input

13 O7 DAC Output #7, addr = 0110

14 O8 DAC Output #8, addr = 0111 2

15 O9 DAC Output #9, addr = 1000 2

16 O10 DAC Output #10, addr = 1001 2

17 O11 DAC Output #11, addr = 1010 2

18 O12 DAC Output #12, addr = 1011 2

19 RS Asynchronous Preset to Midscale Output

Setting. Loads all DAC Registers with 80 H

20 V DD Positive Power Supply, Specified for Operation

V REFL CLK SDI VREFH SHDN CS GND TOP VIEW (Not to Scale) AD8804 TOP VIEW (Not to Scale) VREFH O11 O12 RS V DD AD8802 O10O4 SHDN CS GND CLK SDI AD8804 PIN DESCRIPTIONS Pin Name Description 1V REFH Common High-Side DAC Reference Input

8 SHDN Reference input current goes to zero DAC latch

9 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded input the target DAC register REFL Common Low-Side DAC Reference Input

12 CLK Serial Clock Input, Positive Edge Triggered

13 SDI Serial Data Input

14 O7 DAC Output #7, addr = 0110

15 O8 DAC Output #8, addr = 0111 2

16 O9 DAC Output #9, addr = 1000 2

17 O10 DAC Output #10, addr = 1001 2

18 O11 DAC Output #11, addr = 1010 2

19 O12 DAC Output #12, addr = 1011 2

20 V DD Positive power supply, specified for operation at

Temperature Package Package Model FTN Range Description Option AD8802AN RS –40°C/+85°C PDIP-20 N-20 AD8802AR RS –40°C/+85°C SOL-20 R-20 AD8802ARU RS –40°C/+85°C TSSOP-20 RU-20 AD8804AN REFL –40 °C/+85°C PDIP-20 N-20 AD8804AR REFL –40 °C/+85°C SOL-20 R-20 AD8804ARU REFL –40 °C/+85°C TSSOP-20 RU-20 WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

where Dx is the data contained in the 8-bit DACx register. Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit available to establish a user designed full-scale output voltage. design uses fully bidirectional switches as shown in Figure 16. OUT from DAC-to-DAC typically matches within ± 1%. down all twelve outputs are open-circuited. Figure 17. Block Diagram into the serial register on each positive clock edge, see Table II.

0 P Shifts Serial Register One bit loading the next bit

P = Positive Edge, X = Don’t Care. DAC registers, see Figure 18 detail.

; using the 8051’s serial port in MODE 0 (Shift Register Mode). Figure 25. An AD8802/AD8804-8051 µC Interface Using communication with the AD8802/AD8804.

; using the 8051’s parallel port #1. SHDN and RS (AD8802 only) inputs. Figure 26. An AD8802/AD8804-to-MC68HC11 Interface

REV. 0–12– * AD8802/AD8804 to M68HC11 Interface Assembly Program * M68HC11 Register definitions PORTC EQU $1003 Port C control register DDRC EQU $1007 Port C data direction PORTD EQU $1008 Port D data register * “0,0,/CS,CLK;SDI,0,0,0” DDRD EQU $1009 Port D data direction SPCR EQU $1028 SPI control register * “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0” SPSR EQU $1029 SPI status register * “SPIF,WCOL,0,MODF;0,0,0,0” SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * SDI RAM variables: SDI1 is encoded from 0H to 7H * SDI2 is encoded from 00H to FFH * AD8802/AD8804 requires two 8-bit loads; upper 4 bits * of SDI1 are ignored. AD8802/AD8804 address bits in last * four LSBs of SDI1. SDI1 EQU $00 SDI packed byte 1 “0,0,0,0;A3,A2,A1,A0” SDI2 EQU $01 SDI packed byte 2 “DB7–DB4;DB3–DB0” * Main Program ORG $C000 Start of user’s RAM in EVB INIT LDS #$CFFF Top of C page RAM * Initialize Port C Outputs * /RS-Hi, /SHDN-Hi STAA PORTC Initialize Port C Outputs STAA DDRC /RS and /SHDN are now enabled as outputs * Initialize Port D Outputs * /CS-Hi,/CLK-Lo,SDI-Lo STAA PORTD Initialize Port D Outputs STAA DDRD /CS,CLK, and SDI are now enabled as outputs * Initialize SPI Interface LDAA #$53 STAA SPCR SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32 * Call update subroutine BSR UPDATE Xfer 2 8-bit words to AD8402 JMP $E000 Restart BUFFALO * Subroutine UPDATE UPDATE PSHX Save registers X, Y, and A PSHY PSHA * Enter Contents of SDI1 Data Register

REV. 0 –13– LDAA $0000 Hi-byte data loaded from memory STAA SDI1 SDI1 = data in location 0000H * Enter Contents of SDI2 Data Register LDAA $0001 Low-byte data loaded from memory STAA SDI2 SDI2 = Data in location 0001H LDX #SDI1 Stack pointer at 1st byte to send via SDI LDY #$1000 Stack pointer at on-chip registers * Reset AD8802 to one-half scale (AD8804 does not have a Reset input) BCLR PORTC,Y $02 Assert /RS BSET PORTC,Y $02 De-Assert /RS * Get AD8802/04 ready for data input BCLR PORTD,Y $02 Assert /CS TFRLP LDAA 0,X Get a byte to transfer for SPI STAA SPDR Write SDI data reg to start xfer WAIT LDAA SPSR Loop to wait for SPIF BPL WAIT SPIF is the MSB of SPSR INX Increment counter to next byte for xfer CPX #SDI2+1 Are we done yet ? BNE TFRLP If not, xfer the second byte * Update AD8802 output BSET PORTD,Y $20 Latch register & update AD8802 PULA When done, restore registers X, Y & A PULY PULX RTS Return to Main Program Listing 3. AD8802/AD8804 to MC68HC11 Interface Program Source Code An Intelligent Temperature Control System—Interfacing the 8051 mC with the AD8802/AD8804 and TMP14 Connecting the 80CL51 µC, or any modern microcontroller, with the TMP14 and AD8802/AD8804 yields a powerful tem- perature control tool, as shown in Figure 27. For example, the 80CL51 µC controls the TrimDACs allowing the user to auto- matically set the temperature setpoints voltages of the TMP14 via computer or touch pad, while the TMP14 senses the tem- perature and outputs four open-collector trip-points. Feeding these trip-point outputs back to the 80CL51 µC allow it to sense whether or not a setpoint has been exceeded. Additional 80CL51 µC port pins or TMP14 trip-point outputs may then be used to change fan speed (i.e., high, medium, low, off), or increase/decrease the power level to a heater. (Please refer to the TMP14 data sheet for more applications information.) The CS (Chip Select) on the AD8802/AD8804 makes applica- tions that call for large temperature sensor arrays possible. In addition, the 12 channels of the AD8802/AD8804 allow inde- pendent setpoint control for all four trip-point outputs on up to three TMP14 temperature sensors. For example, assume that the 80CL51 µC has eight free port pins available after all user interface lines, interrupts, and the serial port lines have been assigned. The eight port pins may be used as chip selects, in which case an array of eight AD8802/AD8804s controlling twenty-four TMP14 sensors is possible. The AD8802/AD8804 and TMP14 are also ideal choices for low power applications. These devices have power shutdown modes and operate on a single 5 Volt supply. When their shut- down modes are activated current consumption is reduced to less than 35 µA. However, at high operating frequencies (12 MHz) the 80CL51 consumes far more energy (18 mA typ) than the AD8802/AD8804 and TMP14 combined. Therefore, to achieve a low power design the 80CL51 should operate at its lowest possible frequency or be placed in its power-down mode at the end of each instruction sequence. To use the power-down mode of the 80CL51 µC set PCON.1 as the last instruction executed prior to going into the power- down mode. If INT2 and INT9 are enabled, the 80CL51 µC can be awakened from power-down mode with external inter- rupts. As shown in Figure 28, the TLC555 outputs a pulse every few seconds providing the interrupt to restart the 80CL51 µC which then samples the user input pins, the outputs of the

3 TO 2nd AD8802/4

2.5 VREF

Figure 27. Temperature Sensor Array with Programmable Setpoints The gain of the SSM2018T is controlled by the voltage at Pin 11. would be no need for the TLC555, which consumes 1 mW typ.

12 Channel Programmable Voltage Controlled Amplifier

0 TO 40dB GAINVOUT

Figure 28. 12-Channel Programmable Voltage Controlled Amplifier

Figure 29. A Digitally Controlled LM1204—150 MHz RGB Amplifier System decoupled from the power rails and shifted closer together. nate penalty of decreased gain range. The LM1204 is an industry standard video amplifier system. added feature of digital control.

1.0 V, then all 256 voltage levels of the AD8804 will fall within

are low impedance (2 k Ω typical).

Figure 30. A Low Noise 90 MHz PGA