AD880 AD | Alldatasheet
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FEATURES AD880 FUNCTIONAL BLOCK DIAGRAM
4 Matched Transimpedance Amplifiers
40 MHz Bandwidth Mew
Selectable 40 kQ/120 kQ. Transimpedance mo fel = cus Continuous or Sampled Servo Capability [l cell H+) > ry Outputs: ——| ween ‘Quad Sum we oT Track & Tes | 1. Normalized Track Hae) => ce Focus Normalized Focus ow Tf 10 Miz Normalization Dividers om oes] L. OL roo 10 ns Write Recovery with Sampling [] i a|= | aoe | PRODUCT DESCRIPTION o el L qj i ‘The AD880 is a monolithic integrated circuit intended for al JH applications in the servo/read systems of an optical disk drive product “ aasm ses ‘The AD880 consists of four matched transimpedance amplifiers = (A, B, C, D) with selectable 40 k® or 120 kA transimpedance. _ F . . i 3 | ‘The basic transimpedance stage consists of a 10 KO transimped- -—‘1” addition, the, ae three offset trimmed summing. ance front end that drives @ programmable x1 or x3 buffer. amplifiers idwidth. One amplifier provides the Each stage has been configured to minimize noise and noise THis output can be low pass filtered prior to peaking. To further enhance overall signal to noise perfe ‘normalization dividers. Two other summing amplifi- an external capacitor may be added bet -- and focus ourputs. amplifier and the programmable Lane a ‘A+B+C+D) der low-pass filter - Sw HA+D) ~ (B+O) or (A~B) ‘The AD880 is stable over the full rafige of inpyt capi © Focus 2 (A+©) ~ (B+D) or (CD) tances. To ensure stability and maximize sab! both transimpedance modes, the internal cor itor rf rs are programmed through a CMOS com- in the programmable buffer is appropriately modified for e ul trof line. mode. 1 finally, a pair of two quadrant dividers are provided. These ; . ‘ the normalized focus and track signals with an accuracy Fast read after write recovery is implemented through the trans- _ Benevare woes impedance sample function, Use of the sample function allows OF 10%, and have bandwidths in excess of 10 MHz. for a read-after-write recovery in approximately 10 ns. The ‘The AD880 is available in a 20-pin SOIC package and is speci- “sample capacitor” also serves the dual purpose of providing the fied to operate over the 0 to +70°C commercial temperature low-pass filter. range. This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. MASS STORAGE COMPONENTS 3-3
SPECIFICATIONS a + ave aa +120 ce, mies cere sted D880) Parameter Conditions Min Typ Max | Units TRANSIMPEDANCE AMPLIFIER Transimpedance | 10 Ka ‘Transimpedance Matching | Channel to Channel +1 % Channel to Channel Crosstalk @ 30 MHz Input Signal ~40 | 4B Open-Loop Gain AVo 20 vw Open-Loop Bandwidth 40 MHz Input Capacitance 2 pF Input Offset Current TBD nA Input Offset Voltage TBD mV Input Current Noise 1 PAV Hz Input Voltage Noise LS nVi/Hz Feedback Resistor Noise 13 aVi/Hz ‘Output Impedance @ Fitter Capacitor Pin (Active) 1 ka Output Impedance @ Fiker Capacitor Pin (Sampled) 250 Mo Max Output Voltage Swing +07 v ‘Max Output Current . TBD mA Veur Range con B45 455 ] V Veer Input Current % Le 5 5 mA PROGRAMMABLE BUFFER a HARE ORE Gain | Gai fe ‘! ame 10 4B Gain Matching gt Gai roel TBD 4B 3 dB Bandwidth ~~ Lr F trol = * 4 40 MHz Gain Pe e. Gain . \\ \\ i 0 4B Gain Matching Le to Channel TBD 4B 3 dB Bandwidth weg tfol = 1 60 MHz Input Bias Current 4 |= a, ~~ LN 0.1 pA Input Offset Voltage 8 : i aa TBD uv Input Current Noise 2 1 pAN/Fz Input Voltage Noise 13 aVi/Hz Max Output Voltage Swing Relative to Var 41 v SUMMING AMPLIFIER. Gain 12 4B Gain Matching Input to Input TBD % 3 dB Bandwidth 40 MHz Output DC Voltage Relative to Vane 0 Vv ‘Output Voltage Offset TBD v ‘Output Impedance TBD a ‘Max Output Voltage Relative to Vine 225 v ‘Max Output Current 20 mA NORMALIZATION DIVIDERS Division Error OS=YsX=15 +10 | % 3 dB Bandwidth 10 MHz ‘Output Voltage Range | Relative to Var 2 v ‘Ourput Current Division Ratio = 1 200 HA QWAD SUM FILTER Resistance Quad Sum to Quad Sum Filter ko MODE CONTROL SECTION (CMOS Compatible) Vie 4.0 Vee v Vin | 0 1 v Iu O1 pA Tn O1 pA ‘Mode Switching Times Gain Control 10 ns Output Mode 10 ns Sample Mode 10 as This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing. 9-4 MASS STORAGE COMPONENTS
AD880) Parameter Conditions Min Typ Max Units: POWER SUPPLY REQUIREMENTS Supply Voltage Voc ws 2 132 Vv Supply Voltage Vee 0 Vv Quiescent Current Ioc Trin €© Trax 50 oO 70 mA ABSOLUTE MAXIMUM RATINGS! Supply Voltage Voc 145 v Veer Input Voltage -0.8 70 v ‘Storage Temperature Range 65 10 °C Operating Temperature Range” 0 70 “Cc Lead Temperature Range Soldering 60 Sec +300 | °C NOTES ‘Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device, This is a stress rating only, and functional opera~ ‘tion of the device at these or any other condition above those indicated in the operational section of this specification is not implied. Exposure to absolute rating condos fer eended peed yet sevice ey. ‘Sn de bly 50 pete: = 465m ‘Specifications subject to change without notice. Sample | Gain [Output Me Sample] Gain | Output Logic Assignments Control | Control | Co fro By, fe Control | Control | Control Transimpedance Amplifiers Active 1 rack Outpyg =GA+D) - (B+C) Transimpedance Ampifers Sampleapyp Hood : IN lx |x fo Select 120 k2 ae») bax A 4 n*(A+C) ~ (B+D) | Select 40 k Transimpedance B kon ‘ck Output = (A~B) f Sa gt and x x 1 i 3 | = pcugsalaput = (C-D) oP 2 Do Nac ca, Table I. Logic Assignments PIN ASSIGNMENTS Ft TOR vse EH lacuararet Cae] [L_ ar Sst pars REFERENCE VOLTAGE Fl nt Fx] uso sour ren LEI anaes crow | PTI |b sv eowensuenty : ae Y : use su | r Ly canon at ser - || i somaneven, focus | Ly comrmos une ro anes a Sera AMES womuauze0 rac Fo 1g * Lf norman rus mer som This information applies to a product under development. Its characteristics and specifications are subject to change without notice Analog Devices assumes no obligation regarding future menufectre unless otherwise agreed tn wring, MASS STORAGE COMPONENTS $-5
‘The transimpedance stage is configured as a fixed 10 k@ line (Pin 14). 2 buffer ensures an excellent droop-rate in the sample mode. " 120 k@ overall transimpedance. Figure 1. ‘The output of both the Focus and Track summing amplifiers To optimize the signal to noise performance the input amplifier trol” line (Pin 12). stage is shown in Figure 2. ‘Quad Sum signal to the normalization dividers.
9 General Layout Requirements
1010 Care must be taken to ensure good R,- practice in the PC layout
Notice. Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.