AD871 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
+2.5V REFERENCE OUTPUT BUFFERS VINA VINB CLOCK REF IN REF OUT AV DD AV SSAGND DV DD DGND *DRV DD *DRGND REF OUT *OUTPUT ENABLE OTR *MSB MSB–BIT 12 (LSB) *ONLY AVAILABLE ON 44 -TERMINAL SURFACE MOUNT PACKAGE AD871 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Complete 12-Bit 5 MSPS Monolithic A/D Converter AD871
FEATURES
Monolithic 12-Bit 5 MSPS A/D Converter Low Noise: 0.17 LSB RMS Referred to Input No Missing Codes Guaranteed Differential Nonlinearity Error: 0.5 LSB Signal-to-Noise and Distortion Ratio: 68 dB Spurious-Free Dynamic Range: 73 dB Power Dissipation: 1.03 W Complete: On-Chip Track-and-Hold Amplifier and Voltage Reference Pin Compatible with the AD872 Twos Complement Binary Output Data Out of Range Indicator 28-Lead Side Brazed Ceramic DIP or 44-Terminal Surface Mount Package PRODUCT DESCRIPTION The AD871 is a monolithic 12-bit, 5 MSPS analog-to-digital converter with an on-chip, high performance track-and-hold amplifier and voltage reference. The AD871 uses a multistage differential pipelined architecture with error correction logic to provide 12-bit accuracy at 5 MSPS data rates and guarantees no missing codes over the full operating temperature range. The AD871 is a redesigned variation of the AD872 12-bit, 10 MSPS ADC, optimized for lower noise in applications requiring sam- pling rates of 5 MSPS or less. The AD871 is pin compatible with the AD872, allowing the parts to be used interchangeably as system requirements change. The low-noise input track-and-hold (T/H) of the AD871 is ide- ally suited for high-end imaging applications. In addition, the T/H’s high input impedance and fast settling characteristics allow the AD871 to easily interface with multiplexed systems that switch multiple signals through a single A/D converter. The dynamic performance of the input T/H also renders the AD871 suitable for sampling single channel inputs at frequencies up to and beyond the Nyquist rate. The AD871 provides both refer- ence output and reference input pins, allowing the onboard ref- erence to serve as a system reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. A single clock input is used to control all internal conversion cycles. The digital output data is presented in twos complement binary output format. An out-of- range signal indicates an overflow condition, and can be used with the most significant bit to determine low or high overflow. The AD871 is fabricated on Analog Devices’ ABCMOS-1 pro- cess, which uses high speed bipolar and CMOS transistors on a single chip. High speed, precision analog circuits are now com- bined with high density logic circuits. The AD871 is packaged in a 28-lead ceramic DIP and a 44-terminal leadless ceramic surface mount package and is specified for operation from 0 °C to +70°C and –55°C to +125°C. PRODUCT HIGHLIGHTS The AD871 offers a complete single-chip sampling 12-bit,
5 MSPS analog-to-digital conversion function in a 28-lead DIP
or 44-terminal leadless ceramic surface mount package (LCC). Low Noise— The AD871 features 0.17 LSB referred-to-input noise, producing essentially a “1 code wide” histogram for a code-centered dc input. Low Power— The AD871 at 1.03 W consumes a fraction of the power of presently available hybrids. On-Chip Track-and-Hold (T/H)— The low noise, high imped- ance T/H input eliminates the need for external buffers and can be configured for single ended or differential inputs. Ease of Use— The AD871 is complete with T/H and voltage ref- erence and is pin-compatible with the AD872 (12-bit, 10 MSPS monolithic ADC). Out of Range (OTR)— The OTR output bit indicates when the input signal is beyond the AD871’s input range. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997
REV. A–2– DC SPECIFICATIONS Parameter J Grade 1 S Gradel Units RESOLUTION 12 12 Bits min MAX CONVERSION RATE 5 5 MHz min INPUT REFERRED NOISE 0.17 0.17 LSB rms typ ACCURACY Integral Nonlinearity (INL) ± 1.5 ± 1.5 LSB typ Differential Nonlinearity (DNL) ± 0.5 ± 0.5 LSB typ No Missing Codes 12 12 Bits Guaranteed Zero Error (@ +25°C) 2 ± 0.75 ± 0.75 % FSR max Gain Error (@ +25°C)2 ± 1.25 ± 1.25 % FSR max TEMPERATURE DRIFT3 Zero Error ± 0.15 ± 0.3 % FSR max Gain Error3, 4 ± 0.80 ± 1.75 % FSR max Gain Error3, 5 ± 0.25 ± 0.50 % FSR max POWER SUPPLY REJECTION 6 AVDD, DVDD (+5 V ± 0.25 V) ± 0.125 ± 0.125 % FSR max AVSS (–5 V ± 0.25 V) ± 0.125 ± 0.125 % FSR max ANALOG INPUT Input Range ± 1 ± 1 Volts max Input Resistance 50 50 k Ω typ Input Capacitance 10 10 pF typ INTERNAL VOLTAGE REFERENCE Output Voltage 2.5 2.5 Volts typ Output Voltage Tolerance ± 20 ± 40 mV max Output Current (Available for External Loads) 2.0 2.0 mA typ (External load should not change during conversion.) REFERENCE INPUT RESISTANCE 5 5 k Ω typ POWER SUPPLIES Supply Voltages AVDD +5 +5 V ( ± 5% AVDD Operating) AVSS –5 –5 V ( ± 5% AVSS Operating) DVDD +5 +5 V ( ± 5% DVDD Operating) DRVDD 7 +5 +5 V ( ± 5% DRVDD Operating) Supply Current IAVDD 87 88 mA max (82 mA typ) IAVSS 147 150 mA max (115 mA typ) IDVDD 20 21 mA max (7 mA typ) IDRVDD 7 2 2 mA max POWER CONSUMPTION 1.03 1.03 W typ 1.25 1.3 W max NOTES 1Temperature ranges are as follows: J Grade: 0 °C to +70°C, S Grade: –55 °C to +125°C. 2Adjustable to zero with external potentiometers (see Zero and Gain Error Calibration section). 3+25°C to TMIN and +25°C to TMAX. 4Includes internal voltage reference error. 5Excludes internal reference drift. 6Change in Gain Error as a function of the dc supply voltage (V NOMINAL to VMIN, VNOMINAL to VMAX). 7LCC package only. Specifications subject to change without notice. (TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V, f SAMPLE = 5 MHz, unless otherwise noted) AD871–SPECIFICATIONS
REV. A –3– AC SPECIFICATIONS (TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, AVSS = –5 V, f SAMPLE = 5 MSPS, unless otherwise noted)1 Parameter Symbol J, S Grades Units LOGIC INPUTS High Level Input Voltage V IH +2.0 V min Low Level Input Voltage V IL +0.8 V max High Level Input Current (V IN = DVDD)I IH ± 115 µA max Low Level Input Current (V IN = 0 V) I IL ± 115 µA max Input Capacitance C IN 5 pF typ LOGIC OUTPUTS High Level Output Voltage (I OH = 0.5 mA) V OH +2.4 V min Low Level Output Voltage (I OL = 1.6 mA) V OL +0.4 V max Output Capacitance C OUT 5 pF typ Leakage (Three-State, LCC Only) IZ ± 10 µA max Specifications subject to change without notice. J Grade S Grade Units SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) fINPUT = 750 kHz 68 68 dB typ fINPUT = 1 MHz 66 66 dB typ 63 62 dB min fINPUT = 2.49 MHz 60 60 dB typ TOTAL HARMONIC DISTORTION (THD) fINPUT = 750 kHz –72 –72 dB typ fINPUT = 1 MHz –69 –69 dB typ –64 –63 dB max fINPUT = 2.49 MHz –62 –62 dB typ SPURIOUS FREE DYNAMIC RANGE (SFDR) fINPUT = 750 kHz 73 73 dB typ fINPUT = 1 MHz 70 70 dB typ fINPUT = 2.49 MHz 62 62 dB typ INTERMODULATION DISTORTION (IMD) 2 Second Order Products –80 –80 dB typ Third Order Products –73 –73 dB typ FULL POWER BANDWIDTH 15 15 MHz typ SMALL SIGNAL BANDWIDTH 15 15 MHz typ APERTURE DELAY 6 6 ns typ APERTURE JITTER 16 16 ps rms typ ACQUISITION TO FULL-SCALE STEP 80 80 ns typ OVERVOLTAGE RECOVERY TIME 80 80 ns typ NOTES 1fIN amplitude = –0.5 dB full scale unless otherwise indicated. All measurements referred to a 0 dB (1 V pk) input signal unless ot herwise indicated. 2fa = 1.0 MHz, fb = 0.95 MHz with f SAMPLE = 5 MHz. Specifications subject to change without notice. DIGITAL SPECIFICATIONS(TMIN to TMAX with AVDD = +5 V, DVDD = +5 V, AVSS = –5 V unless otherwise noted)
1Conversion rate is operational down to 10 kHz without degradation in specified performance. 2For clock periods of 200 ns or greater, see Clock Input section. 3See section on Three-State Outputs for timing diagrams and application information. Specifications subject to change without notice. Figure 1. Timing Diagram ratings for extended periods may affect device reliability. accumulate on the human body and test equipment and can discharge without detection. precautions are recommended to avoid performance degradation or loss of functionality.
REV. A –5– PIN FUNCTION DESCRIPTIONS DIP LCC Symbol Pin No. Pin No. Type Name and Function VINA 1 1 AI (+) Analog Input Signal on the differential input amplifier. VINB 2 2 AI (–) Analog Input Signal on the differential input amplifier. AVSS 3, 25 5, 40 P –5 V Analog Supply. AVDD 4 6, 38 P +5 V Analog Supply. AGND 5, 24 9, 36 P Analog Ground. DGND 6, 23 10 P Digital Ground. DVDD 7, 22 33 P +5 V Digital Supply. BIT 12 (LSB) 8 16 DO Least Significant Bit. BIT 2–BIT 11 18–9 26–17 DO Data Bits 2 through 11. MSB 19 29 DO Inverted Most Significant Bit. Provides twos complement output data format. OTR 20 30 DO Out of Range is Active HIGH on the leading edge of code 0 or the trailing edge of code 4096. See Output Data Format Table III. CLK 21 31 DI Clock Input. The AD871 will initiate a conversion on the rising edge of the clock input. See the Timing Diagram for details. REF OUT 26 41 AO +2.5 V Reference Output. Tie to REF IN for normal operation. REF GND 27 42 AI Reference Ground. REF IN 28 43 AI Reference Input. +2.5 V input gives ± 1 V full-scale range. BIT 1 (MSB) N/A 27 DO Most Significant Bit. DRV DD N/A 12, 32 P +5 V Digital Supply for the output drivers. DRGND N/A 11, 34 P Digital Ground for the output drivers. (See section on Power Supply Decoupling for details on DRV DD and DRGND.) OEN N/A 13 DI Output Enable. See the Three State Output Timing Diagram for details. NC N/A 3, 4, 7, 8, 14, 15, No Connect. 28, 35, 37, 39, 44 TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power; N/A = Not Available on 28-lead DIP, available only on 44-terminal surface mount package. PIN CONFIGURATIONS 28-Lead Side Brazed Ceramic DIP TOP VIEW (Not to Scale) AD871 BIT 11 BIT 12 (LSB) VINA VINB AV SS AV DD DV DD DGND AGND OTR CLK REF IN REF GND REF OUT AV SS DV DD AGND MSBBIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 DGND 44-Terminal LCC 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) NC = NO CONNECT NC AV DD NC AGND NC DRGND DV DD DRV DD CLK OTR MSB NC NC AGND DGND DRGND DRV DD OEN NC NC BIT 12 (LSB) BIT 11 AV DD AV SS NC NC VINB VINA NC BIT 10 BIT 9 BIT 8 BIT 7 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) NC BIT 6 REF IN REF GND REF OUT AV SS AD871
REV. A–6– OVERVOLTAGE RECOVERY TIME Overvoltage recovery time is defined as that amount of time required for the ADC to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converter’s range. DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. INTERMODULATION DISTORTION (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 . . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa – fb), and the third or- der terms are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (2 fb – fa). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distor- tion terms. The two signals are of equal amplitude and the peak value of their sums is –0.5 dB from full scale. The IMD prod- ucts are normalized to a 0 dB input signal. FULL-POWER BANDWIDTH The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input. SPURIOUS FREE DYNAMIC RANGE The difference, in dB, between the rms amplitude of the input signal and the peak spurious signal. ORDERING GUIDE Model Temperature Range Package Option 1 AD871JD 0 °C to +70°C D-28 AD871JE 0 °C to +70°C E-44A AD871SD2 –55°C to +125°C D-28 AD871SE2 –55°C to +125°C E-44A NOTES 1D = Side Brazed Ceramic DIP, E = Leadless Ceramic Chip Carrier. 2MIL-STD-883 version will be available; contact factory. DEFINITIONS OF SPECIFICATIONS LINEARITY ERROR Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. ZERO ERROR The major carry transition should occur for an analog value 1/2 LSB below analog common. Zero error is defined as the devia- tion of the actual transition from that point. The zero error and temperature drift specify the initial deviation and maximum change in the zero error over temperature. GAIN ERROR The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal positive full scale. Gain error is the deviation of the actual dif- ference between first and last code transitions and the ideal dif- ference between first and last code transitions. TEMPERATURE DRIFT The temperature drift for zero error and gain error specifies the maximum change from the initial (25 °C) value to the value at TMIN or TMAX. POWER SUPPLY REJECTION The specifications show the maximum change in the converter’s full-scale as the supplies are varied from nominal to min/max values. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. APERTURE DELAY Aperture delay is a measure of the Track-and-Hold Amplifier (THA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.
Figure 12 shows the common-mode rejection performance vs. Figure 12. Common-Mode Rejection vs. Input Frequency,
1 V p-p Input
Figure 13. AD871 Single-Ended Input Connection Figure 14. AD871 Single-Ended Input Connection Using a is required, we suggest either the AD811 or AD9617. mum phase matching between U1 and U2. Figure 15. Single-Ended to Differential Connections; signal (–20 dB) frequency response. Figure 16. Full Power (–0.5 dB) and Small Signal ure 17 illustrates the typical acquisition of a full-scale input step. Figure 17. Typical AD871 Settling Time
from a 50% overdrive in less than 100 ns. input bandwidth is acceptable.
10 OR 20pF
Figure 18. Optional High Frequency Noise Reduction cuitry, therefore no “kickback” into the reference. Figure 19. Equivalent Reference Input Circuit mance vs. reference voltage for a 1 MHz, –0.5 dB input signal. all three conversions in the pipeline will be invalidated. Figure 20. S/(N+D) vs. Reference Input Voltage, reduction purposes is recommended.
Figure 21. Optional +5 V Reference Input Circuit ± 1 V, without any performance degradation. stable with this capacitor in place. Figure 22. Typical Reference Decoupling Connection ence is better than 54 dB at dc. Figure 23. Reference Output Voltage vs. Temperature Figure 24. Reference Output Voltage vs. Output Load twos complement output for various analog inputs.
0.999268 V 1111 1111 1111 0111 1111 1111 0
0 V 1000 0000 0000 0000 0000 0000 0
MSB and MSB bits are provided. +FS, but may actually fold back to midscale.
Figure 34. AD872/AD871 Evaluation Board Schematic Dimensions shown in inches and (mm).