AD8603

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Multiplying DACs with Serial Interface Data Sheet AD5444/AD5446 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

12 MHz multiplying bandwidth

INL of ± 0.5 LSB at 12 bits Pin-compatible 12-/14-bit current output DAC 2.5 V to 5.5 V supply operation 10-lead MSOP package ±10 V reference input

50 MHz serial interface

2.7 MSPS update rate

Extended temperature range: −40°C to +125°C 4-quadrant multiplication Power-on reset with brownout detection 0.4 µA typical current consumption Guaranteed monotonic

APPLICATIONS

Portable, battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming Automotive radar GENERAL DESCRIPTION The AD5444/AD54461 are CMOS 12-bit and 14-bit, current output, digital-to-analog converters (DACs). Operating from a single 2.5 V to 5.5 V power supply, these devices are suited for battery-powered and other applications. As a result of the CMOS submicron manufacturing process, these parts offer excellent 4-quadrant multiplication char- acteristics of up to 12 MHz. These DACs use a double-buffered, 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. On power-up, the internal shift register and latches are filled with 0s, and the DAC output is at zero scale. The applied external reference input voltage (VREF) determines the full-scale output current. These parts can handle ±10 V inputs on the reference, despite operating from a single-supply power supply of 2.5 V to 5.5 V . An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external current-to-voltage precision amplifier. The AD5444/AD5446 DACs are available in small 10-lead MSOP packages, which are pin-compatible with the AD5425/AD5426/AD5432/AD5443 family of DACs. The EV-AD5443/46/53SDZ board is available for evaluating DAC performance. For more information, see the UG-327 evaluation board user guide. 1 US Patent Number 5,689,257. FUNCTIONAL BLOCK DIAGRAM 04588-001 POWER-ON RESET GND VREF RFB IOUT1 IOUT2 R SDOCONTROL LOGIC AND INPUT SHIFT REGISTER DAC REGISTER 12-BIT R-2R DAC INPUT LATCH SCLK SDIN SYNC VDD AD5444/ AD5446 Figure 1.

Rev. E | Page 2 of 28 TABLE OF CONTENTS Overview of AD54xx and AD55xx Current Output Devices ... 24

REVISION HISTORY

6/13—Rev. D to Rev. E 4/12—Rev. C to Rev. D 4/07—Rev. B to Rev. C 4/05—Rev. 0 to Rev. A 10/04—Revision 0: Initial Version

Rev. E | Page 3 of 28 SPECIFICATIONS VDD = 2.5 V to 5.5 V , VREF = 10 V , IOUT2 = 0 V . Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP177, and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE AD5444 Resolution 12 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Total Unadjusted Error (TUE) ±1 LSB Gain Error ±0.5 LSB AD5446 Resolution 14 Bits Relative Accuracy ±2 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Total Unadjusted Error (TUE) ±4 LSB Gain Error ±2.5 LSB Gain Error Temperature Coefficient1 ±2 ppm FSR/°C Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, IOUT1 ±10 nA Data = 0x0000, TA = −40°C to +125°C, IOUT1 REFERENCE INPUT1 Reference Input Range ±10 V VREF Input Resistance 7 9 11 kΩ Input resistance TC = −50 ppm/°C RFB Feedback Resistance 7 9 11 kΩ Input resistance TC = −50 ppm/°C Input Capacitance Zero-Scale Code 18 22 pF Full-Scale Code 18 22 pF DIGITAL INPUTS/OUTPUTS1 Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V 1.7 V VDD = 2.5 V to 3.6 V Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V 0.7 V VDD = 2.5 V to 2.7 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, ISOURCE = 200 µA VDD − 0.5 V VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, ISINK = 200 µA 0.4 V VDD = 2.5 V to 3.6 V, ISINK = 200 µA Input Leakage Current, IIL ±1 nA TA = 25°C ±10 nA TA = −40°C to +125°C Input Capacitance 10 pF

Rev. E | Page 4 of 28 Parameter Min Typ Max Unit Conditions DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth 12 MHz VREF = ±3.5 V, DAC loaded with all 1s Multiplying Feedthrough Error VREF = ±3.5 V, DAC loaded with all 0s 72 dB 100 kHz 64 dB 1 MHz 44 dB 10 MHz Output Voltage Settling Time VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 100 110 ns Measured to ±4 mV of FS 24 40 ns Measured to ±16 mV of FS 16 33 ns Digital Delay 20 40 ns Interface delay time 10%-to-90% Settling Time 10 30 ns Rise and fall time, VREF = 10 V, RLOAD = 100 Ω Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, VREF = 0 V Output Capacitance IOUT1 13 pF DAC latches loaded with all 0s 28 pF DAC latches loaded with all 1s IOUT2 18 pF DAC latches loaded with all 0s 5 pF DAC latches loaded with all 1s Digital Feedthrough 0.5 nV-s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Analog THD 83 dB VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz Digital THD Clock = 1 MHz, VREF = 3.5 V 50 kHz fOUT 71 dB 20 kHz fOUT 77 dB Output Noise Spectral Density 25 nV/√Hz @ 1 kHz SFDR Performance (Wide Band) Clock = 10 MHz, VREF = 3.5 V 50 kHz fOUT 78 dB 20 kHz fOUT 74 dB SFDR Performance (Narrow Band) Clock = 1 MHz, VREF = 3.5 V 50 kHz fOUT 87 dB 20 kHz fOUT 85 dB Intermodulation Distortion 79 dB f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V POWER REQUIREMENTS Power Supply Range, VDD 2.5 5.5 V Supply Current, IDD 0.4 10 µA TA = −40°C to +125°C, logic inputs = 0 V or VDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5% 1 Guaranteed by design and characterization; not subject to production test.

VREF = 10 V , IOUT2 = 0 V , temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted.

5.5 V Unit Conditions/Comments

fSCLK 50 50 MHz max Maximum clock frequency. t1 20 20 ns min SCLK cycle time. t2 8 8 ns min SCLK high time. t3 8 8 ns min SCLK low time. t4 8 8 ns min SYNC falling edge to SCLK active edge setup time. t5 5 5 ns min Data setup time. t6 4.5 4.5 ns min Data hold time. t8 30 30 ns min Minimum SYNC high time. t9 23 30 ns min SCLK active edge to SDO valid. 1 Guaranteed by design and characterization; not subject to production test. Figure 2. Standalone Timing Diagram EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain Timing Diagram

100 mA do not cause SCR latch-up. 1 Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes. Figure 4. Load Circuit for SDO Timing Specifications

Figure 5. Pin Configuration Table 4. Pin Function Descriptions 2 IOUT2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. into the shift register on the rising edge of SCLK. 5 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. the user to change the active edge to the rising edge. alternate edge to data loaded to the shift register. 8 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. 9 VREF DAC Reference Voltage Input. 10 RFB DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.

Rev. E | Page 14 of 28 TERMINOLOGY Relative Accuracy or Integral Nonlinearity Relative accuracy or integral nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero scale and full scale and is normally expressed in LSBs or as a percentage of full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For this DAC, ideal maximum output is V REF − 1 LSB. Gain error of the DAC is adjustable to zero with external resistance. Output Leakage Current Output leakage current is current that flows in the DAC ladder switches when the ladder is turned off. For the I OUT1 line, it can be measured by loading all 0s to the DAC and measuring the I OUT1 current. Minimum current flows in the IOUT2 line when the DAC is loaded with all 1s. Output Capacitance Capacitance from IOUT1 or IOUT2 to AGND. Output Current Settling Time The amount of time it takes for the output to settle to a speci- fied level for a full-scale input change. For this device, it is specified with a 100 Ω resistor to ground. The settling time specification includes the digital delay from the SYNC rising edge to the full-scale output change. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either picoamps per second or nanovolts per second, depending upon whether the glitch is measured as a current or voltage signal. Digital Feedthrough When the device is not selected, high frequency logic activ- ity on the device’s digital inputs can be capacitively coupled through the device to show up as noise on the I OUT1 and IOUT2 pins and, subsequently, into the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error Multiplying feedthrough error is due to capacitive feedthrough from the DAC reference input to the DAC I OUT1 line, when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower-order harmonics, such as second to fifth, are included. 5432 V VVVVTHD 2222 log20 +++= Digital Intermodulation Distortion Second-order intermodulation (IMD) measurements are the relative magnitudes of the fa and fb tones digitally generated by the DAC and the second-order products at 2fa − fb and 2fb − fa. Compliance Voltage Range The maximum range of (output) terminal voltage for which the device provides the specified characteristics. Spurious-Free Dynamic Range (SFDR) The usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate or f S/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.

1. ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 43. Current-Steering DAC Used as a Divider amplifier does not saturate and the required accuracy is met. opposite current supplied from the op amp through the DAC. where R is the DAC resistance at the VREF terminal. (1/D) of 16, the error voltage is 1.6 mV . IN and AGND), they settle quickly. input, capacitance buffer amplifiers and careful board design. should be consistent with the system accuracy specifications. should be less than 78 ppm/°C. temperature coefficient, this error source can be minimized.

Table 7. Suitable Analog Devices Precision References Table 8. Suitable Analog Devices Precision Op Amps Table 9. Suitable Analog Devices High Speed Op Amps

Rev. E | Page 23 of 28 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. The printed circuit boards on which the AD5444/AD5446 are mounted should be designed so the analog and digital sections are separated and confined to certain areas of the board. If the DACs are in systems in which multiple devices require a AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the devices. The DAC should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the pack- age as possible, ideally right up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on oppo- site sides of the board should run at right angles to each other. This reduces the effects of feedthrough throughout the board. A microstrip technique, by far the best, is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead-length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between V REF and RFB should also be matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close to the device as possible.

Rev. E | Page 24 of 28 OVERVIEW OF AD54xx AND AD55xx CURRENT OUTPUT DEVICES Table 12. Part Number Resolution (Bits) Number of DACs INL (LSB) Interface Package1 Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-10 12 MHz BW, 50 MHz serial interface AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-10 12 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.

0.50 BSC

1.10 MAX

Figure 54. 10-Lead Mini Small Outline Package [MSOP]

Rev. E | Page 26 of 28 NOTES

Rev. E | Page 27 of 28 NOTES

Rev. E | Page 28 of 28 NOTES ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04588-0-6/13(E)