AD8600 (Rev. 0) - OBSOLETE
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 16
Technical content
Tel: 617/329-4700 Fax: 617/326-8703 FUNCTIONAL BLOCK DIAGRAM R/W VDD1 LD CONTROL LOGIC ADDRESS DECODE 16 x 8 INPUT REGISTERS RS VDD2 VREF VCC 16 x 8 DAC REGISTERS 8-BIT DACS CS EN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 O10 O11 O12 O13 O14 O15 VEEDGND1 DGND2 DACGND AD8600 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 16-Channel, 8-Bit Multiplying DAC AD8600
FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference 2 µs Settling Time Double Buffered 8-Bit Parallel Input High Speed Data Load Rate Data Readback Operates from Single +5 V Optional ±6 V Supply Extends Output Range
APPLICATIONS
Phased Array Ultrasound & Sonar Power Level Setting Receiver Gain Setting Automatic Test Equipment LCD Clock Level Setting GENERAL DESCRIPTION The AD8600 contains 16 independent voltage output digital-to- analog converters that share a common external reference input voltage. Each DAC has its own DAC register and input register to allow double buffering. An 8-bit parallel data input, four ad- dress pins, a CS select, a LD, EN, R/W, and RS provide the digital interface. The AD8600 is constructed in a monolithic CBCMOS process which optimizes use of CMOS for logic and bipolar for speed and precision. The digital-to-analog converter design uses volt- age mode operation ideally suited to single supply operation. The internal DAC voltage range is fixed at DACGND to V REF. The voltage buffers provide an output voltage range that ap- proaches ground and extends to 1.0 V below V CC. Changes in reference voltage values and digital inputs will settle within ± 1 LSB in 2 µs. Data is preloaded into the input registers one at a time after the internal address decoder selects the input register. In the write mode (R/ W low) data is latched into the input register during the positive edge of the EN pulse. Pulses as short as 40 ns can be used to load the data. After changes have been submitted to the input registers, the DAC registers are simultaneously up- dated by a common load EN × LD strobe. The new analog out- put voltages simultaneously appear on all 16 outputs. At system power up or during fault recovery the reset ( RS) pin forces all DAC registers into the zero state which places zero volts at all DAC outputs. The AD8600 is offered in the PLCC-44 package. The device is designed and tested for operation over the extended industrial temperature range of –40°C to +85°C. VDD1 DACGND R/WCSADDRESS RS VDD2 VREF VCC DGND2 DGND1 R-2R DAC LDEN VEERS R/WCSADDREN OX DAC REGISTER INPUT REGISTERDB7...DB0 Figure 1. Equivalent DAC Channel
AD8600–SPECIFICATIONS SINGLE SUPPLY Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE 1 Resolution N 8 Bits Relative Accuracy 2 INL –1 ± 1/2 +1 LSB Differential Nonlinearity 2 DNL Guaranteed Monotonic –1 ± 1/4 +1 LSB Full-Scale Voltage VFS Data = FFH 2.480 2.490 2.500 V Full-Scale Tempco TCV FS Data = FFH ± 20 ppm/ °C Zero Scale Error V ZSE Data = 00H, RS = “0,” TA = +25°C +3.5 LSB VZSE Data = 00H, RS = “0” +5 LSB Reference Input Resistance R REF Data = ABH 1.2 2 kΩ ANALOG OUTPUT Output Voltage Range 2 OVRSS VREF = +2.5 V 0.000 2.500 V Output Current IOUT Data = 80H ± 2m A Capacitive Load CL No Oscillation 50 pF LOGIC INPUTS Logic Input Low Voltage V IL 0.8 V Logic Input High Voltage V IH 2.4 V Logic Input Current IIL 10 µA Logic Input Capacitance 3 CIL 10 pF LOGIC OUTPUTS Logic Out High Voltage V OH IOH = –0.4 mA 3.5 V Logic Out Low Voltage V OL IOL = 1.6 mA 0.4 V AC CHARACTERISTICS 3 Slew Rate SR For Δ VREF or FS Code Change 4 7 V/µs Voltage Output Settling Time 2 tS1 ± 1 LSB of Final Value, Full-Scale Data Change 2 µs Voltage Output Settling Time 2 tS2 ± 1 LSB of Final Value, Δ VREF = 1 V, Data = FFH 2 µs POWER SUPPLIES Positive Supply Current I CC VIH = 5 V, VIL = 0 V, No Load 24 35 mA Logic Supply Currents I DD1&2 VIH = 5 V, VIL = 0 V, No Load 0.1 mA Power Dissipation PDISS VIH = 5 V, VIL = 0 V, No Load 120 175 mW Power Supply Sensitivity PSS ΔVCC = ± 5% 0.007 %/% Logic Power Supply Range V DDR 4.75 5.25 V Positive Power Supply Range 3 VCCR VDD 7.0 V NOTES 1When VREF = 2.500 V, 1 LSB = 9.76 mV. 2Single supply operation does not include the final 2 LSBs near analog ground. If this performance is critical, use a negative supply (V EE) pin of at least –0.7 V to –5.25 V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 7 10 to 8010. 3Guaranteed by design not subject to production test. Specifications subject to change without notice. REV. 0–2– (@ VDD1 = VDD2 = VCC = +5 V ± 5%, VEE = 0 V, VREF = +2.500 V, –40 °C ≤ TA ≤ +85°C, unless otherwise noted) OBSOLETE
Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE 1 Resolution N 8 Bits Total Unadjusted Error TUE All Other DACs Loaded with Data = 55 H –1 ± 3/4 +1 LSB Relative Accuracy INL –1 ± 1/2 +1 LSB Differential Nonlinearity DNL Guaranteed Monotonic –1 ± 1/4 +1 LSB Full-Scale Voltage V FS Data = FFH, VREF = +3.5 V 3.473 3.486 3.500 V Full-Scale Voltage Error V FSE Data = FFH, VREF = +3.5 V –1 +1 LSB Full-Scale Tempco TCVFS Data = FFH, VREF = +3.5 V ± 20 ppm/ °C Zero Scale Error V ZSE Data = 00H, RS = “0,” TA = +25°C– 2 ± 1+ 2 m V Zero Scale Error V ZSE Data = 00H, All Other DACs Data = 00 H –1 +1 LSB Zero Scale Error VZSE Data = 00H, All Other DACs Data = 55 H ± 1/2 LSB Zero Scale Tempco TCV ZS Data = 00H, VCC = +5 V, VEE = –5 V ± 10 µV/°C Reference Input Resistance R REF Data = ABH 1.2 2 kΩ Reference Input Capacitance 2 CREF Data = ABH 240 pF ANALOG OUTPUT Output Voltage Range OVR 1 VREF = +3.5 V 0.000 3.500 V Output Voltage Range 2 OVR2 VCC = VDD2 = +7 V, VEE = –0.7 V, VREF = 5 V 0.000 5.000 V Output Current IOUT Data = 80H ± 2m A Capacitive Load 2 CL No Oscillation 50 pF LOGIC INPUTS Logic Input Low Voltage V IL 0.8 V Logic Input High Voltage V IH 2.4 V Logic Input Current IIL 10 µA Logic Input Capacitance 2 CIL 10 pF LOGIC OUTPUTS Logic Out High Voltage V OH IOH = –0.4 mA 3.5 V Logic Out Low Voltage V OL IOL = 1.6 mA 0.4 V AC CHARACTERISTICS 2 Reference In Bandwidth BW –3 dB Frequency, V REF = 2.5 VDC + 0.1 VAC 500 kHz Slew Rate SR For ΔVREF or FS Code Change 4 7 V/µs Voltage Noise Density eN f = 1 kHz, VREF = 0 V 46 nV/√Hz Digital Feedthrough FT Digital Inputs to DAC Outputs 10 nVs Voltage Output Settling Time 3 tS1 ± 1 LSB of Final Value, FS Data Change 1 2 µs Voltage Output Settling Time 3 tS2 ± 1 LSB of Final Value, ΔVREF = 1 V, Data = FFH 12 µs POWER SUPPLIES Positive Supply Current I CC VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load 22 35 mA Negative Supply Current I EE VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load 22 35 mA Logic Supply Currents I DD1&2 VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load 0.1 mA Power Dissipation 4 PDISS VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load 225 350 mW Power Supply Sensitivity PSS ΔVCC & ΔVEE = ± 5% 0.007 %/% Logic Power Supply Range V DDR 4.75 5.25 V Pos Power Supply Range 2 VCCR VDD 7.0 V Neg Power Supply Range 2 VEER –5.25 0.0 V NOTES 1When VREF = +3.500 V, 1 LSB = 13.67 mV. 2Guaranteed by design not subject to production test. 3Settling time test is performed using R L = 50 kΩ and CL = 35 pF. 4Power Dissipation is calculated using 5 V × (IDD + |ISS| + IDD1 + IDD2). Specifications subject to change without notice. DUAL SUPPLY (@ VDD1 = VDD2 = VCC = +5 V ± 5%, VEE = –5 V ± 5%, VREF = +3.500 V, –40 °C ≤ TA ≤ +85°C, unless otherwise noted) AD8600 REV. 0 –3– OBSOLETE
REV. 0 –5– PIN DESCRIPTION Pin No. Name Description
1 NC No Connection
2V REF Reference input voltage common to all DACs. 3 DACGND DAC Analog Ground Return. Sets analog zero-scale voltage. CC Output Amplifier Positive Supply 5V EE Output Amplifier Negative Supply 6 O7 DAC Channel Output No. 7 7 O6 DAC Channel Output No. 6 8 O5 DAC Channel Output No. 5 9 O4 DAC Channel Output No. 4 10 O3 DAC Channel Output No. 3 11 O2 DAC Channel Output No. 2 12 O1 DAC Channel Output No. 1 13 O0 DAC Channel Output No. 0 14 V DD1 Digital Logic Power Supply
15 RS Active Low Reset Input Pin
16 DB0 Data Bit Zero I/O (LSB)
17 DB1 Data Bit I/O
18 DB2 Data Bit I/O
19 DB3 Data Bit I/O
20 DB4 Data Bit I/O
21 DB5 Data Bit I/O
22 DB6 Data Bit I/O
23 DB7 Most Significant Data Bit I/O (MSB)
24 A0 Address Bit Zero (LSB)
25 A1 Address Bit
26 A2 Address Bit
27 A3 Most Significant Addr Bit (MSB)
W Read/Write Select Control Input
29 EN Active Low Enable Clock Strobe
30 CS Chip Select Input
31 LD DAC Register Load Strobe
32 DGND1 Digital Ground Input No. 1 33 O15 DAC Channel Output No. 15 34 O14 DAC Channel Output No. 14 35 O13 DAC Channel Output No. 13 36 O12 DAC Channel Output No. 12 37 O11 DAC Channel Output No. 11 38 O10 DAC Channel Output No. 10 39 O9 DAC Channel Output No. 9 40 O8 DAC Channel Output No. 8 41 V EE Output Amplifier Negative Supply
42 V CC Output Amplifier Positive Supply
43 DGND2 Digital Ground Input No. 2
44 V DD2 DAC Analog Supply Voltage
WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8600 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS (TA= +25°C unless otherwise noted) Short Circuit Duration Thermal Resistance–Theta Junction-to-Ambient ( θJA) NOTE 1No more than four outputs may be shorted to power or GND simultaneously. PIN CONFIGURATION NC = NO CONNECT O10 O13 O14 O15 O11 O12 VEE VREF NC VDD2 VCC DB2 DB3 DB6 DB7 DB4 DB5 DACGND VCC VEE R/W A1 DGND2 LD CS EN DGND1 RS DB0 DB1 VDD1 44 1 264 5 21 24 232218 2019 40 41 42 25 28 2726 TOP VIEW (Not to Scale) AD8600 ORDERING GUIDE Package Package Model Temperature Description Option AD8600AP –40 °C to +85°C 44-Lead PLCC P-44A AD8600Chips +25 °C Die* *For die specifications contact your local Analog Devices sales office. The AD8600 contains 5782 transistors. OBSOLETE
REV. 0–6– AD8600 TRANSFER EQUATIONS Output Voltage Oi = D × VREF 256 where i is the DAC channel number and D is the decimal value of the DAC register data. Table I. Truth Table EN R/W CS LD RS Operation Write to DAC Register – X H L H Update DAC Register L X H – H Update DAC Register + X H L H Latches DAC Register L X H + H Latches DAC Register L L L L H DAC Register Transparent Write to Input Register L L L H H Load Data to Input Register at Decoded Address + L L H H Latches Data in Input Register at Decoded Address L L + H H Latches Data in Input Register at Decoded Address Readback Input Registers X H L H H Input Register Readback (Data Access) X H + H H Hi-Z Readback Disconnects from Bus X X H X X Hi-Z on Data Bus Reset X X X X L Clear All Registers to Zero, V OUT = 0 V X X H H + Latches All Registers to Zero LX LH + CS = Low; Input Register Ready for R/W, DAC Register Latched to Zero NOTES 1+ symbol means positive edge of control input line. 2– symbol means negative edge of control input line. Decoded DAC Register Oi = A where A is the decimal value of the decoded address bits A3, A2, A1, A0 (LSB). Address, CS, R/W and data inputs should be stable prior to acti- vation of the active low EN input. Input registers are transpar- ent when EN is low. When EN returns high, data is latched into the decoded input register. When the load strobe LD and EN pins are active low, all input register data is transferred to the DAC registers. The DAC registers are transparent while they are enabled. Table II. Address Decode Table A3 A2 A1 A0 Addr DAC (MSB) (LSB) Code Updated (Binary) (Hex) 000 0 0 O 0 000 1 1 O 1 001 0 2 O 2 001 1 3 O 3 010 0 4 O 4 010 1 5 O 5 011 0 6 O 6 011 1 7 O 7 100 0 8 O 8 100 1 9 O 9 101 0 A O 1 0 101 1 B O 1 1 110 0 C O 1 2 110 1 D O 1 3 111 0 E O 1 4 111 1 F O 1 5 OBSOLETE
CMOS logic should be used to interface to the AD8600. decoupled with a 0.1 µF ceramic capacitor close to the pin. Figure 18. ESD Protection Diode Locations low noise ground to maintain accuracy in the analog circuitry.
5 V Output Swing
The output swing is limited to 1.0 V below the positive supply. +5 V to ensure that the input logic levels do not change. The AD8600 is designed for one reference to drive all 16 DACs. AD8600 can easily be driven from a single reference.
Figure 19. Logic Interface Circuit for DAC Channel 0
- This figure specifically shows the logic for Channel 0; how-
inputs will immediately change the DAC’s R-2R ladder. Table I details the different logic combinations and their effects. data on DB7–DB0 changes the contents of the input register. This data is not latched until either EN or CS returns high. address should be updated at the same time as EN goes low. which is just the reciprocal of 80 ns. DAC register without loading the other 15 input registers. of the data lines or bus passes back to the microprocessor.
REV. 0–12– AD8600 * This program contains subroutines to read and write * to the AD8600 from the 68HC11. Additionally, a ramp * program has been included, to continuously ramp the * output giving a triangle wave output. * The following connections need to be made: * 68HC11 AD8600 * GND DGND1,2 * PC0-PC7 DB0–DB7 respectively, data port * PB0-PB3 A0–A3 respectively, address port * PB4 LD * PB5 EN * PB6 R/W * PB7 CS portc equ $1003 define port addresses portb equ $1004 ddrc equ $1007 org $C000 read lds #$CFFF subroutine to read from AD8600 ldaa #$00 initialize port c to 00000000 staa ddrc configures PC0-PC7 as inputs. ldx #$00 points to DAC address in 68HC11 memory ldaa 0,x put the address in the accumulator adda #$70 add the control bits to the address * R/W, LD, EN are high, CS is low. staa portb output control and address on port b. inx points to memory location to store the data ldaa portc read data from DAC staa 0,x Store this data in memory at address “x” ldy #$1000 bset portb,y $f0 Set CS, LD, EN high jmp $e000 Return to BUFFALO write lds #$cfff routine to write to AD8600 ldaa #$ff initialize port c to 11111111 staa ddrc configures PC0-PC7 as outputs. ldx #$00 points to DAC address in 68HC11 mem ldaa 0,x puts the address in the accumulator adda #$30 set CS, R/W low and LD, EN high staa portb output to portb for control and address inx points to memory location to store the data ldaa 0,x load the data into the accumulator staa portc write the data to the DAC ldy #$1000 bclr portb,y $30 Set LD, EN low to latch data bset portb,y $b0 Bring LD, EN, CS high, write is complete jmp $e000 Return to BUFFALO ramp lds #$cfff routine to generate a triangle wave ldaa #$ff configure port c as outputs OBSOLETE
Figure 22. 68HC11 Microcode to Interface to the AD8600. to generate a ramped output to control the gain of the AD600. to C1HI. This ramp sweeps the gain from 0 dB to 40 dB.
46 REF43
Figure 23. Ultrasound Amplifier with Digitally Controlled
REV. 0 –15– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Lead Chip Carrier (PLCC) Package (P-44A) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.015 (0.38) 0.180 (4.57) 0.165 (4.19) 0.63 (16.00) 0.59 (14.99) 0.110 (2.79) 0.085 (2.16) 0.040 (1.01) 0.025 (0.64) 0.050 (1.27) BSC 0.656 (16.66) 0.650 (16.51)SQ 0.695 (17.65) 0.685 (17.40)SQ 0.048 (1.21) 0.042 (1.07) 40 6 TOP VIEW PIN 1 IDENTIFIER 0.020 (0.50) R OBSOLETE
REV. 0–16– AD8600 PRINTED IN U.S.A. C1921–18–7/94 OBSOLETE