AD8402AN50

AD8400 AD | Alldatasheet

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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 1-/2-/4-Channel Digital Potentiometers AD8400/AD8402/AD8403 Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997

FEATURES

256 Position

Replaces 1, 2 or 4 Potentiometers 1 kV, 10 k V, 50 k V, 100 k V Power Shut Down—Less than 5 mA 3-Wire SPI Compatible Serial Data Input

10 MHz Update Data Loading Rate

+2.7 V to +5.5 V Single-Supply Operation Midscale Preset

APPLICATIONS

Mechanical Potentiometer Replacement Programmable Filters, Delays, Time Constants Volume Control, Panning Line Impedance Matching Power Supply Adjustment FUNCTIONAL BLOCK DIAGRAM RDAC1 SHDN 88-BIT LATCH CK RS RDAC2 SHDN 88-BIT LATCH CK RS RDAC3 SHDN 88-BIT LATCH CK RS RDAC4 SHDN 88-BIT LATCH CK RS SHDN DAC SELECT A1, A0 10-BIT SERIAL LATCH CK Q RS D RSSDO AGND1 AGND2 AGND3 AGND4 AD8403 VDD DGND SDI CLK CS GENERAL DESCRIPTION The AD8400/AD8402/AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in space saving SO-14 surface mount package. The AD8403 con- tains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point deter- mined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 k Ω , 10 kΩ , 50 kΩ or 100 kΩ has a ± 1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching cir- cuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before- make operation. Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without addi- tional external decoding logic. The reset ( RS) pin forces the wiper to the midscale position by loading 80H into the VR latch. The SHDN pin forces the resis- tor to an end-to-end open circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface is still active in shutdown so that code changes can be made which will produce new wiper positions when the device is taken out of shutdown. The AD8400 is available in both the SO-8 surface mount and the 8-lead plastic DIP package. The AD8402 is available in both surface mount (SO-14) and the 14-lead plastic DIP package, while the AD8403 is available in a narrow body 24-lead plastic DIP and the 24-lead surface mount package. The AD8402/AD8403 are also offered in the 1.1 mm thin TSSOP-14/TSSOP-24 package for PCMCIA ap- plications. All parts are guaranteed to operate over the extended industrial temperature range of –40 °C to +85°C.

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ 1 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL R WB, VA = NC –1 ± 1/4 +1 LSB Resistor Nonlinearity 2 R-INL R WB, VA = NC –2 ± 1/2 +2 LSB Nominal Resistance3 RT A = +25°C, Model: AD840XYY10 8 10 12 k Ω Resistance Tempco ΔRAB/ΔTV AB = VDD, Wiper = No Connect 500 ppm/ °C Wiper Resistance R W IW = 1 V/R 50 100 Ω Nominal Resistance Match ΔR/RO CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C 0.2 1 % DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs Resolution N 8 Bits Integral Nonlinearity 4 INL –2 ± 1/2 +2 LSB Differential Nonlinearity 4 DNL V DD = +5 V –1 ± 1/4 +1 LSB DNL V DD = +3 V TA = +25°C– 1 ± 1/4 +1 LSB DNL V DD = +3 V TA = –40°C, +85°C –1.5 ± 1/2 +1.5 LSB Voltage Divider Tempco ΔVW/ΔT Code = 80 H 15 ppm/ °C Full-Scale Error V WFSE Code = FFH –4 –2.8 0 LSB Zero-Scale Error V WZSE Code = 00H 0 +1.3 +2 LSB RESISTOR TERMINALS Voltage Range5 VA, B, W 0V DD V Capacitance6 Ax, Bx C A, B f = 1 MHz, Measured to GND, Code = 80 H 75 pF Capacitance6 Wx C W f = 1 MHz, Measured to GND, Code = 80 H 120 pF Shutdown Current7 IA_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA Shutdown Wiper Resistance R W_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V 100 200 Ω DIGITAL INPUTS & OUTPUTS Input Logic High V IH VDD = +5 V 2.4 V Input Logic Low V IL VDD = +5 V 0.8 V Input Logic High V IH VDD = +3 V 2.1 V Input Logic Low V IL VDD = +3 V 0.6 V Output Logic High V OH RL = 1 kΩ to VDD VDD–0.1 V Output Logic Low V OL IOL = 1.6 mA, VDD = +5 V 0.4 V Input Current I IL VIN = 0 V or +5 V, VDD = +5 V ± 1 µA Input Capacitance6 CIL 5p F POWER SUPPLIES Power Supply Range V DD Range 2.7 5.5 V Supply Current (CMOS) I DD VIH = VDD or VIL = 0 V 0.01 5 µA Supply Current (TTL) 8 IDD VIH = 2.4 V or 0.8 V, V DD = +5.5 V 0.9 4 mA Power Dissipation (CMOS) 9 PDISS VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW Power Supply Sensitivity PSS V DD = +5 V ± 10% 0.0002 0.001 %/% PSS V DD = +3 V ± 10% 0.006 0.03 %/% DYNAMIC CHARACTERISTICS 6, 10 Bandwidth –3 dB BW_10K R = 10 k Ω 600 kHz Total Harmonic Distortion THD W VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 % VW Settling Time t S VA = VDD, VB = 0 V, ± 1% Error Band 2 µs Resistor Noise Voltage e NWB RWB = 5 kΩ , f = 1 kHz, RS = 0 9 nV/ √Hz Crosstalk11 CT VA = VDD, VB = 0 V –65 dB NOTES FOR 10 k Ω VERSION 1 Typicals represent average readings at +25 °C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit. I W = 50 µA for VDD = +3 V and I W = 400 µA for VDD = +5 V for the 10 k Ω versions. 3 VAB = VDD, Wiper (V W) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 8 Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage. 9 PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All Dynamic Characteristics use V DD = +5 V. 11 Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice. AD8400/AD8402/AD8403–SPECIFICATIONS (VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –40 8C ≤ TA ≤ +858C unless otherwise noted) REV. B–2–

50 kV & 100 kV VERSION Parameter Symbol Conditions Min Typ 1 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL R WB, VA = NC –1 ± 1/4 +1 LSB Resistor Nonlinearity 2 R-INL R WB, VA = NC –2 ± 1/2 +2 LSB Nominal Resistance3 RT A = +25°C, Model: AD840XYY50 35 50 65 k Ω RT A = +25°C, Model: AD840XYY100 70 100 130 k Ω Resistance Tempco ΔRAB/ΔTV AB = VDD, Wiper = No Connect 500 ppm/ °C Wiper Resistance R W IW = 1 V/R 53 100 Ω Nominal Resistance Match ΔR/RO CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C 0.2 1 % DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs Resolution N 8 Bits Integral Nonlinearity 4 INL –4 ± 1 +4 LSB Differential Nonlinearity 4 DNL V DD = +5 V –1 ± 1/4 +1 LSB DNL V DD = +3 V TA = +25°C– 1 ± 1/4 +1 LSB DNL V DD = +3 V TA = –40°C, +85°C –1.5 ± 1/2 +1.5 LSB Voltage Divider Tempco ΔVW/ΔT Code = 80 H 15 ppm/ °C Full-Scale Error V WFSE Code = FFH –1 –0.25 0 LSB Zero-Scale Error V WZSE Code = 00H 0 +0.1 +1 LSB RESISTOR TERMINALS Voltage Range5 VA, B, W 0V DD V Capacitance6 Ax, Bx C A, B f = 1 MHz, Measured to GND, Code = 80 H 15 pF Capacitance6 Wx C W f = 1 MHz, Measured to GND, Code = 80 H 80 pF Shutdown Current7 IA_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA Shutdown Wiper Resistance R W_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V 100 200 Ω DIGITAL INPUTS & OUTPUTS Input Logic High V IH VDD = +5 V 2.4 V Input Logic Low V IL VDD = +5 V 0.8 V Input Logic High V IH VDD = +3 V 2.1 V Input Logic Low V IL VDD = +3 V 0.6 V Output Logic High V OH RL = 1 kΩ to VDD VDD–0.1 V Output Logic Low V OL IOL = 1.6 mA, VDD = +5 V 0.4 V Input Current I IL VIN = 0 V or +5 V, VDD = +5 V ± 1 µA Input Capacitance6 CIL 5p F POWER SUPPLIES Power Supply Range V DD Range 2.7 5.5 V Supply Current (CMOS) I DD VIH = VDD or VIL = 0 V 0.01 5 µA Supply Current (TTL) 8 IDD VIH = 2.4 V or 0.8 V, V DD = +5.5 V 0.9 4 mA Power Dissipation (CMOS) 9 PDISS VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW Power Supply Sensitivity PSS V DD = +5 V ± 10% 0.0002 0.001 %/% PSS V DD = +3 V ± 10% 0.006 0.03 %/% DYNAMIC CHARACTERISTICS 6, 10 Bandwidth –3 dB BW_50K R = 50 k Ω 125 kHz BW_100K R = 100 k Ω 71 kHz Total Harmonic Distortion THD W VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.003 % VW Settling Time t S_50K V A = VDD, VB = 0 V, ± 1% Error Band 9 µs tS_100K V A = VDD, VB = 0 V, ± 1% Error Band 18 µs Resistor Noise Voltage e NWB_50K R WB = 25 kΩ , f = 1 kHz, RS = 0 20 nV/ √Hz eNWB_100K R WB = 50 kΩ , f = 1 kHz, RS = 0 29 nV/ √Hz Crosstalk11 CT VA = VDD, VB = 0 V –65 dB NOTES FOR 50 k Ω and 100 k Ω VERSIONS 1 Typicals represent average readings at +25 °C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit. IW = VDD/R for VDD = +3 V or +5 V for the 50 k Ω and 100 k Ω versions. 3 VAB = VDD, Wiper (V W) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 8 Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage. 9 PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All Dynamic Characteristics use V DD = +5 V. 11 Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice. AD8400/AD8402/AD8403 REV. B –3– (VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –40 8C ≤ TA ≤ +858C unless otherwise noted) SPECIFICATIONS

Parameter Symbol Conditions Min Typ 1 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL R WB, VA = NC –5 –1 +3 LSB Resistor Nonlinearity 2 R-INL R WB, VA = NC –4 ± 1.5 +4 LSB Nominal Resistance3 RT A = +25°C, Model: AD840XYY1 0.8 1.2 1.5 k Ω Resistance Tempco ΔRAB/ΔTV AB = VDD, Wiper = No Connect 700 ppm/ °C Wiper Resistance R W IW = 1 V/RAB 53 100 Ω Nominal Resistance Match ΔR/RO CH 1 to 2, VAB = VDD, TA = +25°C 0.75 2 % DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs Resolution N 8 Bits Integral Nonlinearity 4 INL –6 ± 2 +6 LSB Differential Nonlinearity 4 DNL V DD = +5 V –4 –1.5 +2 LSB DNL V DD = +3 V, TA = +25°C –5 –2 +5 LSB Voltage Divider Temperature Coefficent ΔVW/ΔT Code = 80 H 25 ppm/ °C Full-Scale Error V WFSE Code = FFH –20 –12 0 LSB Zero-Scale Error V WZSE Code = 00H 0 6 10 LSB RESISTOR TERMINALS Voltage Range5 VA, B, W 0V DD V Capacitance6 Ax, Bx C A, B f = 1 MHz, Measured to GND, Code = 80 H 75 pF Capacitance6 Wx C W f = 1 MHz, Measured to GND, Code = 80 H 120 pF Shutdown Supply Current 7 IDD_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 µA Shutdown Wiper Resistance R W_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V 50 100 Ω DIGITAL INPUTS & OUTPUTS Input Logic High V IH VDD = +5 V 2.4 V Input Logic Low V IL VDD = +5 V 0.8 V Input Logic High V IH VDD = +3 V 2.1 V Input Logic Low V IL VDD = +3 V 0.6 V Output Logic High V OH RL = 1 kΩ to VDD VDD–0.1 V Output Logic Low V OL IOL = 1.6 mA, VDD = +5 V 0.4 V Input Current I IL VIN = 0 V or +5 V, VDD = +5 V ± 1 µA Input Capacitance6 CIL 5p F POWER SUPPLIES Power Supply Range V DD Range 2.7 5.5 V Supply Current (CMOS) I DD VIH = VDD or VIL = 0 V 0.01 5 µA Supply Current (TTL)8 IDD VIH = 2.4 V or 0.8 V, V DD = +5.5 V 0.9 4 mA Power Dissipation (CMOS) 9 PDISS VIH = VDD or VIL = 0 V, VDD = +5.5 V 27.5 µW Power Supply Sensitivity PSS ΔVDD = +5 V ± 10% 0.0035 0.008 %/% DYNAMIC CHARACTERISTICS 6, 10 Bandwidth –3 dB BW_1K R = 1 k Ω 5,000 kHz Total Harmonic Distortion THD W VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.015 % VW Settling Time t S VA = VDD, VB = 0 V, ± 1% Error Band 0.5 µs Resistor Noise Voltage e NWB RWB = 500 Ω , f = 1 kHz, RS = 0 3 nV/ √Hz Crosstalk11 CT VA = VDD, VB = 0 V –65 dB NOTES FOR 1 k Ω VERSION 1 Typicals represent average readings at +25 °C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. See Figure 30 test circuit. IW = 500 µA for VDD = +3 V and I W = 4 mA for V DD = +5 V for 1 k Ω version. 3 VAB = VDD, Wiper (V W) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 8 Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage. 9 PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All Dynamic Characteristics use V DD = +5 V. 11 Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice. AD8400/AD8402/AD8403–SPECIFICATIONS (VDD = +3 V 6 10% or + 5 V 6 10%, VA = +VDD, VB = 0 V, –40 8C ≤ TA ≤ +858C unless otherwise noted) –4– REV. B

–6– REV. B Table I. Serial Data Word Format ADDR DATA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB MSB LSB 29 28 27 20 PIN CONFIGURATIONS TOP VIEW (Not to Scale) AD8400 CLK VDD GND CS SDI TOP VIEW (Not to Scale) AGND VDD AD8402 SDI CLK RSDGND SHDN CS TOP VIEW (Not to Scale) AD8403 AGND2 AGND1 B3AGND4 DGND SHDN RS V DD AGND3 CS SDI CLK SDO ORDERING GUIDE #CHs/ Temperature Package Package Model k V Range Description Option* AD8400AN10 X1/10 -40 °C to +85°C PDIP-8 N-8 AD8400AR10 X1/10 -40 °C to +85°C SO-8 SO-8 AD8402AN10 X2/10 -40 °C to +85°C PDIP-14 N-14 AD8402AR10 X2/10 -40 °C to +85°C SO-14 SO-14 AD8402ARU10 X2/10 -40 °C to +85°C TSSOP-14 RU-14 AD8403AN10 X4/10 -40 °C to +85°C PDIP-24 N-24 AD8403AR10 X4/10 -40 °C to +85°C SOIC-24 SOL-24 AD8403ARU10 X4/10 -40 °C to +85°C TSSOP-24 RU-24 AD8400AN50 X1/50 -40 °C to +85°C PDIP-8 N-8 AD8400AR50 X1/50 -40 °C to +85°C SO-8 SO-8 AD8402AN50 X2/50 -40 °C to +85°C PDIP-14 N-14 AD8402AR50 X2/50 -40 °C to +85°C SO-14 SO-14 AD8403AN50 X4/50 -40 °C to +85°C PDIP-24 N-24 AD8403AR50 X4/50 -40 °C to +85°C SOIC-24 SOL-24 AD8400AN100 X1/100 -40 °C to +85°C PDIP-8 N-8 AD8400AR100 X1/100 -40 °C to +85°C SO-8 SO-8 AD8402AN100 X2/100 -40 °C to +85°C PDIP-14 N-14 AD8402AR100 X2/100 -40 °C to +85°C SO-14 SO-14 AD8402ARU100 X2/100 -40 °C to +85°C TSSOP-14 RU-14 AD8403AN100 X4/100 -40 °C to +85°C PDIP-24 N-24 AD8403AR100 X4/100 -40 °C to +85°C SOIC-24 SOL-24 AD8403ARU100 X4/100 -40 °C to +85°C TSSOP-24 RU-24 AD8400AN1 X1/1 -40 °C to +85°C PDIP-8 N-8 AD8400AR1 X1/1 -40 °C to +85°C SO-8 SO-8 AD8402AN1 X2/1 -40 °C to +85°C PDIP-14 N-14 AD8402AR1 X2/1 -40 °C to +85°C SO-14 SO-14 AD8403AN1 X4/1 -40 °C to +85°C PDIP-24 N-24 AD8403AR1 X4/1 -40 °C to +85°C SOIC-24 SOL-24 AD8403ARU1 X4/1 -40 °C to +85°C TSSOP-24 RU-24 *N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO. The AD8400, AD8402 and the AD8403 contain 720 transistors.

REV. B –7– AD8400 PIN DESCRIPTIONS Pin Name Description

1 B1 Terminal B RDAC

2 GND Ground

3 CS Chip Select Input, Active Low. When CS returns high data in the serial input register is loaded into the DAC register.

4 SDI Serial Data Input

5 CLK Serial Clock Input, positive edge triggered

6V DD Positive power supply, specified for operation at both +3 V and +5 V.

7 W1 Wiper RDAC, addr = 00 2

8 A1 Terminal A RDAC

1 AGND Analog Ground*

2 B2 Terminal B RDAC #2

3 A2 Terminal A RDAC #2

4 W2 Wiper RDAC #2, Addr = 01 2

5 DGND Digital Ground*

6 SHDN Terminal A open circuit. Shutdown controls Variable Resistors #1 and #2 7 CS Chip Select Input, Active Low. When CS returns high data in the serial input register is decoded based on the address bits and loaded into the target DAC register.

8 SDI Serial Data Input

9 CLK Serial Clock Input, positive edge triggered

RS Active low reset to midscale; sets RDAC registers to 80H

11 V DD Positive power supply, specified for operation

12 W1 Wiper RDAC #1, addr = 00

13 A1 Terminal A RDAC #1

14 B1 Terminal B RDAC #1

*All AGNDs must be connected to DGND. AD8403 PIN DESCRIPTIONS Pin Name Description

1 AGND2 Analog Ground #2*

5 AGND4 Analog Ground #4*

6 B4 Terminal B RDAC #4

7 A4 Terminal A RDAC #4

8 W4 Wiper RDAC #4, addr = 11

9 DGND Digital Ground*

SHDN Active Low Input. Terminal A open circuit. Shutdown controls variable resistors #1 through #4 11 CS Chip Select Input, Active Low. When CS returns high data in the serial input register is decoded based on the address bits and loaded into the target DAC register.

12 SDI Serial Data Input

13 SDO Serial Data Output, Open Drain transistor

14 CLK Serial Clock Input, positive edge triggered

RS Active low reset to midscale; sets RDAC registers to 80H

16 V DD Positive power supply, specified for

operation at both +3 V and +5 V

17 AGND3 Analog Ground #3*

18 W3 Wiper RDAC #3, addr = 10

19 A3 Terminal A RDAC #3

20 B3 Terminal B RDAC #3

21 AGND1 Analog Ground #1*

22 W1 Wiper RDAC #1, addr = 00

23 A1 Terminal A RDAC #1

24 B1 Terminal B RDAC #1

*All AGNDs must be connected to DGND.

and B are available with values of 1 kΩ , 10 kΩ , 50 kΩ and 100 kΩ . diagram of the equivalent RDAC circuit. RBA is the nominal end-to-end resistance.

10 MHz makes it possible to load all 4 VRs in under 4 µs (10 ×

shown in Figures 1a, 1b and 1c. tions when the device is taken out of shutdown. Figure 37. AD8402/AD8403 Equivalent VR (RDAC) Circuit

temperature has a positive 500 ppm/ °C temperature coefficient. proportional to the input voltage applied to a given terminal. Figure 38. Block Diagrams

REV. B –15– The ac characteristics of the RDACs are dominated by the inter- nal parasitic capacitances and the external capacitive loads. The –3 dB bandwidth of the AD8403AN10 (10 k Ω resistor) mea- sures 600 kHz at half scale as a potentiometer divider. Figure 23 provides the large signal BODE plot characteristics of the three available resistor versions 10 k Ω , 50 kΩ , and 100 kΩ . The gain flatness versus frequency graph, Figure 26, predicts filter appli- cations performance. A parasitic simulation model has been de- veloped, and is shown in Figure 42. Listing I provides a macro model net list for the 10 k Ω RDAC: Listing I. Macro Model Net List for RDAC .PARAM DW=255, RDAC=10E3 .SUBCKT DPOT (A,W,) RAW A W {(1-DW/256)*RDAC+50} CW W 0 120E-12 RBW W B {DW/256*RDAC+50} .ENDS DPOT The total harmonic distortion plus noise (THD+N) is measured at 0.003% in an inverting op amp circuit using an offset ground and a rail-to-rail OP279 amplifier, Figure 33. Thermal noise is primarily Johnson noise, typically 9 nV/ √ Hz for the 10 kΩ ver- sion at f = 1 kHz. For the 100 k Ω device, thermal noise becomes 29 nV/√Hz. Channel-to-channel crosstalk measures less than –65 dB at f = 100 kHz. To achieve this isolation, the extra ground pins provided on the package to segregate the individual RDACs must be connected to circuit ground. AGND and DGND pins should be at the same voltage potential. Any unused potentio- meters in a package should be connected to ground. Power sup- ply rejection is typically –35 dB at 10 kHz (care is needed to minimize power supply ripple in high accuracy applications). The digital potentiometer (RDAC) allows many of the applica- tions of trimming potentiometers to be replaced by a solid-state solution offering compact size, freedom from vibration, shock and open contact problems encountered in hostile environ- ments. A major advantage of the digital potentiometer is its programmability. Any settings can be saved for later recall in system memory. The two major configurations of the RDAC include the potentiometer divider (basic 3-terminal application) and the rheostat (2-terminal configuration) connections shown in Figures 29 and 30. Certain boundary conditions must be satisfied for proper AD8400/AD8402/AD8403 operation. First, all analog signals must remain within the 0 to V DD range used to operate the single-supply AD8400/AD8402/AD8403 products. For standard potentiometer divider applications, the wiper output can be used directly. For low resistance loads, buffer the wiper with a suitable rail-to-rail op amp such as the OP291 or the OP279. Second, for ac signals and bipolar dc adjustment applications, a virtual ground will generally be needed. Whatever method is used to create the virtual ground, the result must provide the necessary sink and source current for all connected loads, in- cluding adequate bypass capacitance. Figure 33 shows one channel of the AD8402 connected in an inverting program- mable gain amplifier circuit. The virtual ground is set at +2.5 V which allows the circuit output to span a ± 2.5 volt range with respect to virtual ground. The rail-to-rail amplifier capability is necessary for the widest output swing. As the wiper is adjusted from its midscale reset position (80 H) toward the A terminal (code FFH), the voltage gain of the circuit is increased in suc- cessfully larger increments. Alternatively, as the wiper is ad- justed toward the B terminal (code 00 H), the signal becomes attenuated. The plot in Figure 43 shows the wiper settings for a 100:1 range of voltage gain (V/V). Note the ± 10 dB of pseudo- logarithmic gain around 0 dB (1 V/V). This circuit is mainly useful for gain adjustments in the range of 0.14 V/V to 4 V/V; beyond this range the step sizes become very large and the resis- tance of the driving circuit can become a significant term in the gain equation. INVERTING GAIN – V/V 256 128 0.1 1.0 10 160 192 224DIGITAL CODE – Decimal Figure 43. Inverting Programmable Gain Plot

REV. B –17– OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 8-Pin Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35)SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° 14-Pin Plastic DIP Package (N-14) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.795 (20.19) 0.725 (18.42) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN PIN 1 0.280 (7.11) 0.240 (6.10) 814 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 14-Pin Narrow Body SOIC Package (SO-14) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) 0.0099 (0.25)x 45° PIN 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 14 8 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) 0.3444 (8.75) 0.3367 (8.55) 0.0098 (0.25) 0.0040 (0.10) 14-Lead TSSOP (RU-14) 14 8 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50)

–18– REV. B 24-Pin Narrow Body Plastic DIP Package (N-24) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.203) 0.195 (4.95) 0.115 (2.93) PIN 1 0.280 (7.11) 0.240 (6.10) 0.210 (5.33) MAX 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) SEATING PLANE 0.130 (3.30) MIN 1.275 (32.30) (0.38) MIN 0.160 (4.06) 0.115 (2.92) 24-Pin SOIC Package (SOL-24) 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45° PIN 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 121 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) BSC 0.1043 (2.65) 0.0926 (2.35) 0.6141 (15.60) 0.5985 (15.20) 0.0118 (0.30) 0.0040 (0.10) 24-Lead Thin Surface Mount TSSOP Package (RU-24) 24 13 121 0.311 (7.90) 0.303 (7.70) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50)

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PRINTED IN U.S.A. C1997b–12–1/97 –20–