AD8310ARMZ-REEL7

AD8310_05 AD | Alldatasheet

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Fast, Voltage-Out DC–440 MHz, 95 dB Logarithmic Amplifier AD8310 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

FEATURES

Multistage demodulating logarithmic amplifier Voltage output, rise time <15 ns High current capacity: 25 mA into grounded RL 95 dB dynamic range: −91 dBV to +4 dBV Single supply of 2.7 V min at 8 mA typ DC–440 MHz operation, ±0.4 dB linearity Slope of +24 mV/dB, intercept of −108 dBV Highly stable scaling over temperature Fully differential dc-coupled signal path 100 ns power-up time, 1 mA sleep current

APPLICATIONS

Conversion of signal level to decibel form Transmitter antenna power measurement Receiver signal strength indication (RSSI) Low cost radar and sonar signal processing Network and spectrum analyzers Signal-level determination down to 20 Hz True-decibel ac mode for multimeters GENERAL DESCRIPTION The AD8310 is a complete, dc−440 MHz demodulating logarithmic amplifier (log amp) with a very fast voltage mode output, capable of driving up to 25 mA into a grounded load in under 15 ns. It uses the progressive compression (successive detection) technique to provide a dynamic range of up to 95 dB to ±3 dB law conformance or 90 dB to a ±1 dB error bound up to 100 MHz. It is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 8 mA is needed, corresponding to a power consumption of only 24 mW at 3 V . A fast-acting CMOS- compatible enable pin is provided. Each of the six cascaded amplifier/limiter cells has a small- signal gain of 14.3 dB, with a −3 dB bandwidth of 900 MHz. A total of nine detector cells are used to provide a dynamic range that extends from −91 dBV (where 0 dBV is defined as the amplitude of a 1 V rms sine wave), an amplitude of about ±40 μV , up to +4 dBV (or ±2.2 V). The demodulated output is accurately scaled, with a log slope of 24 mV/dB and an intercept of −108 dBV . The scaling parameters are supply- and temperature-independent. FUNCTIONAL BLOCK DIAGRAM VPOS INHI INLO COMM 8mA 1.0kΩ BAND GAP REFERENCE AND BIASING SIX 14.3dB 900MHz AMPLIFIER STAGES NINE DETECTOR CELLS SPACED 14.3dB INPUT-OFFSET COMPENSATION LOOP 2μA /dB MIRROR 3kΩ 3kΩ 1kΩCOMM COMM COMM ENBL BFIN VOUT OFLT ENABLE BUFFER INPUT OUTPUT OFFSET FILTER AD8310 SUPPLY +INPUT –INPUT COMMON 33pF 01084-001 Figure 1. The fully differential input offers a moderately high impedance (1 kΩ in parallel with about 1 pF). A simple network can match the input to 50 Ω and provide a power sensitivity of −78 dBm to +17 dBm. The logarithmic linearity is typically within ±0.4 dB up to 100 MHz over the central portion of the range, but it is somewhat greater at 440 MHz. There is no minimum frequency limit; the AD8310 can be used down to low audio frequencies. Special filtering features are provided to support this wide range. The output voltage runs from a noise-limited lower boundary of 400 mV to an upper limit within 200 mV of the supply voltage for light loads. The slope and intercept can be readily altered using external resistors. The output is tolerant of a wide variety of load conditions and is stable with capacitive loads of 100 pF. The AD8310 provides a unique combination of low cost, small size, low power consumption, high accuracy and stability, high dynamic range, a frequency range encompassing audio to UHF, fast response time, and good load-driving capabilities, making this product useful in numerous applications that require the reduction of a signal to its decibel equivalent. The AD8310 is available in the industrial temperature range of −40°C to +85°C in an 8-lead MSOP package.

Rev. E | Page 2 of 24 TABLE OF CONTENTS Lowering the High-Pass Corner Frequency of the Offset

REVISION HISTORY

6/05—Rev. D to Rev. E 10/04—Rev. C to Rev. D 7/03—Rev. B to Rev. C 2/03—Rev. A to Rev. B 1/00—Rev. 0 to Rev. A 10/99—Revision 0: Initial Version

Rev. E | Page 3 of 24 SPECIFICATIONS TA = 25°C, VS = 5 V , unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INPUT STAGE Inputs INHI, INLO Maximum Input1 Single-ended, p-p ±2.0 ±2.2 V 4 dBV Equivalent Power in 50 Ω Termination resistor of 52.3 Ω 17 dBm Differential drive, p-p 20 dBm Noise Floor Terminated 50 Ω source 1.28 nV/√Hz Equivalent Power in 50 Ω 440 MHz bandwidth −78 dBm Input Resistance From INHI to INLO 800 1000 1200 Ω Input Capacitance From INHI to INLO 1.4 pF DC Bias Voltage Either input 3.2 V LOGARITHMIC AMPLIFIER Output VOUT ±3 dB Error Dynamic Range From noise floor to maximum input 95 dB Transfer Slope 10 MHz ≤ f ≤ 200 MHz 22 24 26 mV/dB Overtemperature, –40°C < TA < +85°C 20 26 mV/dB Intercept (Log Offset)2 10 MHz ≤ f ≤ 200 MHz −115 −108 −99 dBV Equivalent dBm (re 50 Ω) −102 −95 −86 dBm Overtemperature, −40°C ≤ TA ≤ +85°C −120 −96 dBV Equivalent dBm (re 50 Ω) −107 −83 dBm Temperature sensitivity −0.04 dB/°C Linearity Error (Ripple) Input from –88 dBV (–75 dBm) to +2 dBV (+15 dBm) ±0.4 dB Output Voltage Input = –91 dBV (–78 dBm) 0.4 V Input = 9 dBV (22 dBm) 2.6 V Minimum Load Resistance, RL 100 Ω Maximum Sink Current 0.5 mA Output Resistance 0.05 Ω Video Bandwidth 25 MHz Rise Time (10% to 90%) Input Level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 15 ns Input Level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 20 ns Fall Time (90% to 10%) Input Level = −43 dBV (−30 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 30 ns Input Level = −3 dBV (+10 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 40 ns Output Settling Time to 1% Input Level = −13 dBV (0 dBm), RL ≥ 402 Ω, CL ≤ 68 pF 40 ns POWER INTERFACES Supply Voltage, VPOS 2.7 5.5 V Quiescent Current Zero-signal 6.5 8.0 9.5 mA Overtemperature −40°C < TA < +85°C 5.5 8.5 10 mA Disable Current 0.05 μA Logic Level to Enable Power High condition, −40°C < TA < +85°C 2.3 V Input Current when High 3 V at ENBL 35 μA Logic Level to Disable Power Low condition, −40°C < TA < +85°C 0.8 V 1 The input level is specified in dBV, because logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of 1 V rms. A power level of 0 dBm (1 mW) in a 50 Ω termination corresponds to an input of 0.2236 V rms. Therefore, the relationship between dBV and dBm is a fixed offset of 13 dBm in the special case of a 50 Ω termination. 2 Guaranteed but not tested; limits are specified at six sigma levels.

Rev. E | Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Value Supply Voltage, VS 7.5 V Input Power (re 50 Ω), Single-Ended 18 dBm Differential Drive 22 dBm Internal Power Dissipation 200 mW θJA 200°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electros tatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge wi thout detection. Although this product features proprietary ESD protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 2. Pin Configuration Table 3. Pin Function Descriptions 1 INLO One of Two Balanced Inputs. Biased roughly to VPOS/2. 2 COMM Common Pin. Usually grounded. 3 OFLT Offset Filter Access. Nominally at about 1.75 V. 4 VOUT Low Impedance Output Voltage. Carries a 25 mA maximum load. 5 VPOS Positive Supply. 2.7 V to 5.5 V at 8 mA quiescent current. 6 BFIN Buffer Input. Used to lower post-detection bandwidth. 7 ENBL CMOS Compatible Chip Enable. Active when high. 8 INHI Second of Two Balanced Inputs.

Figure 3. RSSI Output vs. Input Level, 100 MHz Sine Input at TA = −40°C, Figure 4. RSSI Output vs. Input Level at TA = 25°C Figure 5. RSSI Output vs. Input Level at TA = 25°C Figure 6. Log Linearity of RSSI Output vs. Input Level,

100 MHz Sine Input at TA = −40°C, +25°C, and +85°C

Figure 7. Log Linearity of RSSI Output vs. Input Level, Figure 8. Log Linearity of RSSI Output vs. Input Level at TA = 25°C

complete discussion of the theory, see the AD8307 data sheet. base ten, in which case VY is also the volts-per-decade. VX is the intercept voltage. Figure 21. General Form of the Logarithmic Function AD8310, operating in RF applications with a sine wave input. 50 Ω, a level of 0 dBm. Note that the quantity (PIN – PO) is dB. sheet when specifying the performance of the AD8310. dc-coupled, operation at very low frequencies is possible.

Rev. E | Page 10 of 24 SLOPE AND INTERCEPT CALIBRATION All monolithic log amps from Analog Devices use precision design techniques to control the logarithmic slope and intercept. The primary source of this calibration is a pair of accurate voltage references that provide supply- and temperature-independent scaling. The slope is set to 24 mV/dB by the bias chosen for the detector cells and the subsequent gain of the postdetector output interface. With this slope, the full 95 dB dynamic range can be easily accommodated within the output swing capacity, when operating from a 2.7 V supply. Intercept positioning at −108 dBV (−95 dBm re 50 Ω) has likewise been chosen to provide an output centered in the available voltage range. Precise control of the slope and intercept results in a log amp with stable scaling parameters, making it a true measurement device as, for example, a calibrated received signal strength indicator (RSSI). In this application, the input waveform is invariably sinusoidal. The input level is correctly specified in dBV . It can alternatively be stated as an equivalent power, in dBm, but in this case, it is necessary to specify the impedance in which this power is presumed to be measured. In RF practice, it is common to assume a reference impedance of 50 Ω, in which 0 dBm (1 mW) corresponds to a sinusoidal amplitude of 316.2 mV (223.6 mV rms). However, the power metric is correct only when the input impedance is lowered to 50 Ω, either by a termination resistor added across INHI and INLO, or by the use of a narrow-band matching network. Note that log amps do not inherently respond to power, but to the voltage applied to their input. The AD8310 presents a nominal input impedance much higher than 50 Ω (typically 1 kΩ at low frequencies). A simple input matching network can considerably improve the power sensitivity of this type of log amp. This increases the voltage applied to the input and, therefore, alters the intercept. For a 50 Ω reactive match, the voltage gain is about 4.8, and the whole dynamic range moves down by 13.6 dB. The effective intercept is a function of wave- form. For example, a square-wave input reads 6 dB higher than a sine wave of the same amplitude, and a Gaussian noise input reads 0.5 dB higher than a sine wave of the same rms value. OFFSET CONTROL In a monolithic log amp, direct coupling is used between the stages for several reasons. First, it avoids the need for coupling capacitors, which typically have a chip area at least as large as that of a basic gain cell, considerably increasing die size. Second, the capacitor values predetermine the lowest frequency at which the log amp can operate. For moderate values, this can be as high as 30 MHz, limiting the application range. Third, the parasitic back-plate capacitance lowers the bandwidth of the cell, further limiting the scope of applications. However, the very high dc gain of a direct-coupled amplifier raises a practical issue. An offset voltage in the early stages of the chain is indistinguishable from a real signal. If it were as high as 400 μV , it would be 18 dB larger than the smallest ac signal (50 μV), potentially reducing the dynamic range by this amount. This problem can be averted by using a global feedback path from the last stage to the first, which corrects this offset in a similar fashion to the dc negative feedback applied around an op amp. The high frequency components of the feedback signal must, of course, be removed to prevent a reduction of the HF gain in the forward path. An on-chip filter capacitor of 33 pF provides sufficient suppres- sion of HF feedback to allow operation above 1 MHz. The −3 dB point in the high-pass response is at 2 MHz, but the usable range extends well below this frequency. To further lower the frequency range, an external capacitor can be added at OFLT (Pin 3). For example, 300 pF lowers it by a factor of 10. Operation at low audio frequencies requires a capacitor of about 1 μF. Note that this filter has no effect for input levels well above the offset voltage, where the frequency range would extend down to dc (for a signal applied directly to the input pins). The dc offset can optionally be nulled by adjusting the voltage on the OFLT pin (see the Applications section).

Rev. E | Page 13 of 24 For zero-signal conditions, all the detector output currents are equal. For a finite input of either polarity, their difference is converted by the output interface to a single-sided unipolar current, nominally scaled 2 μA/dB (40 μA/decade), at the output pin BFIN. An on-chip resistor of ~3 kΩ, R1, converts this current to a voltage of 6 mV/dB. This is then amplified by a factor of 4 in the output buffer, which can drive a current of up to 25 mA in a grounded load resistor. The overall rise time of the AD8310 is less than 15 ns. There is also a delay time of about 6 ns when the log amp is driven by an RF burst, starting at zero amplitude. When driving capacitive loads, it is desirable to add a low value of load resistor to speed up the return to the baseline; the buffer is stable for loads of a least 100 pF. The output bandwidth can be lowered by adding a grounded capacitor at BFIN. The time- constant of the resulting single-pole filter is formed with the 3 kΩ internal load resistor (with a tolerance of 20%). Therefore, to set the –3 dB frequency to 20 kHz, use a capacitor of 2.7 nF. Using 2.7 μF, the filter corner is at 20 Hz.

Figure 30. Log Conformance Errors vs. Input Level at 10 MHz,

50 MHz, and 100 MHz

change in the RSSI output voltage for a 1 dB change at the input. range is approximately 95 dB (from +4 dBV to −91 dBV). response would intersect the horizontal axis (see Figure 29). VOUT is the demodulated and filtered RSSI output. VSLOPE is the logarithmic slope expressed in V/dB. level (either dBm or dBV in this case). converted to dBm re 50 Ω by adding 13 dB. Table 4. Correction for Signals with Differing Crest Factors 1Add to the measured input level. balances the drive amplitude to INLO and INHI. The choice of turns ratio depends somewhat on the frequency. small contribution from the input noise current.

Table 6. Evaluation Boards Setup Options can be used to isolate the generator ground from the evaluation board ground. See Figure 28. matching capacitors to form an input matching network. See the Input Matching section for details. capacitor in C5. An inductor or small resistor can be placed in R5 for additional decoupling. placed in R6 to give the circuit a back-terminated output impedance. W1 and W2 are used to connect or disconnect the loads. loop in low frequency applications.

0.65 BSC

1.10 MAX

Figure 43. 8-Lead Mini Small Outline Package [MSOP]

Rev. E | Page 23 of 24 NOTES

Rev. E | Page 24 of 24 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. C01084–0–6/05(E)