AD8307ARZ-RL7

AD8307_V01 AD | Alldatasheet

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Low Cost, DC to 500 MHz, 92 dB Logarithmic Amplifier Data Sheet AD8307 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©1997–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Complete multistage logarithmic amplifier 92 dB dynamic range: −75 dBm to +17 dBm to −90 dBm using matching network Single supply of 2.7 V minimum at 7.5 mA typical DC to 500 MHz operation, ±1 dB linearity Slope of 25 mV/dB, intercept of −84 dBm Highly stable scaling over temperature Fully differential dc-coupled signal path 100 ns power-up time, 150 μA sleep current

APPLICATIONS

Conversion of signal level to decibel form Transmitter antenna power measurement Receiver signal strength indication (RSSI) Low cost radar and sonar signal processing Network and spectrum analyzers (to 120 dB) Signal level determination down to 20 Hz True decibel ac mode for multimeters FUNCTIONAL BLOCK DIAGRAM BAND GAP REFERENCE AND BIASING SIX 14.3dB 900MHz AMPLIFIER STAGES MIRROR INPUT-OFFSET COMPENSATION LOOP COM INM INP ENBVPS INT OUT OFS AD8307 7.5mA 1.1kΩ 2µA /dB 12.5kΩ COM NINE DETECTOR CELLS SPACED 14.3dB –INP +INP 01082-001 Figure 1. GENERAL DESCRIPTION The AD8307 is the first logarithmic amplifier made available in an 8-lead SOIC_N package. It is a complete 500 MHz monolithic demodulating logarithmic amplifier based on the progressive compression (successive detection) technique, providing a dynamic range of 92 dB to ±3 dB law conformance and 88 dB to a tight ±1 dB error bound at all frequencies up to 100 MHz. The AD8307 is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 7.5 mA is needed. A fast acting CMOS- compatible control pin can disable the AD8307 to a standby current of 150 μA. The AD8307 operates over the industrial temperature range of −40°C to +85°C and is available in an 8-lead SOIC package and an 8-lead PDIP . Table 1. Next Generation Upgrades for the AD8307

Rev. F | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

12/2019—Rev. E to Rev. F 9/2015—Rev. D to Rev. E 7/2008—Rev. C to Rev. D 10/2006—Rev. B to Rev. C 6/2003—Rev. A to Rev. B

Rev. F | Page 3 of 24 SPECIFICATIONS VS = 5 V , TA = 25°C, RL ≥ 1 MΩ, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit GENERAL CHARACTERISTICS Input Range (±3 dB Error) From noise floor to maximum input 92 dB Input Range (±1 dB Error) From noise floor to maximum input 88 dB Logarithmic Conformance f ≤ 100 MHz, central 80 dB ±0.3 ±1 dB f = 500 MHz, central 75 dB ±0.5 dB Logarithmic Slope Unadjusted1 23 25 27 mV/dB vs. Temperature 23 27 mV/dB Logarithmic Intercept Sine amplitude, unadjusted2 20 μV Equivalent sine power in 50 Ω −87 −84 −77 dBm vs. Temperature −88 −76 dBm Input Noise Spectral Density Inp uts shorted 1.5 nV/√Hz Operating Noise Floor RSOURCE = 50 Ω/2 −78 dBm Output Resistance Pin 4 to ground 10 12.5 15 kΩ Internal Load Capacitance 3.5 pF Response Time Small signal, 10% to 90%, 0 mV to 100 mV, CL = 2 pF 400 ns Large signal, 10% to 90%, 0 V to 2.4 V, CL = 2 pF 500 ns Upper Usable Frequency 500 MHz Lower Usable Frequency AC-coupled input 10 Hz AMPLIFIER CELL CHARACTERISTICS Cell Bandwidth −3 dB 900 MHz Cell Gain 14.3 dB INPUT CHARACTERISTICS DC Common-Mode Voltage AC-coupled input 3.2 V Common-Mode Range Either input (small signal) −0.3 +1.6 V S − 1 V DC Input Offset Voltage3 RSOURCE ≤ 50 Ω 50 500 μV Drift 0.8 μV/°C Incremental Input Resistance Differential 1.1 kΩ Input Capacitance Either pin to ground 1.4 pF Bias Current Either input 10 25 μA POWER INTERFACES Supply Voltage 2.7 5.5 V Supply Current VENB ≥ 2 V 8 10 mA Disabled VENB ≤ 1 V 150 750 μA 1 This can be adjusted downward by adding a shunt resistor from the output to ground. A 50 kΩ resistor reduces the nominal slope to 20 mV/dB. 2 This can be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V. 3 Normally nulled automatically by internal offset correction loop and can be manually nulled by a voltage applied between Pin 3 and ground; see the Applications Information section.

Rev. F | Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Ratings Supply 7.5 V Input Voltage (Pin 1 and Pin 8) VSUPPLY Storage Temperature Range (N, R) −65°C to +125°C Ambient Temperature Range, Rated Performance Industrial, AD8307AN, AD8307AR −40°C to +85°C Lead Temperature Range (Soldering, 10 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION

Figure 2. Pin Configuration Table 4. Pin Function Descriptions 1 INM Signal Input Minus Polarity. Normally at V POS/2. 2 COM Common Pin (Usually Grounded). 3 OFS Offset Adjustment. External capacitor connection. 4 OUT Logarithmic (RSSI) Output Voltage. R OUT = 12.5 kΩ. 6 ENB CMOS-Compatible Chip Enable. Active when high. 7 VPS Positive Supply: 2.7 V to 5.5 V. significance to the sign of the two input pins. DC resistance from INP to INM = 1.1 kΩ.

designed log amp has rational scaling parameters. transition points on the output function (consider Figure 24). approximation below the lin-log transition (labeled 1 in Figure 24). represents the extrapolated, rather than actual, intercept. applications because they do not demodulate their input signal. made using a different type of amplifier stage, called an A/0 cell. output in recovering the signal in FM and PM modes. Figure 25. A/0 Amplifier Functions (Ideal and Tanh) mic intermediate frequency (IF) amplifier all use this technique. voltage of EK = 2 kT/q and a small signal gain of A = IERL/EK. output. This scheme is depicted in single-sided form in Figure 26.

Figure 26. Log Amp Using A/0 Stages and Auxiliary Summing Cells practice followed in all subsequent Analog Devices types. each detector is almost constant over each period of the input. this power is presumed to be measured. positioned at −84 dBm, corresponding to a sine amplitude of 20 μV . power, but to the voltage applied to their input. input 0.5 dB higher than a sine wave of the same rms value.

Rev. F | Page 13 of 24 In the AD8307, this is achieved by an on-chip filter, providing sufficient suppression of HF feedback to allow operation above 1 MHz. To extend the range below this frequency, an external capacitor can be added. This permits the high-pass corner to be lowered to audio frequencies using a capacitor of modest value. Note that this capacitor has no effect on the minimum signal frequency for input levels above the offset voltage; this extends down to dc (for a signal applied directly to the input pins). The offset voltage varies from part to part; some exhibit essentially stable offsets of under 100 μV without the benefit of an offset adjustment. EXTENSION OF RANGE The theoretical dynamic range for the basic log amp shown in Figure 26 is A N. For A = 5.2 (14.3 dB) and N = 6, it is 20,000 or 86 dB. The actual lower end of the dynamic range is largely determined by the thermal noise floor, measured at the input of the chain of amplifiers. The upper end of the range is extended upward by the addition of top-end detectors. The input signal is applied to a tapped attenuator, and progressively smaller signals are applied to three passive rectifying g m cells whose outputs are summed with those of the main detectors. With care in design, the extension to the dynamic range can be seamless over the full frequency range. For the AD8307, it amounts to a further 27 dB. Therefore, the total dynamic range is theoretically 113 dB. The specified range of 90 dB (−74 dBm to +16 dBm) is for high accuracy and calibrated operation, and includes the low end degradation due to thermal noise and the top end reduction due to voltage limitations. The additional stages are not redundant, but are needed to maintain accurate logarithmic conformance over the central region of the dynamic range, and in extending the usable range considerably beyond the specified range. In applications where log conformance is less demanding, the AD8307 can provide over 95 dB of range.

the overall gain is 86 dB with a −3 dB bandwidth of 500 MHz. noise spectral density (1.5 nV/√Hz). current to the signal current. Figure 27. Main Features of the AD8307 path, the stability of the offset correction loop is assured. numbering in each of these interface diagrams is local.

1 V , the AD8307 is disabled and consumes a sleep current of

input or the settling of the offset control loop. Figure 28. Enable Interface Figure 29. Signal Input Interface

until it has become much less than the signal. to either Pin 1 or Pin 8, with the other pin ac-coupled to ground. operate at ground potential. most positive value, the input-referred offset is reversed to −1.6 mV . is then automatically nulled by the action of the feedback loop. in a closed-loop high-pass corner at about 1.5 MHz. Figure 30. Offset Interface and Offset Nulling Path nulling loop; the AD8307 differs in using this single-sided form. are summed at the LGP node and the LGM node in Figure 31. the log intercept. These scaling parameters can be adjusted. current nominally scaled 2 μA/dB (40 μA/decade) at the OUT pin. a low-pass filter pole with a corner frequency of about 5 MHz. applications, and is typically made equal to CFLT.

Figure 31. Simplified Output Interface

1 GHz, at which frequency the gain of the main path is still over

resistance to the ground plane. Figure 32. Basic Connections effect of the basic 1.1 kΩ input resistance (RIN) of the AD8307.

10 MHz, 100 MHz, and 500 MHz; Figure 34 shows the typical

termination resistor is omitted, the input power is negligible. considered carefully in connection with the AD8307. Figure 33. Log Response at 10 MHz, 100 MHz, and 500 MHz Figure 34. Logarithmic Law Conformance at 10 MHz, 100 MHz, and 500 MHz

shown in Figure 37 can be used, either singly or in combination. signal varies from −47.5 dBm to −32.5 dBm. Figure 37. Slope and Intercept Adjustments

±10% slope adjustment; VR2 provides a ±3 dB intercept range. a supply of at least this amount is needed for the op amp. Figure 38. Log Amp with Buffered Output reverse termination, which halves the slope to 12.5 mV/dB.

20 Hz, it is useful to employ the buffer amplifier as a multipole

rapid response time to changes in signal level. Figure 39. Cable Driving Log Amp applications; 12 V is recommended. Figure 40. Log Amp with Four-Pole Low-Pass Filter signal range at its input, doubling as a ±4 dB intercept adjustment.

0.50 WITH FILTER

Figure 43. Results for 120 dB Measurement System input range is now 0.5 mV to 20 V (sine amplitude). in Figure 44, the output time constant is 125 ms. C4 to the offset compensation loop. Figure 44. Connections for Low Frequency Operation

Rev. F | Page 24 of 24 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD8307ANZ −40°C to +85°C 8-Lead PDIP N-8 AD8307ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD8307ARZ-REEL −40°C to +85°C 8-Lead SOIC_N 13" Tape and Reel R-8 AD8307ARZ-RL7 −40°C to +85°C 8-Lead SOIC_N 7" Tape and Reel R-8 1 Z = RoHS Compliant Part. ©1997–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D01082-0-12/19(F)