AD8306

AD8306 Data Sheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD8306 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999

5 MHz–400 MHz 100 dB High Precision

Limiting-Logarithmic Amplifier FUNCTIONAL BLOCK DIAGRAMFEATURES Complete, Fully Calibrated Log-Limiting IF Amplifier 100 dB Dynamic Range: –91 dBV to +9 dBV Stable RSSI Scaling Over Temperature and Supplies: 20 mV/dB Slope, –95 dBm Intercept 60.4 dB RSSI Linearity up to 200 MHz Programmable Limiter Gain and Output Current Differential Outputs to 10 mA, 2.4 V p-p Overall Gain 90 dB, Bandwidth 400 MHz Constant Phase (Typical 656 ps Delay Skew) Single Supply of +2.7 V to +6.5 V at 16 mA Typical Fully Differential Inputs, R IN = 1 k V, CIN = 2.5 pF 500 ns Power-Up Time, <1 mA Sleep Current

APPLICATIONS

Receivers for Frequency and Phase Modulation Very Wide Range IF and RF Power Measurement Receiver Signal Strength Indication (RSSI) Low Cost Radar and Sonar Signal Processing Instrumentation: Network and Spectrum Analyzers PRODUCT DESCRIPTION The AD8306 is a complete IF limiting amplifier, providing both an accurate logarithmic (decibel) measure of the input signal (the RSSI function) over a dynamic range of 100 dB, and a programmable limiter output, useful from 5 MHz to 400 MHz. It is easy to use, requiring few external components. A single supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre- sponding to a power consumption of under 50 mW at 3 V, plus the limiter bias current, determined by the application and typi- cally 2 mA, providing a limiter gain of 90 dB when using 200 W loads. A CMOS-compatible control interface can enable the AD8306 within about 500 ns and disable it to a standby current of under 1 mA. The six cascaded amplifier/limiter cells in the main path have a small signal gain of 12.04 dB ( ·4), with a –3 dB bandwidth of 850 MHz, providing a total gain of 72 dB. The programmable output stage provides a further 18 dB of gain. The input is fully differential and presents a moderately high impedance (1 k W in parallel with 2.5 pF). The input-referred noise-spectral-density, when driven from a terminated 50 W , source is 1.28 nV/ ÖHz, equivalent to a noise figure of 3 dB. The sensitivity of the AD8306 can be raised by using an input matching network. Each of the main gain cells includes a full-wave detector. An additional four detectors, driven by a broadband attenuator, are used to extend the top end of the dynamic range by over 48 dB. The overall dynamic range for this combination extends from –91 dBV (–78 dBm at the 50 W level) to a maximum permissible value of +9 dBV, using a balanced drive of antiphase inputs each of

2 V in amplitude, which would correspond to a sine wave power

of +22 dBm if the differential input were terminated in 50 W . Through laser trimming, the slope of the RSSI output is closely controlled to 20 mV/dB, while the intercept is set to –108 dBV (–95 dBm re 50 W ). These scaling parameters are determined by a band-gap voltage reference and are substantially indepen- dent of temperature and supply. The logarithmic law conform- ance is typically within – 0.4 dB over the central 80 dB of this range at any frequency between 10 MHz and 200 MHz, and is degraded only slightly at 400 MHz. The RSSI response time is nominally 73 ns (10%–90%). The averaging time may be increased without limit by the addition of an external capacitor. The full output of 2.34 V at the maximum input of +9 dBV can drive any resistive load down to 50 W and this interface remains stable with any value of capacitance on the output. The AD8306 is fabricated on an advanced complementary bipolar process using silicon-on-insulator isolation techniques and is available in the industrial temperature range of –40 °C to +85°C, in a 16-lead narrow body SO package. The AD8306 is also available for the full military temperature range of –55 °C to +125°C, in a 16-lead side-brazed ceramic DIP. 12dB LIM DET 12dB DET DET4 3 DET LADR ATTEN INHI INLO I–V BIAS CTRL TEN DETECTORS SPACED 12dB INTERCEPT TEMP COMP BAND-GAP REFERENCEENBL GAIN BIAS LMHI LMLO LMDR VLOG FLTR SIX STAGES TOTAL GAIN 72dB TYP GAIN 18dB SLOPE BIAS 12dB

REV. A–2– AD8306–SPECIFICATIONS Parameter Conditions Min 1 Typ Max 1 Units INPUT STAGE (Inputs INHI, INLO) Maximum Input2 Differential Drive, p-p – 3.5 – 4V +9 dBV Equivalent Power in 50 W Terminated in 52.3 W iRIN +22 dBm Noise Floor Terminated 50 W Source 1.28 nV/ ÖHz Equivalent Power in 50 W 400 MHz Bandwidth –78 dBm Input Resistance From INHI to INLO 800 1000 1200 W Input Capacitance From INHI to INLO 2.5 pF DC Bias Voltage Either Input 1.725 V LIMITING AMPLIFIER (Outputs LMHI, LMLO) Usable Frequency Range 5 400 MHz At Limiter Output R LOAD = RLIM = 50 W , to –10 dB Point 585 MHz Phase Variation at 100 MHz Over Input Range –73 dBV to –3 dBV – 2 Degrees Limiter Output Current Nominally 400 mV/R LIM 011 0 m A Versus Temperature –40 °C £ TA £ +85°C –0.008 %/ °C Input Range3 –78 +9 dBV Maximum Output Voltage At Either LMHI or LMLO, wrt VPS2 1 1.25 V Rise/Fall Time (10%–90%) R LOAD = 50 W , 40 W £ RLIM £ 400 W 0.6 ns LOGARITHMIC AMPLIFIER (Output VLOG) – 3 dB Error Dynamic Range From Noise Floor to Maximum Input 100 dB Transfer Slope4 f = 10 MHz 19.5 20 20.5 mV/dB f = 100 MHz 19.6 mV/dB Over Temperature –40 °C < TA < +85°C 19.3 20 20.7 mV/dB Intercept (Log Offset) 4 f = 10 MHz –109.5 –108 –106.5 dBV f = 100 MHz –108.4 dBV Over Temperature –40 °C £ TA £ +85°C –111 –108 –105 dBV Temperature Sensitivity –0.009 dB/ °C Linearity Error (Ripple) Input from –80 dBV to +0 dBV – 0.4 dB Output Voltage Input = –91 dBV, V S = +5 V, +2.7 V 0.34 V Input = +9 dBV, VS = +5 V 2.34 2.75 V Input = –3 dBV, VS = +3 V 2.10 V Minimum Load Resistance, R L 40 50 W Maximum Sink Current To Ground 0.75 1.0 1.25 mA Output Resistance 0.3 W Small-Signal Bandwidth 3.5 MHz Output Settling Time to 2% Large Scale Input, +3 dBV, R L ‡␣ 50 W , CL £␣ 100 pF 120 220 ns Rise/Fall Time (10%–90%) Large Scale Input, +3 dBV, R L ‡␣ 50 W , CL £␣ 100 pF 73 100 ns POWER INTERFACES Supply Voltage, VS 2.7 5 6.5 V Quiescent Current Zero-Signal, LMDR Open 13 16 20 mA Over Temperature –40 °C < TA < +85°C 1 11 62 3 m A Disable Current –40 °C < TA < +85°C 0.01 4 mA Additional Bias for Limiter R LIM = 400 W (See Text) 2.0 2.25 mA Logic Level to Enable Power HI Condition, –40 °C < TA < +85°C 2.7 V S V Input Current when HI 3 V at ENBL, –40 °C < TA < +85°C4 0 6 0 mA Logic Level to Disable Power LO Condition, –40 °C < TA < +85°C –0.5 1 V TRANSISTOR COUNT # of Transistors 207 207 NOTES 1Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 2The input level is specified in “dBV” since logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of 1 V rms. A power level of 0 dBm (1 mW) in a 50 W termination corresponds to an input of 0.2236 V rms. Hence, in the special case of 50 W termination, dBV values can be converted into dBm by adding a fixed offset of +13 to the dBV rms value. 3Due to the extremely high Gain Bandwidth Product of the AD8306, the output of either LMHI or LMLO will be unstable for levels below –78 dBV (–65 dBm, re 50 W ). 4Standard deviation remains essentially constant over frequency. See Figures 13, 14, 16 and 17. Specifications subject to change without notice. (VS = +5 V, TA = +258C, f = 10 MHz, unless otherwise noted)

REV. A AD8306 –3– ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE Temperature Package Package Model Range Description Options AD8306AR –40 °C to +85°C 16-Lead Narrow Body SO SO-16 AD8306AR-REEL –40 °C to +85°C 13" Tape and Reel SO-16 AD8306AR-REEL7 –40 °C to +85°C 7" Tape and Reel SO-16 AD8306ACHIPS –40 °C to +85°CD i e 5962-9864601QEA –55 °C to +125°C 16-Lead Side-Brazed Ceramic DIP D-16 AD8306-EVAL Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8306 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATION TOP VIEW (Not to Scale) COM2 VLOG AD8306 VPS1 PADL INHI INLO PADL COM1 ENBL VPS2 PADL LMHI LMLO PADL FLTR LMDR PIN FUNCTION DESCRIPTIONS Pin Name Function 1 COM2 Special Common Pin for RSSI Output.

2 VPS1 Supply Pin for First Five Amplifier Stages

and the Main Biasing System. 3, 6, 11, 14 PADL Four Tie-Downs to the Paddle on which the IC Is Mounted; Grounded. 4 INHI Signal Input, HI or Plus Polarity. 5 INLO Signal Input, LO or Minus Polarity. 7 COM1 Main Common Connection. 8 ENBL Chip Enable; Active When HI. 9 LMDR Limiter Drive Programming Pin. 10 FLTR RSSI Bandwidth-Reduction Pin. 12 LMLO Limiter Output, LO or Minus Polarity. 13 LMHI Limiter Output, HI or Plus Polarity.

15 VPS2 Supply Pin for Sixth Gain Stage, Limiter

and RSSI Output Stage Load Current. 16 VLOG Logarithmic (RSSI) Output. Storage Temperature Range –65°C to +150°C Lead Temperature Range (Soldering 60 sec) +300°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

Figure 7. RSSI Output vs. Input Level, 100 MHz Sine In- Figure 8. RSSI Output vs. Input Level, at T A = +25°C, for Figure 9. RSSI Output vs. Input Level, at T A = +25°C, for Figure 10. Log Linearity of RSSI Output vs. Input Level,

100 MHz Sine Input, at T A = –40°C, +25°C, and +85°C

Figure 11. Log Linearity of RSSI Output vs. Input Level, at Figure 12. Log Linearity of RSSI Output vs. Input Level,

400 MHz

12.04 dB (·4) and small-signal –3 dB bandwidth of 850 MHz. pin-to-pin output is used. The overall voltage gain is thus 90 dB. is accurately (400 mV)/R LIM. Figure 19. Main Features of the AD8306 the input, ensuring accurate response down to the noise floor. spectral-density of 1.07 nV/ ÖHz. further information on the use of this interface). compatible level at ENBL (Pin 8).

ESD protection; these may be neither accurate nor stable. tied to the supply, or any voltage above 2 V, it will be fully enabled. supply current to fall below 10 mA. Figure 20. Enable Interface come much less than the signal.

1 THRU 5

Figure 21. Signal Input Interface perature, by –6 dB over a 120 °C range. times of typically 0.6 ns, when load resistors of 50 W are used. supply voltage applied to VPS2 (Pin 15). LIM and strapping LMHI and LMLO to VPS2. Figure 22. Limiter Output Interface

Figure 27. Basic Connections for Operating the Limiter coupled node on the PC board (see layout of evaluation board). in instabilities caused by the very high gain of the signal path. LIM is reduced (recommended value is 400 W ).

50 W to 50 MHz for RLOAD = RLIM = 400 W (bandwidth =

210 MHz for RLOAD = RLIM = 100 W and 100 MHz for RLOAD =

the primary input will be lowered to –121 dBV (–108 dBm). transformer is useful whenever broadband coupling is required. network, as shown in Figure 28, which has several advantages. lar when the impedance ratio is fairly high (i.e., 50 W to 1000 W ). Figure 28. High Frequency Input Matching Network Figure 29 shows the response for a center frequency of 100 MHz. Figure 29. Response of 100 MHz Matching Network

method can be used to calculate the basic matching parameters. when CIN = 2.5 pF. For example, at fC = 100 MHz, LIN = 1 mH. Figure 30. Altering the Logarithmic Slope

REV. A AD8306 –13– 10 mV/dB The AD8031 rail-to-rail op amp, used in both ex- amples, can swing from 50 mV to 4.95 mV on a single +5 V supply. If high output current is required (> 10 mA), the AD8051, which also has rail-to-rail capability but can deliver up to 45 mA of output current, can be used. The AD8306 is a versatile and easily applied log-limiting ampli- fier. Being complete, it can be used with very few external com- ponents, and most applications can be accommodated using the simple connections shown in the preceding section. A few ex- amples of more specialized applications are provided here. High Output Limiter Loading The AD8306 can generate a fairly large output power at its differential limiter output interface. This may be coupled into a

50 W grounded load using the narrow-band coupling network

following similar lines to those provided for input matching. Alternatively, a flux-linked transformer, having a center-tapped primary, may be used. Even higher output powers can be ob- tained using emitter-followers. In Figure 31, the supply voltage to the AD8306 is dropped from 5 V to about 4.2 V, by the diode. This increases the available swing at each output to about 2 V. Taking both outputs differentially, a square wave output of 4 V p-p can be generated. VLOG VPS2 PADL LMHI LMLO PADL FLTR LMDR COM2 VPS1 PADL INHI INLO PADL COM1 ENBL AD8306 0.1mF 10V R LIM RSSI 3V TO 5V 0.1mF 10V +5V IN914 APPROX. 4.2V R LOAD SET R L = 5*RLIM 5V TO 3V DIFFERENTIAL OUTPUT = 4V pk-pk R LOAD Figure 31. Increasing Limiter Output Voltage cies, very careful attention must be paid to the issue of stability. wave whose amplitude is proportional to the control bias. Figure 32. Variable Limiter Output Programming duce different results at the log amp’s output. device (the output for a CDMA input being lower). tracted from the output voltage of the AD8306. settings for different setups are described in Table III.

to enable/disable the AD8306. the AD8306 differentially, R1 should be removed. into Position R9 (nominally open). the VLOG output according to the equation: fCORNER (Hz) = 12.7 · 10–6/(C7 + 3.5 · 10–12). Figure 33. Evaluation Board Schematic

REV. A AD8306 –16– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3592a–9–8/99PRINTED IN U.S.A. 16-Lead Narrow Body SO (SO-16) 16 9 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.3937 (10.00) 0.3859 (9.80) 0.050 (1.27) BSC SEATING PLANE 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25)3 458 0.0500 (1.27) 0.0160 (0.41) 0.0099 (0.25) 0.0075 (0.19)