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100 dB Range (10 nA to 1 mA) Logarithmic Converter Data Sheet AD8305 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2002–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Optimized for fiber optic photodiode interfacing Measures current over 5 decades Law conformance 0.1 dB from 10 nA to 1 mA Single- or dual-supply operation (3 V to 12 V total) Full log-ratio capabilities Nominal slope of 10 mV/dB (200 mV/decade) Nominal intercept of 1 nA (set by external resistor) Optional adjustment of slope and intercept Complete and temperature stable Rapid response time for a given current level Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm) Low power: ~5 mA quiescent current
APPLICATIONS
Wide range baseband logarithmic compression Measurement of current and voltage ratios Optical absorbance measurement FUNCTIONAL BLOCK DIAGRAM BIAS GENERATOR VLOG COMM VNEG VSUM IREF 0.5V 80kΩ 0.5V TEMPERATURE COMPENSATION VBE1 6.69kΩ COMM 20kΩ 451Ω VREF VRDZ 14.2kΩ INPT COMM 2.5V VPOS BFIN SCAL VOUT ILOG IPD 200kΩ VP 0.20 log10 IPD 1nA VBIAS VBE2 03053-001 Figure 1. GENERAL DESCRIPTION The AD83051 is an inexpensive microminiature logarithmic converter optimized for determining optical power in fiber optic systems. It uses an advanced implementation of a classic translinear (junction based) technique to provide a large dynamic range in a versatile and easily used form. A single-supply voltage of between 3 V and 12 V is adequate; dual supplies may optionally be used. The low quiescent current (typically 5 mA) permits use in battery-operated applications. The input current, I PD, of 10 nA to 1 mA applied to the INPT pin is the collector current of an optimally scaled NPN transistor, which converts this current to a voltage (VBE) with a precise logarithmic relationship. A second such converter is used to handle the reference current (IREF) applied to pin IREF. These input nodes are biased slightly above ground (0.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating I REF. The output of the logarithmic front end is available at Pin VLOG. The basic logarithmic slope at this output is nominally 200 mV/decade (10 mV/dB). Thus, a 100 dB range corresponds to an output change of 1 V . When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the AD8305 voltage reference output of 2.5 V at Pin VREF can be used to improve the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit), AD7823 (serial 8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of the logarithmic slope can be provided using a simple external resistor network. 1 Protected by U.S. Patent No. 5,519,308. The logarithmic intercept (also known as the reference current) is nominally positioned at 1 nA by the use of the externally generated current, IREF, of 10 µA, provided by a 200 kΩ resistor connected between VREF, at 2.5 V , and the reference input, IREF , at 0.5 V . The intercept can be adjusted over a wide range by varying this resistor. The AD8305 can also operate in a log ratio mode, with the numerator current applied to INPT and the denominator current applied to IREF. A buffer amplifier is provided for driving a substantial load, for use in raising the basic slope of 10 mV/dB to higher values, as a precision comparator (threshold detector), or in implementing low-pass filters. Its rail-to-rail output stage can swing to within 100 mV of the positive and negative supply rails, and its peak current sourcing capacity is 25 mA. It is a fundamental aspect of translinear logarithmic converters that the small signal bandwidth falls as the current level diminishes, and the low frequency noise-spectral density increases. At the 10 nA level, the bandwidth of the AD8305 is about 50 kHz and increases in proportion to I PD up to a maximum value of about 15 MHz. Using the buffer amplifier, the increase in noise level at low currents can be addressed by using it to realize low-pass filters of up to three poles. The AD8305 is available in a 16-lead LFCSP package and is specified for operation from −40°C to +85°C.
Rev. C | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
9/2017—Rev. B to Rev. C 4/2010—Rev. A to Rev. B 3/2003—Rev. 0 to Rev. A
Rev. C | Page 3 of 24 SPECIFICATIONS VP = 5 V, VN = 0 V, TA = 25°C, RREF = 200 kΩ, and VRDZ connected to VREF , unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INPUT INTERFACE Pin 4, INPT, Pin 3, IREF Specified Current Range, IPD Flows toward INPT pin 10 nA 1 mA Input Current Min/Max Limits Flows toward INPT pin 10 mA Reference Current, IREF, Range Flows toward IREF pin 10 nA 1 mA Summing Node Voltage Internally preset; may be altered by the user 0.46 0.5 0.54 V Temperature Drift −40°C < TA < +85°C 0.015 mV/°C Input Offset Voltage VINPT − VSUM, VIREF − VSUM −20 +20 mV LOGARITHMIC OUTPUT Pin 9, VLOG Logarithmic Slope 190 200 210 mV/dec −40°C < TA < +85°C 185 215 mV/dec Logarithmic Intercept1 0.3 1 1.7 nA Law Conformance Error 10 nA < IPD < 1 mA 0.1 0.4 dB Wideband Noise2 IPD > 1 µA 0.7 mV√Hz Small Signal Bandwidth2 IPD > 1 µA 0.7 MHz Maximum Output Voltage 1.7 V Minimum Output Voltage Limited by VN = 0 V 0.01 V Output Resistance 4.375 5 5.625 kΩ REFERENCE OUTPUT Pin 2, VREF Voltage With Reference to Ground 2.435 2.5 2.565 V Maximum Output Current Sourcing (grounded load) 20 mA Incremental Output Resistance Load current < 10 mA 2 Ω OUTPUT BUFFER Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT Input Offset Voltage −20 +20 mV Input Bias Current Flowing out of Pin 10 or Pin 11 0.4 mA Incremental Input Resistance 35 MΩ Output Range RL = 1 kΩ to ground VP − 0.1 V Incremental Output Resistance Load current < 10 mA 0.5 Ω Peak Source/Sink Current 25 mA Small Signal Bandwidth GAIN = 1 15 MHz Slew Rate 0.2 V to 4.8 V output swing 15 V/µs POWER SUPPLY Pin 8, VPOS; Pin 6 and Pin 7, VNEG Positive Supply Voltage (VP − VN) ≤ 12 V 3 5 12 V Quiescent Current 5.4 6.5 mA Negative Supply Voltage (Optional) (VP − VN) ≤ 12 V −5.5 0 V 1 Other values of logarithmic intercept can be achieved by adjusting RREF. 2 Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1.
Rev. C | Page 4 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Supply Voltage VP − VN 12 V Input Current 20 mA Internal Power Dissipation 500 mW θJA1 30°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C
1 With package die paddle soldered to thermal pad containing nine vias
connected to inner and bottom layers. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
12 VOUT
11 SCAL
10 BFIN
9 VLOG
16 COMM
15 COMM
14 COMM
13 COMM
Figure 2. Pin Configuration Table 3. Pin Function Descriptions be connected to ground when bipolar outputs are to be provided. 2 VREF Reference Output Voltage of 2.5 V. 3 IREF Accepts (Sinks) Reference Current, IREF. 5 VSUM Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential. 6, 7 VNEG Optional Negative Supply, VN (this pin is usually grounded; for details of usage, see the Applications section. 8 VPOS Positive Supply, (VP − VN ) ≤ 12 V. 9 VLOG Output of the Logarithmic Front End. 10 BFIN Buffer Amplifier Noninverting Input. 11 SCAL Buffer Amplifier Inverting Input. 13 to 16 COMM Analog Ground. EPAD The exposed pad must be soldered to ground.
a simplified schematic showing the key elements. Figure 33. Simplified Schematic degradation in law conformance (see Figure 3). IC is its collector current. IS is a scaling current, typically only 10−17 A. temperature (PTAT) and is 25.85 mV at 300 K. dependencies must be eliminated. voltage is processed by what is essentially an analog divider. mode output, VLOG, scaled 200 mV/decade.
chip resistors. Consequently, this practice is not recommended. recommended value of IREF = 10 mA. also allow higher slopes to be used. found in the AD8304 data sheet. Figure 15. The output low frequency voltage-noise spectral- signal current (>1 mA) prior to the AD8305 being powered on. the photodiode or current source. at the base of the transistor is ~0.5 V.
Rev. C | Page 13 of 24 the input compensation network and C2 is the recommended bypassing capacitor on VSUM. If board space limits the amount of external circuitry to the AD8305 it is possible to eliminate the transistor in Figure 34 and connect the resistor divider directly to VSUM. In this case the bias voltage at VSUM and INPT is set by the resistor values selected for the divider, not the internal biasing of the AD8305.
the various configuration options. Table 4. Evaluation Board Configuration Options and R19 can be used to adjust the output-offset voltage at the VLOG output. the AD8305 in log-ratio applications.
Figure 49. Evaluation Board Schematic
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
Figure 50. 16-Lead Lead Frame Chip Scale Package [LFCSP] 1 Z = RoHS Compliant Part; # denotes lead-free product may be top or bottom marked. registered trademarks are the prop erty of their respective owners.