AD8304-EVAL

AD8304ARUZ AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

REV. A a Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD8304 160 dB Range (100 pA –10 mA) Logarithmic Converter

FEATURES

Optimized for Fiber Optic Photodiode Interfacing Eight Full Decades of Range Law Conformance 0.1 dB from 1 nA to 1 mA Single-Supply Operation (3.0 V– 5.5 V) Complete and Temperature Stable Accurate Laser-Trimmed Scaling: Logarithmic Slope of 10 mV/dB (at VLOG Pin) Basic Logarithmic Intercept at 100 pA Easy Adjustment of Slope and Intercept Output Bandwidth of 10 MHz, 15 V/ /H9262s Slew Rate 1-, 2-, or 3-Pole Low-Pass Filtering at Output Miniature 14-Lead Package (TSSOP) Low Power: ~4.5 mA Quiescent Current (Enabled)

APPLICATIONS

High Accuracy Optical Power Measurement Wide Range Baseband Log Compression Versatile Detector for APC Loops FUNCTIONAL BLOCK DIAGRAM PDB BIAS VREF 10 2 12 IPD VPDB VSUM INPT VSUM 5 VNEG ~10k/H9024 ACOM VPS2 PWDN VPS1 VREF 7 VLOG 8 BFIN9 BFNG13 TEMPERA TURE COMPENSA TION 5k/H9024 VOUT 0.5V AD8304 PRODUCT DESCRIPTION The AD8304 is a monolithic logarithmic detector optimized for the measurement of low frequency signal power in fiber optic systems. It uses an advanced translinear technique to provide an exceptionally large dynamic range in a versatile and easily used form. Its wide measurement range and accuracy are achieved using proprietary design techniques and precise laser trimming. In most applications only a single positive supply, V P, of 5 V will be required, but 3.0 V to 5.5 V can be used, and certain applications benefit from the added use of a negative supply, VN. When using low supply voltages, the log slope is readily altered to fit the available span. The low quiescent current and chip disable features facilitate use in battery-operated applications. The input current, I PD, flows in the collector of an optimally scaled NPN transistor, connected in a feedback path around a low offset JFET amplifier. The current-summing input node operates at a constant voltage, independent of current, with a default value of 0.5 V; this may be adjusted over a wide range, including ground or below, using an optional negative supply. An adaptive biasing scheme is provided for reducing the dark current at very low light input levels. The voltage at Pin VPDB applies approximately 0.1 V across the diode for I PD = 100 pA, rising linearly with current to 2.0 V of net bias at I PD = 10 mA. The input pin INPT is flanked by the guard pins VSUM that track the voltage at the summing node to minimize leakage. The default value of the logarithmic slope at the output VLOG is accurately scaled to 10 mV/dB (200 mV/decade). The resistance at this output is laser-trimmed to 5 k Ω, allowing the slope to be lowered by shunting it with an external resistance; the addition of a capacitor at this pin provides a simple low-pass filter. The intermediate voltage VLOG is buffered in an output stage that can swing to within about 100 mV of ground (or V N) and the posi- tive supply, VP, and provides a peak current drive capacity of ± 20 mA. The slope can be increased using the buffer and a pair of external feedback resistors. An accurate voltage reference of 2V is also provided to facilitate the repositioning of the intercept. Many operational modes are possible. For example, low-pass filters of up to three poles may be implemented, to reduce the output noise at low input currents. The buffer may also serve as a com- parator, with or without hysteresis, using the 2 V reference, for example, in alarm applications. The incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. At the 1 nA level, the AD8304 ’s bandwidth is about 2 kHz, but this increases in proportion to I PD up to a maximum value of 10 MHz. The AD8304 is available in a 14-lead TSSOP package and specified for operation from –40°C to +85°C.

REV. A–2– AD8304–SPECIFICATIONS(VP = 5 V, VN = 0 V, TA = 25/H11543C, unless otherwise noted.) Parameter Conditions Min 1 Typ Max 1 Unit INPUT INTERFACE Pin 4, INPT; Pin 3 and Pin 5, VSUM Specified Current Range Flows toward INPT Pin 100 pA 10 mA Input Node Voltage Internally preset; may be altered 0.46 0.5 0.54 V Temperature Drift –40°C < T Input Guard Offset Voltage V IN – VSUM –20 +20 mV PHOTODIODE BIAS2 Established between Pin 6, V PDB, and Pin 4 Minimum Value I PD = 100 pA 70 100 mV Transresistance 200 mV/mA LOGARITHMIC OUTPUT Pin 8, VLOG Slope Laser-trimmed at 25 °C 196 200 204 mV/dec 0°C < TA < 70°C 194 207 mV/dec Intercept Laser-trimmed at 25 °C6 0 100 140 pA 0°C < TA < 70°C3 5 175 pA Law Conformance Error 10 nA < I PD < 1 mA, Peak Error 0.05 0.25 dB 1 nA < IPD < 1 mA, Peak Error 0.1 0.7 dB Maximum Output Voltage 1.6 V Minimum Output Voltage Limited by V N = 0 V 0.1 V Output Resistance Laser-trimmed at 25 °C 4.95 5 5.05 k Ω REFERENCE OUTPUT Pin 7, VREF Voltage WRT Ground Laser-trimmed at 25 °C 1.98 2 2.02 V Output Resistance 2 Ω OUTPUT BUFFER Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT Input Offset Voltage –20 +20 mV Input Bias Current Flowing out of Pin 9 or Pin 13 0.4 µA Incremental Input Resistance 35 M Ω Output Range R L = 1 kΩ to ground V P – 0.1 V Output Resistance 0.5 Ω Wide-Band Noise3 IPD > 1 µA (see Typical Performance Characteristics) 1 µV/√Hz Small Signal Bandwidth 3 IPD > 1 µA (see Typical Performance Characteristics) 10 MHz Slew Rate 0.2 V to 4.8 V output swing 15 V/ µs POWER-DOWN INPUT Pin 2, PWDN Logic Level, HI State –40°C < TA < +85°C, 2.7 V < VP < 5.5 V 2 V Logic Level, LO State –40°C < TA < +85°C, 2.7 V < VP < 5.5 V 1 V POWER SUPPLY Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG Positive Supply Voltage 3.0 5 5.5 V Quiescent Current 4.5 5.3 mA In Disabled State 60 µA Negative Supply Voltage 4 |1VP –VN| < 8V 0 –5.5 V NOTES 1Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 2This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground. 3Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics. 4Optional Specifications subject to change without notice.

REV. A AD8304 –3– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8304 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS * *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 VNEG Optional Negative Supply, V N. This pin is usually grounded; for details of usage, see Applications section. 2P WDN Power-Down Control Input. Device is active when PWDN is taken LOW. 3, 5 VSUM Guard Pins. Used to shield the INPT current line. 4I NPT Photodiode Current Input. Usually connected to photodiode anode (the photo current flows toward INPT). 6 VPDB Photodiode Biaser Output. May be connected to photodiode cathode to provide adaptive bias control.

7 VREF Voltage Reference Output of 2 V

8 VLOG Output of the Logarithmic Front-End

Processor; R OUT = 5 kΩ to ground.

9 BFIN Buffer Amplifier Noninverting Input

(High Impedance) 10 VPS2 Positive Supply, V P (3.0 V to 5.5 V)

11 VOUT Buffer Output; Low Impedance

12 VPS1 Positive Supply, V P (3.0 V to 5.5 V)

13 BFNG Buffer Amplifier Inverting Input

14 ACOM Analog Ground

(Not to Scale) AD8304 VNEG PWDN VSUM INPT VSUM VPDB VREF ACOM BFNG VPS1 VOUT VPS2 BFIN VLOG ORDERING GUIDE Model Temperature Range Package Description Package Option AD8304ARU –40°C to +85°CT ube, 14-Lead TSSOP RU-14 AD8304ARU-REEL 13" Tape and Reel AD8304ARU-REEL7 7" Tape and Reel AD8304-EVAL Evaluation Board

REV. A–4– AD8304–Typical Performance Characteristics 1.6 VLOG – V 1.4 0.8 0.6 0.4 0.2 1.2 1.0 –40/H11543C +25/H11543C +85/H11543C INPUT – A 100p 10m1n 10n 100n 1 /H9262 10/H9262100/H9262 1m TA = –40/H11543C, +25/H11543C, +85/H11543C VN = –0.5V 0/H11543C +70/H11543C TPC 1. V LOG vs. IPD INPUT – A 2.0 –2.0 100p 10m1n ERROR – dB (10mV/dB) 10n 100n 1 /H9262 10/H9262100/H9262 1m 1.5 –0.5 –1.0 –1.5 1.0 0.5 +25/H11543C –40/H11543C TA = –40/H11543C, +25/H11543C, +85/H11543C VN = –0.5V 0/H11543C +70/H11543C +85/H11543C TPC 2. Logarithmic Conformance (Linearity) for V LOG 2.0 –2.0 ERROR FROM IDEAL OUTPUT – dB (10mV/dB) 1.5 –0.5 –1.0 –1.5 1.0 0.5 5.5V 5.0V 4.5V INPUT – A 100p 10m1n 10n 100n 1 /H9262 10/H9262100/H9262 1m VN = –0.1V TPC 3. Absolute Deviation from Nominal Speci- fied Value of VLOG for Several Supply Voltages 0.510VSUM – V 0.508 0.502 0.500 0.506 0.504 +85/H11543C +25/H11543C –40/H11543C INPUT – A 100p 10m1n 10n 100n 1 /H9262 10/H9262100/H9262 1m TA = –40/H11543C, +25/H11543C, +85/H11543C TPC 4. V SUM vs. IPD INPUT – mA 2.8 1.4 0.6 01 0 1 VPDB – V 23456789 2.6 1.6 1.2 0.8 2.0 1.8 1.0 2.4 2.2 –40/H11543C +25/H11543C +85/H11543C TA = –40/H11543C, +25/H11543C, +85/H11543C TPC 5. V PDB vs. IPD INPUT – A 2.4 0.6 100p 10m1n VOUT – V 10n 100n 1 /H9262 10/H9262 100/H9262 1m 2.2 1.6 1.4 1.2 1.0 2.0 1.8 +85/H11543C +25/H11543C –40/H11543C 0.8 1.25 –1.00 ERROR – dB (10mV/dB) 1.00 0.25 –0.25 –0.50 0.75 0.50 –0.75 TA = –40/H11543C, +25/H11543C, +85/H11543C VP = 3.0V TPC 6. Logarithmic Conformance (Linearity) for a

3 V Single Supply (See Figure 6)

(VP = 5 V, VN = 0 V, TA = 25/H11543C, unless otherwise noted.)

REV. A AD8304 –5– FREQUENCY – Hz –30 –70 100 100M 1k NORMALIZED RESPONSE – dB 10k 100k 1M 10M –40 –50 –60 –10 –20 1nA 10nA 1/H9262A 10/H9262A 10mA 100/H9262A 1mA 100nA TPC 7. Small Signal AC Response, I PD to VLOG (5% Sine Modulation of I PD at Frequency) IPD – /H9262A 100 0.01 /H9262V rms/ Hz 0.1 10kHz 100kHz 100Hz 1kHz 1MHz 10m100n 10 /H92621n 10n 1 /H9262 100/H9262 1m TPC 8. Spot Noise Spectral Density at V LOG vs. IPD FREQUENCY – Hz 100 0.01 100 10M 1k /H9262V rms/ Hz 10k 100k 1M 0.1 1nA 10nA 100nA 1/H9262A 10/H9262A >100/H9262A TPC 9. Spot Noise Spectral Density at V LOG vs. Frequency INPUT CURRENT – A 10m100n 10 /H92621n 10n 1 /H9262 100/H9262 1m WIDEBAND NOISE – mV rms TPC 10. Total Wideband Noise Voltage at V LOG vs. IPD FREQUENCY – Hz –12 100 100M 1k NORMALIZED RESPONSE – dB 10k 100k 1M 10M AV = 5 AV = 2.5 AV = 2 AV = 1 GAIN = 1/H11547, 2/H11547, 2.5/H11547, 5/H11547 TPC 11. Small Signal Response of Buffer FREQUENCY – Hz –70 10 100k 100 NORMALIZED GAIN – dB 1k 10k –10 –20 –60 –30 –40 –50 fC = 1kHz TPC 12. Small Signal Response of Buffer Operating as Two-Pole Filter

REV. A–6– AD8304 INPUT – A 2.0 –2.0 100p 10m1n ERROR – dB (10mV/dB) 10n 100n 1 /H9262 10/H9262100/H9262 1m 1.5 –0.5 –1.0 –1.5 1.0 0.5 TA = 25/H11543C MEAN + 3/H9268 MEAN – 3/H9268 TPC 13. Logarithmic Conformance Error Distribution (3σ to Either Side of Mean) INPUT – A 100p 10m1n ERROR – dB (10mV/dB) 10n 100n 1 /H9262 10/H9262100/H9262 1m TA = 0/H11543C, 70/H11543C MEAN + 3/H9268 @ 70/H11543C MEAN – 3/H9268 @ 70/H11543C MEAN /H11550 3/H9268 @ 0/H11543C TPC 14. Logarithmic Conformance Error Distribution (3σ to Either Side of Mean) INPUT – A 100p 10m1n ERROR – dB (10mV/dB) 10n 100n 1 /H9262 10/H9262100/H9262 1m TA = /H1154640/H11543C, /H1154585/H11543C MEAN /H115453/H9268 @/H1154640/H11543C MEAN /H115463/H9268 @/H1154640/H11543C MEAN /H115503/H9268 @ /H1154585/H11543C TPC 15. Logarithmic Conformance Error Distribution (3σ to Either Side of Mean) TEMPERA TURE – /H11543C –15 –30 –40 90–30 VREF DRIFT – mV –20 –10 0 10 20 40 60 80 –10 –20 –25 30 50 70 MEAN + 3/H9268 MEAN – 3/H9268 TPC 16. V REF Drift vs. Temperature (3 σ to Either Side of Mean) TEMPERA TURE – /H11543C –40 90–30 SLOPE CHANGE FROM 25/H11543C – mV/dec –20 –10 0 10 20 40 60 80 30 50 70 MEAN + 3/H9268 MEAN – 3/H9268 TPC 17. Slope Drift vs. Temperature (3 σ to Either Side of Mean) TEMPERA TURE – /H11543C –30 –50 –40 90–30 INTERCEPT CHANGE FROM 25/H11543C – pA –20 –10 0 10 20 40 60 80 –20 –40 –10 30 50 70 MEAN + 3/H9268 MEAN – 3/H9268 TPC 18. Intercept Drift vs. Temperature (3 σ to Either Side of Mean)

REV. A AD8304 –7– TEMPERA TURE – /H11543C –40 90–30 vOS DRIFT – mV –20 –10 0 10 20 40 60 80 30 50 70 MEAN + 3/H9268 MEAN – 3/H9268 TPC 19. Output Buffer Offset vs. Temperature (3σ to Either Side of Mean) LOGARITHMIC SLOPE – mV/dec 180 160 196 204 198 HITS 200 202 100 140 120 TPC 20. Distribution of Logarithmic Slope, Sample 1000 LOGARITHMIC INTERCEPT – pA 160 60 140 80 HITS 100 120 100 140 120 TPC 21. Distribution of Logarithmic Intercept, Sample 1000 INPUT GUARD OFFSET – mV 180 –20 20 –10 HITS 01 0 100 140 120 160 TPC 22. Distribution of Input Guard Offset Voltage (VINPT – VSUM), Sample 1000

REV. A–8– AD8304 BASIC CONCEPTS The AD8304 uses an advanced circuit implementation that exploits the well known logarithmic relationship between the base-to-emitter voltage, VBE, and collector current, IC, in a bipolar transistor, which is the basis of the important class of translinear circuits *: VV I IBE T C S= log( / ) (1) There are two scaling quantities in this fundamental equation, namely the thermal voltage VT = kT/q and the saturation current IS. These are of key importance in determining the slope and intercept for this class of log amp. V T has a process-invariant value of 25.69 mV at T = 25°C and varies in direct proportion to absolute temperature, while IS is very much a process- and device-dependent parameter, and is typically 10–16 A at T = 25°C but exhibits a huge variation over the temperature range, by a factor of about a billion. While these variations pose challenges to the use of a transistor as an accurate measurement device, the remarkable matching and isothermal properties of the components in a monolithic process can be applied to reduce them to insignificant proportions, as will be shown. Logarithmic amplifiers based on this unique property of the bipolar transistor are called translinear log amps to distin- guish them from other Analog Devices products designed for RF applications that use quite different principles. The very strong temperature variation of the saturation current I S is readily corrected using a second reference transistor, having an identical variation, to stabilize the intercept. Similarly, propri- etary techniques are used to ensure that the logarithmic slope is temperature-stable. Using these pri nciples in a carefully scaled design, the now accurate relationship between the input current, IPD, applied to Pin INPT, and the voltage appearing at the inter- mediate output Pin VLOG is: VV I ILOG Y PD Z= log ( / )10 (2) VY is called the slope voltage (in the case of base-10 logarithms, it is also the “volts per decade”). The fixed current IZ is called the intercept. The scaling is chosen so that VY is trimmed to 200 mV/decade (10 mV/dB). The intercept is positioned at 100 pA; the output voltage V LOG would cross zero when IPD is of this value. However, when using a single supply the actual VLOG must always be slightly above ground. On the other hand, by using a negative supply, this voltage can actually cross zero at the intercept value. Using Equation 2, one can calculate the output for any value of I PD. Thus, for an input current of 25 nA, VVn A pA VLOG ==02 25 100 0 479610. log ( / ) . (3) In practice, both the slope and intercept may be altered, to either higher or lower values, without any significant loss of calibration accuracy, by using one or two external resistors, often in conjunc- tion with the trimmed 2 V voltage reference at Pin VREF. Optical Measurements When interpreting the current IPD in terms of optical power inci- dent on a photodetector, it is necessary to be very clear about the transducer properties of a biased photodiode. The units of this transduction process are expressed as amps per watt. The param- eter /H9267, called the photodiode responsivity, is often used for this purpose. For a typical InGaAs p-i-n photodiode, the responsivity is about 0.9 A/W. It is also important to note that amps and watts are not usually related in this proportional manner. In purely electrical circuits, a current I PD applied to a resistive load R L results in a power proportional to the square of the current (that is, I PD 2 RL). The reason for the difference in scaling for a photodiode interface is that the current I PD flows in a diode biased to a fixed voltage, VPDB. In this case, the power dissipated within the detector diode is simply proportional to the current IPD (that is, IPDVPDB) and the proportionality of I PD to the optical power, POPT, is preserved. IPPD OPT=ρ (4) Accordingly, a reciprocal correspondence can be stated between the intercept current, IZ, and an equivalent “intercept power,” PZ, thus: IPZZ=ρ (5) and Equation 2 may then be written as: VV P PLOG Y OPT Z= log ( / )10 (6) For the AD8304 operating in its default mode, its I Z of 100 pA corresponds to a P Z of 110 picowatts, for a diode having a responsivity of 0.9 A/W. Thus, an optical power of 3 mW would generate: VV m W pW VLOG ==02 3 110 1 48710.l o g ( / ). (7) Note that when using the AD8304 in optical applications, the interpretation of VLOG is in terms of the equivalent optical power, the logarithmic slope remains 10 mV/dB at this output. This can be a little confusing since a decibel change on the optical side has a different meaning than on the electrical side. In either case, the logarithmic slope can always be expressed in units of mV per decade to help eliminate any confusion. Decibel Scaling In cases where the power levels are already expressed as so many decibels above a reference level (in dBm, for a reference of 1 mW), the logarithmic conversion has already been performed, and the “log ratio ” in the above expressions becomes a simple differ- ence. One needs to be careful in assigning variable names here, because “P” is often used to denote actual power as well as this same power expressed in decibels, while clearly these are numeri- cally different quantities. Such potential misunderstandings can be avoided by using “D” to denote decibel powers. The quantity V Y (“volts per decade”) must now be converted to its decibel value, VY´ = VY/10, because there are 10 dB per decade in the context of a power measurement. Then it can be stated that: VD D m V d BLOG OPT Z=− ()20 / (8) where DOPT is the optical power in decibels above a reference level, and DZ is the equivalent intercept power relative to the same level. This convention will be used throughout this data sheet. *For a basic discussion of the topic, see Translinear Circuits: An Historical Overview, B. Gilbert, Analog Integrated Circuits and Signal Processing, 9, pp. 95–118, 1996.

cept, which require a minimal number of external components. between VLOG and the inverting input Pin BFNG. lower headroom in the output swing. Alteration of the logarithmic intercept is only slightly more tricky. from VLOG to VREF (2 V) as shown in Figure 4. Figure 4. Method for Lowering the Intercept combined with various slope variations. a third resistor, RZ, placed between the Pins BFNG and VREF. for representative intercepts.

Figure 15. Using the Buffer to Invert the Polarity

2 V V

LOG (shown dotted) to decrease the noise bandwidth. Figure 16. Calibrated Level Comparator Figure 17. Multidecade Current Source

1 VNEG ACOM 14

2 PWDN BFNG 13

3 VSUM VPS1 12

4 INPT VOUT 11

5 VSUM VPS2 10

6 VPDB BFIN 9

7 VREF VLOG 8

Figure 22. Evaluation Board Schematic Figure 20. Configuration for Logarithmic sures to provide additional shielding to external noise sources. Figure 21. Configuration for Noise Spectral

removed when a fixed bias is applied to VSUM. of the adaptive bias output at Pin VPDB. VSUM Pin or connected to ground. Figure 23. Component Side Layout Figure 24. Component Side Silkscreen

C02743–0–8/02(A) PRINTED IN U.S.A. –20– AD8304 REV. A OUTLINE DIMENSIONS 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 4.50 4.40 4.30 14 8 6.40 BSC PIN 1 5.10 5.00 4.90 0.65 BSC SEATING PLANE 0.15 0.05 0.30 0.19 1.20 MAX 1.05 1.00 0.80 0.20 0.09 8/H11543 0/H11543 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AB-1

Revision History

8/02—Data Sheet changed from REV. 0 to REV. A.