AD82010 ESMT | Alldatasheet
Document overview
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Technical content
Features
16/18/20/24-bit input with I2S, Left-alignment and Right-alignment data format PSNR & DR(A-weighting) Loudspeaker: 102dB (DR) @ 24V Multiple sampling frequencies (Fs) 32kHz / 44.1kHz / 48kHz and 64kHz / 88.2kHz / 96kHz and 128kHz/176.4kHz/192kHz System clock = 64x, 128x, 256x, 384x, 512x, 768x, 1024x Fs 256x~1024x Fs for 32kHz / 44.1kHz / 48kHz 128x~512x Fs for 64kHz / 88.2kHz / 96kHz 64x~256x Fs for 128kHz /176.4kHz/192kHz Supply voltage 3.0~3.3V for digital circuit 4.5V~26V for loudspeaker driver Loudspeaker output power for Stereo 10W x 2ch into 8Ω @ 10% THD+N@13V 15W x 2ch into 8Ω @ 10% THD+N@16V Sounds processing including: Volume control (+24dB~-103dB, 0.125dB/step) Dynamic range control Power clipping Channel mixing User programmed noise gate with hysteresis window DC-blocking high-pass filter Anti-pop design I2C control interface with selectable device address Internal PLL Dynamic temperature control Short circuit and over-temperature protection LV Under-voltage shutdown and HV Under-voltage detection DC detection function Clock detection function Filter-less solution MCLK-less application
Applications
TV audio Boom-box, CD and DVD receiver, docking system Powered speaker Wireless audio
Description
AD82010 is a digital audio amplifier capable of driving a pair of 8Ω,20W or a single 4Ω,40W speaker, both which operate with play music at a 24V supply . Using I2C digital control interface, the user can control AD82010’s input format selection, mute and volume control functions. AD82010 has many built -in protection circuits to safeguard AD82010 from connection errors.
Ordering Information
Product ID Package Packing / MPQ Comments AD82010-QG24NRT E-TSSOP 24L
62 Units / Tube
100 Tubes / Small Box
AD82010-QG24NRR 2.5K Units Tape & Reel Green
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 2/52 Pin Assignment (Top View) TSSOP TSSOP--2424 DD--505 505 SD/ FAULT/ BCLK LRCIN GND DVDD SDATA GND SCL SDA PVCCL BSPL OUTPL PGNDL OUTNL BSNL BSNR OUTNR PGNDR OUTPR BSPR PVCCR AD82010 E-TSSOP-24L VREG GVDD Pin Description NAME E-TSSOP 24L TYPE DESCRIPTION CHARACTERISTICS SD
1 I Shut down, low active
2 I/O
pin is a dual function pin. One is I2C address setting during power up. The other one is error status report (low active), It sets by register of A_SEL_FAULT at address 0x02 B[7] to enable it. Schmitt trigger TTL input buffer BCLK 3 I Bit clock input (64Fs) Schmitt trigger TTL input buffer LRCIN 4 I Left/Right clock input (Fs) Schmitt trigger TTL input buffer SCL 5 I I2C serial clock input Schmitt trigger TTL input buffer SDA 6 I/O I2C bi-directional serial data Schmitt trigger TTL input buffer DVDD 7 P Digital Power GND 8 P Ground GVDD 9 O 5V Regulator voltage output. This pin must not be used to drive external devices. VREG 10 O 1.8V Regulator voltage output
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 3/52 SDATA 11 I Serial audio data input Schmitt trigger TTL input buffer GND 12 P Ground PVCCR 13 P High-voltage power supply for right-channel. Right channel and left channel power supply inputs are connect internal BSPR 14 P Bootstrap I/O for right channel, positive high side FET OUTPR 15 O Class-D H-bridge positive output for right channel. PGNDR 16 P Power ground for the H-bridges. OUTNR 17 O Class-D H-bridge negative output for right channel. BSNR 18 P Bootstrap I/O for right channel, negative high side FET BSNL 19 P Bootstrap I/O for left channel, negative high side FET OUTNL 20 O Class-D H-bridge negative output for left channel. PGNDL 21 P Power ground for the H-bridges. OUTPL 22 O Class-D H-bridge positive output for left channel. BSPL 23 P Bootstrap I/O for left channel, positive high side FET PVCCL 24 P High-voltage power supply for left-channel. Right channel and left channel power supply inputs are connect internal
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 4/52 Functional Block Diagram VREG Regulator BCLK SDATA LRCLK Over Sample filter Power clipping Digital Audio I/F SDM DAC ControlSDA SD/ SCL CKDET DCDET OTP OCP UVLO AD82010 DRC Noise gate/ DVDD OVP PLL SD/DRC/ Volume control DC blocking filter/ GVDD LINP LINN Modulator OUTPLPower StageModulator OUTNL OUTPR OUTNR DC Detect Power Stage PGND PVCCR Short - Circuit Protection BSPL BSNL N/N N/N BSPR BSNR Δ-wave PWM Logic PWM Logic RINP RINN Gain Control Amplifier Gain Control Amplifier PGND FAULT/ GND PVCCL Available Package Package Type Device No. θ ja(℃/W) Ψ jt(℃/W) θ jt(℃/W) Exposed Thermal Pad E-TSSOP 24L AD82010 26.8 0.35 27.1 Yes (Note1) Note 1.1: The thermal pad is located at the bottom of the package. To optimize thermal performance, soldering the thermal pad to the PCB’s ground plane is suggested. Note 1.2: θ ja is measured on a room temperature (TA=25℃), natural convection environment test board, which is constructed with a thermally efficient, 4-layers PCB (2S2P). The measurement is tested using the JEDEC51-5 thermal measurement standard. Note 1.3: θ jt represents the heat resistance for the heat flow between the chip and the package’s top surface. Note 1.4: Ψ jt represents the heat resistance for the heat flow between the chip and the package’s top surface center.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 5/52 Absolute Maximum Ratings Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. Symbol Parameter Min Max Units DVDD Supply for Digital Circuit -0.3 3.6 V PVCCL/R Supply for Driver Stage -0.3 30 V Vi Input Voltage -0.3 3.6 V Tstg Storage Temperature -65 150 oC TJ Junction Operating Temperature -40 150 oC RL BTL: PVCC ＞ 13V 4.8 Ω BTL: PVCC ≦ 13V 3.2 Ω PBTL 3.2 Ω ESD Human Body Model ±2K V Charged Device Model ±750 Pd Power Dissipation at TA=25℃ 4.66 W Recommended Operating Conditions Marking Information AD82010 Line 1 : LOGO Line 2 : Product no. Line 3 : Tracking Code Symbol Parameter Typ Units DVDD Supply for Digital Circuit 3.0~3.6 V PVCCL/R Supply for Driver Stage 4.5~26 V TJ Junction Operating Temperature -40~125 oC TA Ambient Operating Temperature -40~85 oC PIN1 DOT ESMT AD82010 Tracking Code E-TSSOP-24L
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 6/52 General Electrical Characteristics Condition: TA=25 oC (unless otherwise specified). Symbol Parameter Condition Min Typ Max Units IPD PVCC Supply Current during Power Down PVCC=24V 24 uA IQ(24V) PVCC Supply Current during standby PVCC=24V 21 mA IQ(12V) PVCC=12V 17 mA IQ(DVDD) Quiescent current for DVDD DVDD=3.3V 8 mA TSENSOR Junction Temperature for Driver Shutdown 160 oC Temperature Hysteresis for Recovery from Shutdown 35 oC DVDDUVH Under Voltage Disabled (For DVDD) 2.9 V DVDDUVL Under Voltage Enabled (For DVDD) 2.6 V PVCCUVH Under Voltage Disabled (For PVCC) 10.4 V PVCCUVL Under Voltage Enabled (For PVCC) 9.7 V Rds-on Static Drain-to-Source On-state Resistor, NMOS PVCC=24V, Id=500mA 225 mΩ GVDD 5V Regulator voltage output. 5 V VREG 1.8V Regulator voltage output. 1.8 V ISC L(R) Channel Over-Current Protection (Note 2) 8 A VIH High-Level Input Voltage DVDD=3.3V 1.7 V VIL Low-Level Input Voltage DVDD=3.3V 0.8 V VOH High-Level Output Voltage DVDD=3.3V 2.4 V VOL Low-Level Output Voltage DVDD=3.3V 0.4 V CI Input Capacitance 6.4 pF fPWM PWM Frequency 235 315 395 KHz Note 2: Loudspeaker over-current protection is only effective when loudspeaker drivers are properly connected with external LC filters. Please refer to the application circuit example for recommended LC filter configuration.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 7/52 Application Circuit Example for Stereo SCL LRCIN DVDD SDA BCLK PVCCL PGND OUTPL BSNL OUTNL BSPL AD82010 GND SDATA VREG GND GVDD PVCCR PGND BSNR OUTNR BSPR OUTPR SD FAULT Bead 1nF Bead PVCC (Note 3.1) 10uF0.1uF PVCC Bead Bead 0.22uF 0.1uF 1uF 0.1uF 1uF 1uF DVDD 10 10 10 10 470pF 470pF 470pF 470pF 1nF 1nF 1nF 0.22uF 0.22uF 0.22uF 0.1uF 10uF (Note 3.1) (Note 3.2) (Note 3.2) Note 3.1: PVCC needs increasing to 100uFx2 if the power ripple > 500mVpp. Note 3.2: Option for EMI.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 8/52 Application Circuit Example for Mono SCL LRCIN DVDD SDA BCLK PVCCL PGND OUTPL BSNL OUTNL BSPL AD82010 GND SDATA VREG GND GVDD PVCCR PGND BSNR OUTNR BSPR OUTPR SD FAULT PVCC PVCC 0.1uF 1uF 0.1uF 1uF 1uF DVDD Bead Bead 1nF 1nF470pF 470pF 10 10 0.47uF 0.47uF (Note 3.1) 10uF 10uF (Note 3.1) 0.1uF 0.1uF (Note 3.2) Note 3.1: PVCC needs increasing to 100uFx2 if the power ripple > 500mVpp. Note 3.2: Option for EMI.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 9/52 Electrical Characteristics and Specifications for Loudspeaker (Stereo) Condition: TA=25 oC, DVDD=3.3V, PVCCL=PVCCR=24V, FS=48kHz, Load=8Ω ; Input is 1kHz sine wave. Volume is 0dB unless otherwise specified. Symbol Parameter Condition Input Level Min Typ Max Units PO Output Power (Note 5) THD+N=0.02%, f=1kHz, PVCC=24V 20 W THD+N=10%, f=1kHz, PVCC=12V, RL=4Ω 16 W THD+N=10%, f=1kHz, PVCC=12V, RL=8Ω 9.7 W THD+N Total Harmonic Distortion + Noise PO=10W 0.027 % PO=5W 0.04 % Vn Noise RL=8Ω,A-Weighted Filter 117 uV RL=8Ω,A-Weighted Filter, PVCC=12V 76 uV SNR Signal to Noise Ratio (Note 4) Maximum output at THD+N=1%, f=1kHz, 102 dB DR Dynamic Range (Note 4) -60dB of input level 109 dB PSRR Power Supply Rejection Ratio VRIPPLE=200mVpp at 1kHz 66 dB X-talk Channel Separation (non-shield choke) PO=1W at 1kHz 85 dB Note 4: Measured with A-weighting filter. Note 5: Thermal dissipation is limited by package type and PCB design, the external heat-sink or system cooling method should be adopted for RMS power output.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 10/52 THD + N (%) v.s. Output power (8Ω load) 0.01 0.02 0.05 0.1 0.2 0.5 100 10m 20m 50m 100m 200m 500m W THD + N (%) v.s. Output power (6Ωload) 0.01 0.02 0.05 0.1 0.2 0.5 100 10m 20m 50m 100m 200m 500m W T T T T T Load=6Ω+47uH Load=8Ω+66uH 12V 18V 12V 18V 24V
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 11/52 THD + N (%) v.s. Output power (4Ωload) 0.01 0.02 0.05 0.1 0.2 0.5 100 10m 20m 50m 100m 200m 500m W T T THD + N (%) v.s. Frequency (24V 8Ωload) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20k 100 200 500 10k Hz Load=4Ω+33uH 8V 12V 10W 20W Load=8Ω+66uH
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 12/52 Noise (8Ωload) 160u 10u 20u 30u 40u 50u 60u 70u 80u 90u 100u 110u 120u 130u 140u 150u V 20k 100 200 500 10k Hz AD82010_8ohm stereo 6 8 10 12 14 16 18 20 22 24 26 Output Power (W) PVCC (V) Note: Dashed Line represent thermally limited regions. 12V 18V 24V Load=8Ω+66uH THD=10% THD=1%
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 13/52 AD82010_6ohm stereo Note: Dashed Line represent thermally limited regions. Efficiency (Stereo 8Ωload) / 2ch 100 0 10 20 30 40 50 60 70 80 Output Pow er (W)*2CH Efficiency (%) 12V 18V 24V THD=10% THD=1%
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 14/52 Efficiency (Stereo 6Ωload) / 2ch 100 0 10 20 30 40 50 60 70 Output Pow er (W)*2CH Efficiency (%) 12V 18V Efficiency (Stereo 4Ωload) / 2ch 100 0 10 20 30 40 50 Output Pow er (W)*2CH Efficiency (%) 12V
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 15/52 Electrical Characteristics and Specifications for Loudspeaker (Mono) Condition: TA=25 oC, DVDD=3.3V, PVCCL=PVCCR=24V, FS=48kHz, Load=4Ω ; Input is 1kHz sine wave. Volume is 0dB unless otherwise specified. Symbol Parameter Condition Input Level Min Typ Max Units PO Output Power (Note 5) THD+N=0.08%, f=1kHz, PVCC=24V 40 W THD+N=10%, f=1kHz, PVCC=12V 19.5 W THD+N Total Harmonic Distortion + Noise PO=20W 0.045 % Vn Noise RL=4Ω ,A-Weighted Filter 102 uV RL=4Ω ,A-Weighted Filter PVCC=12V 82 uV SNR Signal to Noise Ratio (Note 4) Maximum output at THD+N=1%, f=1kHz, 103 dB DR Dynamic Range (Note 4) -60dB of input level 110 dB PSRR Power Supply Rejection Ratio VRIPPLE=200mVpp at 1kHz 66 dB Note 4: Measured with A-weighting filter. Note 5: Thermal dissipation is limited by package type and PCB design, the external heat-sink or system cooling method should be adopted for RMS power output. THD + N (%) v.s. Output power (Mono 4Ωload) 0.01 0.02 0.05 0.1 0.2 0.5 100 10m 20m 50m 100m 200m 500m W 12V 18V 24V Load=4Ω+33uH
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 16/52 THD + N (%) v.s. Frequency (24V Mono 4Ωload) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20k 100 200 500 10k Hz T T T T Noise (Mono 4Ωload) 160u 10u 20u 30u 40u 50u 60u 70u 80u 90u 100u 110u 120u 130u 140u 150u V 20k 100 200 500 10k Hz 10W 20W 40W 12V 18V 24V Load=4Ω+33uH Load=4Ω+33uH
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 17/52 AD8010_4ohm Mono 6 8 10 12 14 16 18 20 22 24 26 Output Power (W) PVCC (V) Note: Dashed Line represent thermally limited regions. Efficiency (Mono 4Ωload) 100 0 10 20 30 40 50 60 70 80 90 Output Power (W) Efficiency (%) 12V 18V 24V THD=10% THD=1%
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 18/52 MSB LSB MSB LSB Left RightLRCIN BCLK SDATA Interface Configuration I2S Left-Alignment Right-Alignment System Clock Timing BCLK tHIGH t LOW t PERIOD tHIGH ≧ 162.7 ns , t LOW ≧ ns , t PERIOD ≧ ns Default setting,PLL is enable BCLK system162.7 325.4 Timing Relationship (Using I2S format as an example) MSB LSB MSB LSB Left RightLRCIN BCLK SDATA MSB LSB Left Right MSB LSBSDATA BCLK LRCIN LRCIN BCLK SDATA Left Right MSB MSB t LR tBL tLB tBCC tDS tDH tBCHtBCL
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 19/52 Symbol Parameter Min Typ Max Units tLR LRCIN Period (1/FS) 5.2 31.25 us tBL BCLK Rising Edge to LRCIN Edge 50 ns tLB LRCIN Edge to BCLK Rising Edge 50 ns tBCC BCLK Period (1/64FS) 162.76 488.3 ns tBCH BCLK Pulse Width High 40.69 244 ns tBCL BCLK Pulse Width Low 40.69 244 ns tDS SDATA Set-Up Time 50 ns tDH SDATA Hold Time 50 ns I2C Timing Parameter Symbol Standard Mode Fast Mode Unit MIN. MAX. MIN. MAX. SCL clock frequency fSCL 0 100 0 400 kHz Hold time for repeated START condition tHD,STA 4.0 --- 0.6 --- us LOW period of the SCL clock tLOW 4.7 --- 1.3 --- us HIGH period of the SCL clock tHIGH 4.0 --- 0.6 --- us Setup time for repeated START condition tSU;STA 4.7 --- 0.6 --- us Hold time for I2C bus data tHD;DAT 0 3.45 0 0.9 us Setup time for I2C bus data tSU;DAT 250 --- 100 --- ns Rise time of both SDA and SDL signals tr --- 1000 20+0.1Cb 300 ns Fall time of both SDA and SDL signals tf --- 300 20+0.1Cb 300 ns Setup time for STOP condition tSU;STO 4.0 --- 0.6 --- us Bus free time between STOP and the next START condition tBUF 4.7 --- 1.3 --- us Capacitive load for each bus line Cb 400 400 pF Noise margin at the LOW level for each connected device (including hysteresis) VnL 0.1VDD --- 0.1VDD --- V Noise margin at the HIGH level for each connected device (including hysteresis) VnH 0.2VDD --- 0.2VDD --- V tf tHD;STA tLOW tr tHD;DAT tSU;DAT tf tHIGH tSU;STA tHD;STA tSU;STO tr tBUF S Sr P S
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 20/52 Operation Description Shut down control AD82010 has a built -in volume fade -in/fade-out design for SD/Mute function. The relative SD timing diagrams for loudspeakers are shown below. Volume Level time +24 dB -103 dB Fade out time Fade in time Mute state PD enabled PD disabled Original level Volume Level time +24 dB -103 dB Fade out time Fade in time PD enabled PD disabled Original level The volume level will be decreased to -∞dB in several LRCIN cycles. Once the fade -out procedure is finished, AD82010 will turn off the power stages, clock signals (for digital circuits) and current (for analog circuits). After PD pin is pulled low, AD82010 requires Tfade to finish the aforementioned work before entering power down state. Users can not program AD82010 during power down state. Also, all settings in the registers will remain intact unless DVDD is removed. If the PD signal is removed during the fade-out procedure (above, right figure), AD82010 will still execute the fade-in procedure. In addition, AD82010 will establish the analog circuits’ bias current and send the clock signals to digital circuits. Afterwards, AD82010 will return to its normal status. )96/1(512)1010( 20 )(arg Kxx dBoriginaldBett
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 21/52 Internal PLL AD82010 has a built-in PLL with multiple MCLK/FS ratio, which is selected by I2C control interface. The MCLK/FS ratio will be fixed at 1024x, 512x, or 256x with a sample frequency of 48kHz, 96kHz, or 192kHz respectively. Anti-pop design AD82010 will generate appropriate control signals to suppress pop sounds during initial power on/off, power down/up, mute, and volume level changes. I2C chip select FAULT is an input pin during power start-up. It can be pulled high (15-kΩ pull up) or low (15-kΩ pull down) for I2C address selection. Low indicates an I2C address of 0x30, and high an address of 0x34. Self-protection circuits AD82010 has built-in protection circuits including thermal, short-circuit and under-voltage detection circuits. (i) When the internal junction temperature is higher than 160 ℃, power stages will be turned off and AD82010 will return to normal operation once the temperature drops to 135 ℃. The temperature values may vary around 10%. (ii) The short-circuit protection circuit protects the output stage when the wires connected to loudspeakers are shorted to each other or GND/VDD. For normal 24V operations, the current flowing through the power stage will be less than 8A for stereo configuration. Otherwise, the short -circuit detectors may pull the FAULT pin to DGND, disabling the output stages. When the over -temperature or short -circuit condition occurs, the open-drain FAULT pin will be pulled low and latched into ERROR state. Once the short-circuit condition is removed, AD82010 will exit ERROR state when one of the following conditions is met: (1) SD pin is pulled low, (3) Master mute is enabled through the I2C interface. (iii) Once the DVDD voltage is lower than 2.6V, AD82010 will turn off its loudspeaker power stages and cease the operation of digital processing circuits. When DVDD becomes larger than 2.9V, AD82010 will return to normal operation. (iv) If the master clock inputted into BCLK pin stops during the period for 500 ns or more, AD82010 detect the stop of BCLK. In this state, amplifier outputs are forced to Weak Low. If master clock is inputted normally again, FAULT pin is set to high.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 22/52 Power on sequence Hereunder is AD82010’s power on sequence for FS=48kHz application . Give a de -mute command via I 2C when the whole system is stable. OthersWaitSW Reset De- Mute PVCCL/R DVDD BCLK LRCIN SD t2 t3 t4 t5 I2C I2C Active t10 t 11 t12 Power-on Normal operation SD = L Normal Operation t13OUTPR/OUTNR OUTPL/OUTNL Note: Please be noted below sequence shall be follow up with “I2C Active” processing, (1) Set S/W reset bit (0X02 B[4]) = 0 (2) Delay 5ms (3) Set S/W reset bit (0X02 B[4]) = 1 (4) Delay 20ms (5) Set all channels = mute (setting address 0X02 B[3] = 1) (6) Set other registers (except setting address 0X02 B[4:3]) (7) Set all channels = de-mute (setting address 0X02 B[3] = 0) Symbol Condition Min Max Units t1 0 - msec t2 0 - msec t3 10 - msec t4 0 - msec t5 10 - msec 22(FADE_SPEED=0) 176(FADE_SPEED=1) msec t7 - 150 msec t8 10 - msec t9 150 - msec t10 - 0.1 msec t11 25 - msec
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 23/52 t12 25 - msec t13 20 - msec FS=96KHz or 192KHz application, below mentioned power on sequence shall be follow up with. Give a de-mute command via I2C when the whole system is stable. # 1 # 2 P V C C L/R DVDD B C L K L R C I N SD I2 C O U T P R/O U T N R O U T P L/O U T N L P o w e r O n N o r m a l O p e r a tio n SD = L N o r m a l O p e r a tio n t7 t8 t10 t11 t12 t13 #1: Steps #2: Steps 1) Set S/W reset bit (0X02 B[4]) = 0 1) Set all channels = de-mute (0x02 B[3] = 0) 2) Delay 5ms #3: If reg.0x16 B[3:2]=00, max. is 30ms 3) Set S/W reset bit (0X02 B[4]) = 1 If reg.0x16 B[3:2]=11, max. is 240ms 4) Delay 20ms 5) Set all channels = mute (0X02 B[3] = 1) 6) Set I2S format as Fs = 96KHz or 192KHz (0X01 B[5:4] = 01 or 10) 7) Set other registers (except 0X01 B[5:4] and 0X02 B[4:3]) Symbol Min Max Units Symbol Min Max Units t1 0 - msec t10 35 - msec t2 25 - msec t11 10 - msec t3 35 - msec t12 10 - msec t4 20 - msec t13 150 - msec t5 0 - msec t6 150 - msec t7 - 0.1 msec t8 - #3 msec t9 35 - msec
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 24/52 Power off sequence Hereunder is AD82010’s power off sequence. BCLK LRCIN /SD LA, LB, RA, RB I2C Don’t care t3 t4 DVDD PVCC Symbol Condition Min Max Units t1 35(Note 6) - msec t2 0 - msec t3 1(Note 7) - msec t4 1(Note 7) - msec Note 6: t1 min 35ms refer to FADE_SPEED register=00(address:0X16,bit3~2). If the FADE_SPEED=11, T1 should change to 280ms. Note 7: Don’t care it if the PVCC or DVDD power supports continuously during the system off.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 25/52 I2C-Bus Transfer Protocol Introduction AD82010 employs I 2C-bus transfer protocol. Two wires, serial data and serial clock carry information between the devices connected to the bus. Each device is recognized by a unique 7 -bit address and can operate as either a transmitter or a receiver. The master device initiates a data transfer and provides the serial clock on the bus. AD82010 is always an I2C slave device. Protocol START and STOP condition START is identified by a high to low transition of the SDA signal.. A START condition must precede any command for data transfer. A STOP is identified by a low to high transition of the SDA signal. A STOP condition terminates communication between AD82010 and the master device on the bus. In both START and STOP, the SCL is stable in the high state. Data validity The SDA signal must be stable during the high period of the clock. The high or low change of SDA only occurs when SCL signal is low. AD82010 samples the SDA signal at the rising edge of SCL signal. Device addressing The master generates 7 -bit address to recognize slave devices. When AD82010 receives 7 -bit address matched with 0110000 or 0110100 ( FAULT pin state during power up), AD82010 will acknowledge at the 9 th bit (the 8 th bit is for R/ W bit). The bytes following the device identification address are for AD82010 internal sub-addresses. Data transferring Each byte of SDA signaling must consist of 8 consecutive bits, and the byte is followed by an acknowledge bit. Data is transferred with MSB first, as shown in the figure below. In both write and read operations, AD82010 supports both single -byte and multi -byte transfers. Refer to the figure below for detailed data-transferring protocol. R/W ACK DEV_ADDR SUB_ADDR STOP DATAIN START ACK ACK START DEV_ADDR SUB_ADDR DEV_ADDR DATAIN STOP R/W ACK ACK NO ACK START START DEV_ADDR SUB_ADDR DEV_ADDR DATAIN STOP R/W ACK ACK ACK START R/W R/W DATAIN NO ACK Byte Write Random Address Read Sequential Random Read START DEV_ADDR SUB_ADDR DATAIN DATAIN STOP R/W ACK ACK ACK ACK Multi-Byte Write ACK ACK ACK
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 26/52 Register Table The audio signal processing data flow is shown as the following figure. Users can control these function by programming appropriate setting to register table. In this section, the register table is summarized first. The definition of each register follows in the next section. Interpolation filter Volume control SDM L/R exchange ASRC Volume control SDMHPF DAII BCLK LRCIN SDATA Audio Signal Processing Power Limt (DRC) Mixing DTC control DTC control Power Clipping Power Clipping Interpolation filter ASRC HPF Compensate filter Compensate filter Power Limt (DRC) Address Register B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0] 0X00 SCTL1 IF[2] IF[1] IF[0] LREXC Reserved NGE 0X01 SCTL 2 BCLK_SEL Reserved FS[1] FS[0] PMF[3] PMF[2] PMF[1] PMF[0] 0X02 SCTL 3 A_SEL_FAULT HPB LV_UVSEL SW_RSTB MUTE CM1 CM2 Reserved 0X03 MVOL MV[7] MV[6] MV[5] MV[4] MV[3] MV[2] MV[1] MV[0] 0X04 C1VOL C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[0] 0X05 C2VOL C2V[7] C2V[6] C2V[5] C2V[4] C2V[3] C2V[2] C2V[1] C2V[0] 0X06 HVUV DIS_HVUV DIS_LVUV_FADE DIS_OV_FADE Reserved HVUVSEL[2] HVUVSEL[1] HVUVSEL[0] 0X07 SCTL 4 C1MX_EN C2MX_EN PC1_EN PL1_EN MONO_EN PC2_EN PL2_EN Reserved 0X08 LAR LA[3] LA[2] LA[1] LA[0] LR[3] LR[2] LR[1] LR[0] 0X09 TEST Prohibited 0X0A Reserved Reserved 0X0B Reserved Reserved 0X0C STATUS Prohibited 0X0D ACFG Prohibited 0X0E TM_CTRL Prohibited 0X0F PWM_CTRL Prohibited 0X11 ATT ATT[7] ATT[6] ATT[6] ATT[4] ATT[3] ATT[2] ATT[1] ATT[0] 0X11 ATM ATM[7] ATM[6] ATM[5] ATM[4] ATM[3] ATM[2] ATM[1] ATM[0] 0X12 ATB ATB[7] ATB[6] ATB[5] ATB [4] ATB [3] ATB [2] ATB [1] ATB [0]
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 27/52 0X13 PCT PCT[7] PCT[6] PCT[5] PCT[4] PCT[3] PCT[2] PCT[1] PCT[0] 0X14 PCM PCM[7] PCM[6] PCM[5] PCM[4] PCM[3] PCM[2] PCM[1] PCM[0] 0X15 PCB PCB[7] PCB[6] PCB[5] PCB [4] PCB [3] PCB [2] PCB [1] PCB [0] 0X16 SCTL5 NG_CNT_SEL[1] NG_CNT_SEL[0] Reserved DIS_ZD _FADE FADE_SPEED [1] FADE_SPEED [0] NG_GAIN[1] NG_GAIN[0] 0X17 VFT MV_FT[1] MV_FT[0] C1V_FT[1] C1V_FT[0] C2V_FT[1] C2V_FT[0] Reserved 0X18 DTC DTC_EN DTC_TH[1] DTC_TH[0] DTC_RATE[1] DTC_RATE[0] Reserved 0X19 Reserved Reserved 0X1A NGALT NGALT[7] NGALT[6] NGALT[5] NGALT[4] NGALT[3] NGALT[2] NGALT[1] NGALT[0] 0X1B NGALM NGALM[7] NGALM[6] NGALM[5] NGALM[4] NGALM[3] NGALM[2] NGALM[1] NGALM[0] 0X1C NGALB NGALB[7] NGALB [6] NGALB [5] NGALB [4] NGALB [3] NGALB [2] NGALB [1] NGALB [0] 0X1D NGRLT NGRLT[7] NGRLT[6] NGRLT[5] NGRLT[4] NGRLT[3] NGRLT[2] NGRLT[1] NGRLT[0] 0X1E NGRLM NGRLM[7] NGRLM[6] NGRLM[5] NGRLM[4] NGRLM[3] NGRLM[2] NGRLM[1] NGRLM[0] 0X1F NGRLB NGRLB[7] NGRLB [6] NGRLB[5] NGRLB[4] NGRLB [3] NGRLB [2] NGRLB [1] NGRLB [0] 0X20 DRC_ECT DRC_ECT[7] DRC_ECT[6] DRC_ECT[5] DRC_ECT[4] DRC_ECT[3] DRC_ECT[2] DRC_ECT[1] DRC_ECT[0] 0X21 DRC_ECB DRC_ECB[7] DRC_ECB[6] DRC_ECB[5] DRC_ECB[4] DRC_ECB[3] DRC_ECB[2] DRC_ECB[1] DRC_ECB[0] 0X22 RTT RTT[7] RTT[6] RTT[5] RTT[4] RTT[3] RTT[2] RTT[1] RTT[0] 0X23 RTM RTM[7] RTM[6] RTM[5] RTM[4] RTM[3] RTM[2] RTM[1] RTM[0] 0X24 RTB RTB[7] RTB[6] RTB[5] RTB [4] RTB [3] RTB [2] RTB [1] RTB [0] 0X25 DEVICE ID Device code Version code 0X26 RAM1_ CFADDR Prohibited 0X27 RAM1_ A1CF1 Prohibited 0X28 RAM1_ A1CF2 Prohibited 0X29 RAM1_ A1CF3 Prohibited 0X2A RAM1_ CFRW Prohibited 0X2B Wide Band setting Reserved FIR2_EN ANTI_LC_EN ANTI_ALIAS_EN Reserved 0X2C MBIST Prohibited 0X2D ERROR UVBAR OCSOUT HITOUT UVOUT DC_ERR_N CK_ERR_N OVP Reserved 0X2E MK_H MK_HBYTE[7] MK_HBYTE[6] MK_HBYTE[5] MK_HBYTE[4] MK_HBYTE[3] MK_HBYTE[2] MK_HBYTE[1] MK_HBYTE[0] 0X2F MK_L MK_LBYTE[7] MK_LBYTE[6] MK_LBYTE[5] MK_LBYTE[4] MK_LBYTE[3] MK_LBYTE[2] MK_LBYTE[1] MK_LBYTE[0]
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 28/52 Detail Description for Register In this section, please note that the highlighted columns are the default value of these tables. If no highlighted, it is because the default setting of this bit is determined by external pin. Address 0X00 : State control 1 AD82010 support multiple serial data input formats including I2S, Left-alignment and Right-alignment. These formats is chosen by user via bit7~bit5 of address 0. BIT NAME DESCRIPTION VALUE FUNCTION B[7:5] IF[2:0] Input Format
000 I2S 16-24 bits
001 Left-alignment 16-24 bits
010 Right-alignment 16 bits
011 Right-alignment 18 bits
100 Right-alignment 20 bits
101 Right-alignment 24 bits
B[4] LREXC Left/Right (L/R) Channel Exchanged
0 No exchanged
1 L/R exchanged
B[3] X Reserved B[2] X Reserved B[1] X Reserved B[0] NGE Noise Gate Enable
0 Disable
1 Enable
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 29/52 Address 0X01 : State control 2 AD82010 has built-in PLL, multiple MCLK/FS ratio is supported. Detail setting is shown as the above table. BIT NAME DESCRIPTION VALUE FUNCTION B[7] BCLK_SEL BCLK System enable B[6] X Reserved B[5:4] FS Sampling Frequency 00 32/44.1/48kHz 01 64/88.2/96kHz 10 128/176.4/192kHz 11 128/176.4/192kHz Multiple MCLK/FS ratio setting table BIT NAME DESCRIPTION VALUE B[5:4]=00 B[5:4]=01 B[5:4]=1x B[3:0] PMF[3:0] MCLK/Fs setup when PLL is not bypassed 0000 1024x 512x 256x 0001 Reset Default (64x) Reset Default (64x) Reset Default (64x) 0010 128x 128x 128x 0011 192x 192x 192x 0100 256x 256x 256x 0101 384x 384x Reserved 0110 512x 512x 0111 576x Reserved 1000 768x 1001 1024x
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 30/52 Address 0X02 : State control 3 The FAULT of AD82010 is a dual function pin. It is treated as an I2C device address selection input when bit 7 is set as low. It will become as a FAULT output pin when bit 7 is set as high. To prevent the DC current from damaging the speaker, a high pass filter (3dB frequency=1Hz) is built into the AD82010. It can be enabled or disabled by bit 6 of address 0X02. AD82010 has a mute function which includes master mute and individual channel mute modes. When the master mute mode is enabled, both left and right processing channels are muted. On the other hand, either channel can be muted by using the channel mute mode. When the mute function is enabled or disabled, the fade-out or fade-in process will be initiated. AD82010 frequency response will become higher at high frequency area with PV CC lower 12V.Turning on the compensate filter will can adjust the frequency response more flat a t high frequency area while PV CC lower 12V. BIT NAME DESCRIPTION VALUE FUNCTION B[7] A_SEL_FAULT I2C address selection or FAULT output I2C device address selection
1 ERROR output
B[6] HPB DC Blocking HPF Bypass
0 Enable
1 Disabled
B[5] LV_UVSEL LV Under Voltage Selection 0 2.6V 1 2.2V B[4] SW_RSTB Software reset
0 Reset
1 Normal operating
B[3] MUTE Master Mute
0 Un-Mute
1 Mute
B[2] CM1 Channel 1 Mute B[1] CM2 Channel 2 Mute B[0] COMP_EN Frequency Compensate filter
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 31/52 Address 0X03 : Master volume AD82010 supports both master -volume and channel -volume control for the stereo processing channels. Both master volume control (Address 0X03) and channel volume (Address 0X04 and 0X05 ) settings range from +12dB ~ -102dB. Given master volume level, say, Level A (in dB unit) and channel volume level, say Level B (in dB unit), the total volume equals to Level A plus with Level B and its range is from +24dB ~ -102dB, i.e., -103dB ≦ Total Volume ( Level A + Level B ) ≦ +24dB. BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] MV[7:0] Master Volume 00000000 +12dB 00000001 +11.5dB 00000010 +11dB ︰ ︰ 00010111 0.5dB 00011000 0dB 00011001 -0.5dB ︰ ︰ 11100110 -103dB 11100101 -∞dB ︰ ︰ 11111111 -∞dB Address 0X04 : Channel1 volume BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] C1V[7:0] Channel 1 Volume 00000000 +12dB 00000001 +11.5dB ︰ ︰ 00010100 2dB ︰ ︰ 00011000 0dB 00011001 -0.5dB ︰ ︰ 11100110 -103dB 11100101 -∞dB ︰ ︰ 1111111 -∞dB
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 32/52 Address 0X05 : Channel2 volume BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] C2V[7:0] Channel 2 Volume 00000000 +12dB 00000001 +11.5dB ︰ ︰ 00010100 2dB ︰ ︰ 00011000 0dB 00011001 -0.5dB ︰ ︰ 11100110 -103dB 11100101 -∞dB ︰ ︰ 1111111 -∞dB
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 33/52 Address 0X06 : Under voltage selection for high voltage supply AD82010 provides HV under voltage detection which can be enable or disable via bit 7. The under -voltage detection level is programmable via bit2~ bit0. Once the output stage voltage drops below the default value (see table), AD82010 will fade out audio signals to turn off the speaker. If user want to have an application with PVCC is lower than 10V, user can set HV under voltage disable or set lower under voltage level. AD82010 also provides OV fade function . User can select fade or not fade for OV via bit5. BIT NAME DESCRIPTION VALUE FUNCTION B[7] DIS_HVUV Disable HV Under Voltage Circuit
1 Disable
B[6] DIS_LVUV_FADE Disable LVUV Fade Selection
0 Fade
1 No fade
B[5] DIS_OV_FADE Disable over voltage fade B[4:3] X Reserved B[2:0] HVUVSEL[2:0] HV Under Voltage Selection (Active) 000 4V 001 8.2V 010 9.7V 011 13.2V 100 15.5V 101 19.5V Others 4V
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 34/52 Address 0X07 : State control 4 AD82010 provides channel mix, power clipping, and dynamic range control (DRC) function. These functions can be enable or not as the following table. BIT NAME DESCRIPTION VALUE FUNCTION B[7] C1MX_EN Channel1 Mixing Enable B[6] C2MX_EN Channel2 Mixing Enable B[5] PC1_EN CH1 Power Clipping enable B[4] PL1_EN CH1 Power limit enable B[3] MONO_EN MONO or Stereo configure
0 Stereo
1 MONO
B[2] PC2_EN CH2 Power Clipping enable B[1] PL2_EN CH2 Power limit enable B[0] X Reserved AD82010 also provides MONO register via bit 3 of address 0X07. Besides this MONO register, address 0X2E and 0X2F should be setting to enter MONO configuration. The output configuration shall be right connected before Mono configuration enable. That’s possible to damage chips due to channel shoot-through if the wrong output configuration is connected.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 35/52 Address 0X08 : Attack rate and Release rate for Dynamic Range Control (DRC) The attack/release rates of AD82010 are defined as following table, BIT NAME DESCRIPTION VALUE FUNCTION B[7:5] LA[3:0] DRC Attack Rate 0000 3 dB/ms 0001 2.667 dB/ms 0010 2.182 dB/ms 0011 1.846 dB/ms 0100 1.333 dB/ms 0101 0.889 dB/ms 0110 0.4528 dB/ms 0111 0.2264 dB/ms 1000 0.15 dB/ms 1001 0.1121 dB/ms 1010 0.0902 dB/ms 1011 0.0752 dB/ms 1100 0.0645 dB/ms 1101 0.0563 dB/ms 1110 0.0501 dB/ms 1111 0.0451 dB/ms B[3:0] LR[3:0] DRC Release Rate 0000 0.5106 dB/ms 0001 0.1371 dB/ms 0010 0.0743 dB/ms 0011 0.0499 dB/ms 0100 0.0360 dB/ms 0101 0.0299 dB/ms 0110 0.0264 dB/ms 0111 0.0208 dB/ms 1000 0.0198 dB/ms 1001 0.0172 dB/ms 1010 0.0147 dB/ms 1011 0.0137 dB/ms 1100 0.0134 dB/ms 1101 0.0117 dB/ms 1110 0.0112 dB/ms 1111 0.0104 dB/ms
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 36/52 Address 0X10 : Top 5 bits of attack threshold for Dynamic Range Control (DRC) The AD82010 provides dynamic range control function. When the input RMS exceeds the programmable attack threshold value, the output power will be limited by this threshold power level via gradual gain reduction. Attack threshold is defined by 24-bit representation composed of registers controlled by I2C. The device addresses of DRC attack threshold are 0X10, 0X11, and 0X12. BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] ATT[7:0] Top 8 Bits of Attack Threshold X User programmed 00100000 0dB Address 0X11 : Middle 8 bits of attack threshold BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] ATM[7:0] Middle 8 Bits of Attack Threshold X User programmed 00000000 0dB Address 0X12 : Bottom 8 bits of attack threshold BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] ATB[7:0] Bottom 8 bits of attack threshold X User programmed 00000000 0dB
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 37/52 Address 0X13 : Top 8 bits of power clipping The AD82010 provides power clipping function to avoid excessive signal that may destroy loud speaker. The power clipping level is defined by 24 -bit representation composed of registers controlled by I2C. The device addresses of power clipping threshold are 0X13, 0X14, and 0X15. BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] PCT[7:0] Top 8 Bits of Power Clipping Level X User programmed 00100000 0dB Address 0X14 : Middle 8 bits of power clipping BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] PCM[7:0] Middle 8 Bits of Power Clipping Level X User programmed 00000000 0dB Address 0X15 : Bottom 8 bits of power clipping level BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] PCB[7:0] Bottom 8 Bits of Power Clipping Level X User programmed 00000000 0dB The following table shows the power clipping level’s numerical representation. Sample calculation for power clipping Max amplitude dB Linear Decimal Hex (3.21 format) Gain 0 1 2097152 200000 Gain*0.707 -3 0.707 1482680 169FB8 Gain*0.5 -6 0.5 1048576 100000 Gain*L x L=10(x/20) D=2097152xL H=dec2hex(D) Note: Gain is the closed loop gain of AD82010, the value is 30(±5%) with 8ohm load. If the max amplitude is larger than PVCC, max amplitude change to PVCC.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 38/52 Address 0X16 : State control 5 When receiving signal sample points less than noise gate attack level for the time more than noise gate count time, noise gate function will active. The noise gate count time can be programmed via bit [7:6].User can change noise gate gain via bit1~ bit0. When noise gate function occurs, input signal will multiply noise gate gain (x1/8, x1/4 x1/2, x0). User can select fade out or not via bit 4. AD82010 provide 4 kinds of fade speed(1.25ms,2.5ms,5ms,10ms), user can select most suitable fade speed for their system. BIT NAME DESCRIPTION VALUE FUNCTION B[7:6] NG_CNT_SEL Noise gate count time selection 00 43ms @fs:48K 01 86ms @fs:48K 10 172ms @fs:48K 11 344ms @fs:48K B[4] DIS_NG_FADE Disable Noise Gate Fade B[3:2] FADE_SPEED Fade in/out speed selection 00 1.25ms 01 2.5ms 10 5ms 11 10ms B[1:0] NG_GAIN Noise Gate Detection Gain 00 x1/8 01 x1/4 10 x1/2
11 Mute
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 39/52 Address 0X17 : Volume fine tune AD82010 supports both master-volume fine tune and channel-volume control fine tune modes. Both volume control settings range from 0dB ~ -0.375dB and 0.125dB per step. Note that the master volume fine tune is added to the individual channel volume fine tune as the total volume fine tune. BIT NAME DESCRIPTION VALUE FUNCTION B[7:6] MV_FT Master Volume Fine Tune 00 0dB 01 -0.125dB 10 -0.25dB 11 -0.375dB B[5:4] C1V_FT Channel 1 Volume Fine Tune 00 0dB 01 -0.125dB 10 -0.25dB 11 -0.375dB B[3:2] C2V_FT Channel 2 Volume Fine Tune 00 0dB 01 -0.125dB 10 -0.25dB 11 -0.375dB B[1:0] X Reserved
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 40/52 Address 0X18 : Dynamic Temperature Control (DTC) AD82010 supports dynamic temperature control. The table describes the setting of DTC. BIT NAME DESCRIPTION VALUE FUNCTION B[7] DTC_EN DTC Enable B[6:5] DTC_TH DTC Threshold 00 110 oC 01 120 oC 10 130 oC 11 140 oC B[4:3] DTC_RATE DTC Attack and Release Rate 00 1dB/sec 01 0.5dB/sec 10 0.33dB/sec 11 0.25dB/sec B[2:0] X Reserved Release threshold is always 10 oC smaller than attack threshold. For example: DTC threshold (attack threshold) =130 oC, the release threshold = 120 oC. DTC threshold (attack threshold) =120 oC, the release threshold = 110 oC. If junction temperature (Tj) exceeds 130 oC, amplifier gain will be lowered to timing of 1dB/sec. If amplifier gain falls and junction temperature (Tj) turns into less than 130 oC and larger than 120 oC, the gain will not increase or decrease. If amplifier gain falls and junction temperature (Tj) turns into less than 120 oC, amplifier gain will be raised to timing of 1dB/sec.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 41/52 Address 0X1A : Top 8 bits of noise gate attack level When both left and right signals have 2048 consecutive sample points less than the programmable noise gate attack level, the audio signal will multiply noise gate gain, which can be set at x1/8, x1/4, x1/2, or zero if the noise gate function is enabled. Noise gate attack level is defined by 24 -bit representation composed of registers controlled by I2C. The device addresses of noise gate attack level are 0X1A, 0X1B, and 0X1C BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] NGALT[7:0] Top 8 Bits of Noise Gate Attack Level X User programmed 00000000 -110dB Address 0X1B : Middle 8 bits of noise gate attack level BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] NGALM[7:0] Middle 8 Bits of Noise Gate Attack Level X User programmed 00000000 -110dB Address 0X1C : Bottom 8 bits of noise gate attack level BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] NGALB[7:0] Bottom 8 Bits of Noise Gate Attack Level X User programmed 00011010 -110dB
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 42/52 Address 0X1D : Top 8 bits of noise gate release level After entering the noise gating status, the noise gain will be removed whenever AD82010 receives any input signal that is more than the noise gate release level. Noise gate release level is defined by 24 -bit representation composed of registers controlled by I2C. The device addresses of noise gate release level are 0X1D, 0X1E, and 0X1F. BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] NGRLT[7:0] Top 8 Bits of Noise Gate Release Level X User programmed 00000000 -100dB Address 0X1E : Middle 8 bits of noise gate release level BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] NGRLM[7:0] Middle 8 Bits of Noise Gate Release Level X User programmed 00000000 -100dB Address 0X1F : Bottom 8 bits of noise gate release level BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] NGRLB[7:0] Bottom 8 Bits of Noise Gate Release Level X User programmed 01010011 -100dB The following table shows the noise gate attack and release threshold level’s numerical representation. Sample calculation for noise gate attack and release level Input amplitude (dB) Linear Decimal Hex (1.23 format) 0 1 8388607 7FFFFF -100 10-5 83 53 -110 10-5.5 26 1A X L=10(x/20) D=8388607xL H=dec2hex(D)
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 43/52 Address 0X20 : Top 8 bits of DRC energy coefficient BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] DRC_ECT [7:0] Top 8 Bits of DRC Energy Coefficient X User programmed 00000000 1/2048 Address 0X21 : Bottom 8 bits of DRC energy coefficient BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] DRC_ECB [7:0] Bottom 8 Bits of DRC Energy Coefficient X User programmed 00010000 1/2048 x2[n] DRC_EC Z-1 xrms[n] 1-DRC_EC The above figure illustrates the digital processing of calculating RMS signal power. In this processing, a DRC energy coefficient is required, which can be programmed for different frequency range. Energy coefficient is defined by 16-bit representation composed of registers controlled by I2C. The device addresses of DRC energy coefficient are 0X20, and 0X21. The following table shows the DRC energy coefficient numerical representation. Sample calculation for DRC energy coefficient DRC energy coefficient dB Linear Decimal Hex {1,b0, DRC_ECT[6:0], DRC_ECB,8’b0} (1.23 format) 1 0 1 8388352 7FFF00 1/256 -48.2 1/256 32768 8000 1/2048 -66.2 1/2048 4096 1000 L x L=10(x/20) D=8388352xL H=dec2hex(D)
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 44/52 Address 0X22 : Top 8 bits of release threshold for Dynamic Range Control (DRC) After AD82010 has reached the attack threshold, its output power will be limited to that level. The output power level will be gradually adjusted to the programmable release threshold level. Release threshold is defined by 21-bit representation composed of registers controlled by I2C. The device addresses of release threshold are 0X22, 0X23, and 0X24. BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] RTT[7:0] Top 8 Bits of Release Threshold X User programmed 00001000 -6dB Address 0X23 : Middle 8 bits of release threshold BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] RTM[7:0] Middle 8 Bits of Release Threshold X User programmed 00000000 -6dB Address 0X24 : Bottom 8 bits of release threshold BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] RTB[7:0] Bottom 8 Bits of Release Threshold X User programmed 00000000 -6dB The following table shows the attack and release threshold’s numerical representation. Sample calculation for attack and release threshold Power dB Linear Decimal Hex (3.21 format) (Gain^2)/R 0 1 2097152 200000 (Gain^2)/2R -3 0.5 1048576 100000 (Gain^2)/4R -6 0.25 131072 80000 ((Gain^2)/R)*L x L=10(x/10) D=2097152xL H=dec2hex(D)
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 45/52 To best illustrate the dynamic range control function, please refer to the following figure. GAIN Under release threshold Touch attack threshold Attack threshold Attack threshold Release threshold Release threshold Attack threshold Attack threshold Release threshold Release threshold Δ gain1 Δ gain2 Δ t1 Δ t2 Attack rate=Δ gain1/Δt1 Release rate=Δ gain2/Δt2 INPUTOUTPUT
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 46/52 Address 0X2B, Wide Band Setting Register BIT NAME DESCRIPTION VALUE FUNCTION B[7:4] X Reversed B[3] FIR2_EN FIR2 filter B[2] ANTI_LC_EN ANTI LC filter B[1] ANTI_ALIAS_EN ANTI ALAIAS filter B[0] X Reversed Fs=96KHz input, please set address 0X2B=”0X02” to extend frequency response from 20kHz to 40KHz if Wide Band Setting spec. is request. We called this “Wide Band Setting enable”. ColorSweep Trace Line Style Thick Data Axis Comment 1 1 Red Solid 3 Anlr.Level A Left 24V hi res enable 2 1 Blue Solid 3 Anlr.Level A Left 24V hi res disable 20 40k 50 100 200 500 1k 2k 5k 10k 20k Hz -50 +10 -47.5 -45 -42.5 -40 -37.5 -35 -32.5 -30 -27.5 -25 -22.5 -20 -17.5 -15 -12.5 -10 -7.5 -2.5 +2.5 +7.5 d B r A Wide Band Setting disable 0X2B=”0X0E” Wide Band Setting enable 0X2B=”0X02”
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 47/52 Address 0X2D, Protection Status Register The protection registers will show what kind of protection occurs. BIT NAME DESCRIPTION VALUE FUNCTION B[7] UVBAR Under voltage occur
1 Normal
0 Occurred
B[6] OCSOUT Over current occur B[5] HITOUT Over temperature occur B[4] UVOUT Under voltage occur B[3] DC_ERR_N DC detection error B[2] CK_ERR_N Clock detection error B[1] OVP Over voltage occur B[0] X Reversed
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 48/52 Address 0X2E : Mono Key High Byte AD82010 provide a protection method to enter mono mode. Besides setting MONO_EN register high, it needs to set address 0X2E value to 0X30 and address 0X2F value to 0X06 for mono application. Otherwise, AD82010 will be stereo mode. BIT NAME DESCRIPTION VALUE FUNCTION B[7:0] MK_HBYTE[7:0] Mono key high byte 0000_0000 Stereo X Stereo 0011_0000 MONO Address 0X2F : Mono Key Low Byte BIT NAME DESCRIPTION VALUE FUNCTION B[:0] MK_LBYTE[7:0 Mono key high byte 0000_0000 Stereo X Stereo 0000_0110 MONO
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 49/52 Package Dimensions TSSOP-24(E) (173 mil) SIDE VIEW L PIN#1 MARK E E1 b TOP VIEW c DETAIL A A D e 1 12 1324 Exposed pad Min Max Dimension in mm A 1.00 1.20 Min Max A1 0.00 0.15 D2 3.95 4.75 b 0.19 0.30 E2 2.70 3.10 c 0.09 0.20 D 7.70 7.90 E 4.30 4.50 E1 6.30 6.50 e L 0.45 0.75
0.65 BSC
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 50/52
Revision History
0.1 2017.05.05 Initial version. 0.2 2017.08.24 1. Remove DIS_LVUV_FADE 2. Dis_HVUV default value 1.0 2017.11.08 1. Remove “Preliminary” 1.1 2017.11.09 1.PVDDPVCC 2.PDSD 1.2 2018.01.10 1. Add “Protection Status Register” Table. 2. Modify Register Table. (0x2D, Error) 3. Modify “Power on sequence” figure. 4. Modfiy “Absolute Maximum Ratings” Table. (Add ESD SPEC.) 1.3 2018.02.22 1.Modify “Power on sequence” figure. 2.Add Note 7 3.Modify “Register Table” .( A_SEL_FAULT 4.Modify “Pin Description”. (A_SEL_FAULT at address 0x0D -> 0x02) 1.4 2018.04.25 1.Modify “Sample calculation for power clipping “ Table (Decimal Value: 524288 change to 2097152) 2.Modify “Absolute Maximum Ratings” Table.(Add Pd spec.) 3.Change T9 time 20ms to 150ms 4.Change T7 time 0.1ms to 150ms 1.5 2018.09.06 1. Modify “General Electrical Characteristics” Table (add IQ(DVDD) spec.) 2.Modify the application circuit. 1.6 2019.05.09 1. Add “output power vs. PVCC” figure.. 2. Application circuit update, added snubber circuit into for EMI option components. 3. Added 0X2B, Wide Band Setting register description into. 1.7 2019.10.01 Add power on sequence for FS=96kHz or 192KHz.
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 51/52 1.8 2019.11.07 Modify Fs=96KHz power on sequence. 1.9 2019.01.02 Add System Clock Timing. 2.0 2021.04.13 Modify Register Table at Address 0X06. Modify Address 0X06 data. 2.1 2021.05.24 Modify Power on Sequence. 2.2 2021.08.18 Modify E-TSSOP 24L (173mil) package Dimensions D2 min value
Elite Semiconductor Microelectronics Technology Inc. Publication Date: Aug 2021 Revision: 2.2 52/52 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failu re, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.