AD8200

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REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD8200 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 High Common-Mode Voltage, Single Supply Difference Amplifier FUNCTIONAL BLOCK DIAGRAM SOIC (R) Package DIE Form

FEATURES

High Common-Mode Voltage Range –2V to +24V at a

5 V Supply Voltage

Operating Temperature Range Die: –40/H11543C to +150/H11543C 8-Lead SOIC: –40 /H11543C to +125/H11543C Supply Voltage Range: 4.7 V to 12 V Low-Pass Filter (One Pole or Two Pole) EXCELLENT AC AND DC PERFORMANCE 15 /H9262V//H11543C Max Offset Drift 20 ppm//H11543C Max Gain Drift 80 dB CMRR Min DC to 10 kHz PLATFORMS Transmission Control Diesel Injection Control Engine Management Semi-Active Suspension Control Vehicle Dynamics Control GENERAL DESCRIPTION The AD8200 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage. The input CMV range extends from –2 V to +24 V at a typical supply voltage of 5 V. The AD8200 is offered in die and packaged form. Both package options are specified over wide temperature ranges, making the AD8200 well suited for use in many automotive platforms. The SOIC package is specified over a temperature range of –40 °C to +125°C. The die is specified from –40 °C to +150°C. –IN GND A1 A2 +IN NC +VS OUT AD8200 OUTPUT INDUCTIVE LOAD POWER DEVICE

4 TERM

COMMON NC = NO CONNECT Figure 1. High-Line Current Sensor formance that keeps errors to a minimum in the user’s system. mum CMRR of 80 dB from dc to 10 kHz. filter applications, and for establishing gains other than 20. Figure 2. Low-Line Current Sensor

REV. 0–2– AD8200–SPECIFICATIONS SINGLE SUPPLY AD8200 SOIC AD8200 DIE Parameter Condition Min Typ Max Min Typ Max Unit SYSTEM GAIN Initial 20 20 Error V O ≥ 0.1 V dc –1 +1 –1 +1 % vs. Temperature 10 20 25 30 ppm/ °C OFFSET VOLTAGE Offset Voltage (RTI) V CM = 0.15 V –1 +1 –1 +1 mV vs. Temperature 6 15 12 25 µV/°C INPUT Input Impedance Differential 320 400 480 320 400 480 k Ω Common-Mode 160 200 240 160 200 240 k Ω CMV Continuous –2 +24 –2 +24 V Common-Mode Rejection 1 VCM = 10 V f = 1 kHz 80 80 dB f = 10 kHz2 80 80 dB PREAMPLIFIER Gain 10 10 Gain Error –1 +1 –1 +1 % Output Voltage Range 0.02 4.8 0.02 4.8 V Output Resistance 97 100 103 97 100 103 k Ω OUTPUT BUFFER Gain 2 2 Gain Error –1 +1 –1 +1 % Output Voltage Range 0.02 4.8 0.02 4.8 V Output Resistance 2 2 Ω DYNAMIC RESPONSE 3 dB Bandwidth 30 50 30 50 kHz Slew Rate 0.22 0.22 V/ µs NOISE

0.1 Hz to 10 Hz 10 10 µV p-p

Spectral Density, 1 kHz, RTI 300 300 nV/ √Hz POWER SUPPLY Operating Range 4.7 12 4.7 12 V Quiescent Current vs. Temp V O = 0.1 V dc 0.25 1 0.25 1 mA PSRR V S = 4.7 V to 12 V 75 80 75 80 dB TEMPERATURE RANGE For Specified Performance –40 +125 –40 +150 °C NOTES 1Source Imbalance < 2 Ω. 2The AD8200 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 k Ω resistor, even the small amounts of pin- to-pin capacitance between Pins 1, 8 and 3, 4 may couple an input common-mode signal larger than the greatly attenuated preampl ifier output. The effect of pin-to- pin coupling may be neglected in all applications using filter capacitors at Node 3. Specifications subject to change without notice. (TA = 25/H11543C, VS = 5 V, VCM = 0 V, RL = 10 k/H9024, Pin 5 to ground, unless otherwise noted.)

REV. 0 AD8200 –3– ABSOLUTE MAXIMUM RATINGS * *Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option AD8200R –40 °C to +125°C Plastic SOIC SO-8 AD8200CHIPS –40 °C to +150°C DIE Form PIN CONFIGURATION TOP VIEW (Not to Scale) NC = NO CONNECT –IN GND +IN NC S OUT AD8200 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE METALLIZATION PHOTOGRAPH +IN –IN 1 GND +VS OUT5 A24

REV. 0 SUPPLY VOLTAGE – Volts 25 3 POSITIVE COMMON-MODE RANGE – Volts –12 NEGATIVE COMMON-MODE RANGE – Volts –10 +VCM –VCM TPC 1. Input Common-Mode Range vs. Supply SUPPLY VOLTAGE – Volts –35 2 53 OUTPUT VOLTAGE – mV –30 –25 –20 –15 –10 RL = RL = 10k/H9024 TO GND TPC 2. Output Voltage – VS vs. Supply LOAD RESISTANCE – /H9024 OUTPUT VOLTAGE – Volts 100 1k 10k TPC 3. Output Voltage Swing vs. Load Resistance AD8200–Typical Performance Characteristics –4– (TA = 25/H11543C, VS = 5 V, VCM = 0 V, RL = 10 k/H9024 unless otherwise noted.) FREQUENCY – Hz –20 GAIN – dB 10k 100k 1M –15 –10 TPC 4. Gain vs. Frequency FREQUENCY – Hz 100 CMRR – dB 1k 10k 1M 100 100k TPC 5. Common-Mode Rejection vs. Frequency FREQUENCY – Hz 100 PSRR – dB 100 10k 1k 100k TPC 6. Power Supply Rejection vs. Frequency

REV. 0 AD8200 –5– THEORY OF OPERATION The AD8200 consists of a preamp and buffer arranged as shown in Figure 3. Like-named resistors have equal values. The preamp incorporates a dynamic bridge (subtractor) circuit. Identical networks (within the shaded areas), consisting of R A, RB, RC, and RG, attenuate input signals applied to Pins 1 and 8. Note that when equal amplitude signals are asserted at inputs 1 and 8, and the output of A1 is equal to the common potential (i.e., zero), the two attenuators form a balanced-bridge network. When the bridge is balanced, the differential input voltage at A1 and thus its output, will be zero. Any common-mode voltage applied to both inputs will keep the bridge balanced and the A1 output at zero. Because the resistor networks are carefully matched, the common-mode signal rejec- tion approaches this ideal state. However, if the signals applied to the inputs differ, the result is a difference at the input to A1. A1 responds by adjusting its output to drive R B, by way of RG, to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. By attenuating voltages at Pins 1 and 8, the amplifier inputs are held within the power supply range, even if Pin 1 and Pin 8 input levels exceed the supply, or fall below Common (Ground.) The input network also attenuates normal (differential) mode volt- ages. R C and R G form an attenuator that scales A1 feedback, forcing large output signals to balance relatively small differen- tial inputs. The resistor ratios establish the preamp gain at ten. Because the differential input signal is attenuated, and then amplified to yield an overall gain of ten, the amplifier A1 oper- ates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to Pins 1 and 8. RCM RCM (TRIMMED) 100k/H9024 RA –IN RGRC RB RA RC RB RG +IN COM RF RF AD8200 Figure 3. Simplified Schematic ratio-trimmed for high accuracy. user to incorporate a low-pass filter prior to the output buffer.

APPLICATIONS

The AD8200 difference amplifier is intended for applications where it is required to extract a small differential signal in the presence of large common-mode voltages. The input resistance is nominally 200 kΩ, and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground. The open collector output stage will source current to within 20 mV of ground. TEK RUN: 2.5MS/s HI RES VOUT, RL = 10k/H9024 T VIN CH1 500mV/H902450mV/H9024 M 20/H9262s CH1 1.5VCH2 TPC 7. Pulse Response TEK RUN: 2.5MS/s AVERAGE VIN CH3 100mV VOUT, RL = 10k/H9024 MAGNIFIED VOUT CH1 1V CH 2 10mV M 20/H9262s CH1 1.36V TPC 8. Settling Time

device to withstand voltages below system ground. the low-impedance side of the input corrects for this error. Figure 4. 4–20 mA Current Loop Receiver lowered, raised, or finely calibrated.

2 GAIN =

Figure 5. Adjusting for Gains Less than 20 part’s use in very high-gain, dc-coupled applications. Figure 6. Adjusting for Gains Greater than 20 a trimpot and external resistor REXT. Figure 7. Incremental Gain Trim

adjustment and low-pass filtering. Figure 11. High-Line Current Sensor Interface. Gain = ×40, = 3.6 Hz, which provides about 30 dB of attenuation at 100 Hz. than half that needed for the single-pole filter. Figure 12. Illustration of 2-Pole Low-Pass Filtering R-C network in the output can significantly reduce the effect. lowering the high-frequency output impedance of the AD8200. LAG–CLAG combination as shown in Figure 13. Figure 13. Recommended Circuit for Driving CMOS A/D Dimensions shown in inches and (mm).