AD811ACHIPS

AD811_04 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

High Performance Video Op Amp AD811 Rev. E Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

140 MHz bandwidth (3 dB, G = +1)

120 MHz bandwidth (3 dB, G = +2)

35 MHz bandwidth (0.1 dB, G = +2)

2500 V/µs slew rate

25 ns settling time to 0.1% (for a 2 V step) 65 ns settling time to 0.01% (for a 10 V step) Excellent video performance (RL =150 Ω) 0.01% differential gain, 0.01° differential phase Voltage noise of 1.9 nV/√Hz Low distortion: THD = −74 dB @ 10 MHz Excellent dc precision: 3 mV max input offset voltage Flexible operation Specified for ±5 V and ±15 V operation ±2.3 V output swing into a 75 Ω load (VS = ±5 V)

APPLICATIONS

Video crosspoint switchers, multimedia broadcast systems HDTV compatible systems Video line drivers, distribution amplifiers ADC/DAC buffers DC restoration circuits Medical Ultrasound PET Gamma Counter applications GENERAL DESCRIPTION A wideband current feedback operational amplifier, the AD811 is optimized for broadcast-quality video systems. The −3 dB bandwidth of 120 MHz at a gain of +2 and the differential gain and phase of 0.01% and 0.01° (RL = 150 Ω) make the AD811 an excellent choice for all video systems. The AD811 is designed to meet a stringent 0.1 dB gain flatness specification to a band- width of 35 MHz (G = +2) in addition to low differential gain and phase errors. This performance is achieved whether driving one or two back-terminated 75 Ω cables, with a low power supply current of 16.5 mA. Furthermore, the AD811 is specified over a power supply range of ±4.5 V to ±18 V. (Continued on page 3) CONNECTION DIAGRAMS 5AD811 NC –IN +IN –VS +VS NC OUTPUT NC NC = NO CONNECT 00866-E-001 Figure 1. 8-Lead Plastic (N-8), CERDIP (Q-8), SOIC (R-8) Figure 2. 16-Lead SOIC (R-16) Figure 3. 20-Terminal LCC (E-20A) Figure 4. 20-Lead SOIC (R-20)

Rev. E | Page 2 of 20 TABLE OF CONTENTS Achieving the Flattest Gain Response at High Frequency.... 12

REVISION HISTORY

7/04—Data Sheet Changed from Rev. D to Rev. E

racy for wide dynamic range applications.

100 IRE

Figure 5. Differential Gain and Phase Figure 6. Frequency Response

Rev. E | Page 4 of 20 SPECIFICATIONS @ TA = +25°C, VS = ±15 V dc, RLOAD = 150 Ω, unless otherwise noted. Table 1. AD811J/A1 AD811S2 Parameter Conditions VS Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Small Signal Bandwidth (No Peaking) −3 dB G = +1 RFB = 562 Ω ±15 V 140 140 MHz G = +2 RFB = 649 Ω ±15 V 120 120 MHz G = +2 RFB = 562 Ω ±15 V 80 80 MHz G = +10 RFB = 511 Ω ±15 V 100 100 MHz 0.1 dB Flat G = +2 RFB = 562 Ω ±15 25 25 MHz R FB = 649 Ω ±15 35 35 MHz Full Power Bandwidth3 VOUT = 20 V p-p ±15 40 40 MHz Slew Rate VOUT = 4 V p-p ±15 400 400 V/µs V OUT = 20 V p-p ±15 2500 2500 V/µs Settling Time to 0.1% 10 V Step, AV = − 1 ±15 50 50 ns Settling Time to 0.01% 10 V Step, AV = − 1 ±15 65 65 ns Settling Time to 0.1% 2 V Step, AV = − 1 ±15 25 25 ns Rise Time, Fall Time RFB = 649, AV = +2 ±15 3.5 3.5 ns Differential Gain f = 3.58 MHz ±15 0.01 0.01 % Differential Phase f = 3.58 MHz ±15 0.01 0.01 Degree THD @ fC = 10 MHz VOUT = 2 V p-p, AV = +2 ±15 −74 −74 dBc Third-Order Intercept4 @ fC = 10 MHz ±15 36 36 dBm ±15 43 43 dBm INPUT OFFSET VOLTAGE ±5 V, ±15 V 0.5 3 0.5 3 mV T MIN to TMAX 5 5 mV Offset Voltage Drift 5 5 µV/°C INPUT BIAS CURRENT −Input ±5 V, ±15 V 2 5 2 5 µA TMIN to TMAX 15 30 µA +Input ±5 V, ±1 5 V 2 10 2 10 µA T MIN to TMAX 20 25 µA TRANSRESISTANCE TMIN to TMAX V OUT = ±10 V RL = ∞ ±15 V 0.75 1.5 0.75 1.5 MΩ RL = 200 Ω ±15 V 0.5 0.75 0.5 0.75 MΩ V OUT = ±2.5 V RL = 150 Ω ±5 V 0.25 0.4 0.125 0.4 MΩ 1 The AD811JR is specified with ±5 V power supplies only, with operation up to ±12 V. 2 See the Analog Devices military data sheet for 883B tested specifications. 3 FPBW = slew rate/(2 π VPEAK). 4 Output power level, tested at a closed-loop gain of two.

Rev. E | Page 5 of 20 AD811J/A1 AD811S2 Parameter Conditions Vs Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION VOS (vs. Common Mode) TMIN to TMAX VCM = ±2.5 V ±5 V 56 60 50 60 dB TMIN to TMAX VCM = ±10 V ±15 V 60 66 56 66 dB Input Current (vs. Common Mode) TMIN to TMAX 1 3 1 3 µA/V POWER SUPPLY REJECTION VS = ±4.5 V to ±18 V VOS TMIN to TMAX 60 70 60 70 dB +Input Current TMIN to TMAX 0.3 2 0.3 2 µA/V −Input Current TMIN to TMAX 0.4 2 0.4 2 µA/V INPUT VOLTAGE NOISE f = 1 kHz 1.9 1.9 nV/√Hz INPUT CURRENT NOISE f = 1 kHz 20 20 pA/√Hz OUTPUT CHARACTERISTICS Voltage Swing, Useful Operating Range3 ±5 V ±2.9 ±2.9 V ±15 V ±12 ±12 V Output Current TJ = 25°C 100 100 mA Short-Circuit Current 150 150 mA Output Resistance (Open Loop @ 5 MHz) 9 9 Ω INPUT CHARACTERISTIC +Input Resistance 1.5 1.5 MΩ −Input Resistance 14 14 Ω Input Capacitance +Input 7.5 7.5 pF Common-Mode Voltage Range ±5 V ±3 ±3 V ±15 V ±13 ±13 V POWER SUPPLY Operating Range ±4.5 ±18 ±4.5 ±18 V Quiescent Current ±5 V 14.5 16.0 14.5 16.0 mA ±15 V 16.5 18.0 16.5 18.0 mA TRANSISTOR COUNT Number of Transistors 40 40 1 The AD811JR is specified with ±5 V power supplies only, with operation up to ±12 V. 2 See the Analog Devices military data sheet for 883B tested specifications. 3 Useful operating range is defined as the output voltage at which linearity begins to degrade.

observe the derating curves in Figure 22 and Figure 25. 75 Ω cable and the cable’s far end is shorted to a power supply. Contact the factory for the latest dimensions. Figure 7. Metalization Photograph

Rev. E | Page 12 of 20 GENERAL DESIGN CONSIDERATIONS The AD811 is a current feedback amplifier optimized for use in high performance video and data acquisition applications. Because it uses a current feedback architecture, its closed-loop −3 dB bandwidth is dependent on the magnitude of the feed- back resistor. The desired closed-loop gain and bandwidth are obtained by varying the feedback resistor (R FB) to tune the bandwidth and by varying the gain resistor (RG) to obtain the correct gain. Table 3 contains recommended resistor values for a variety of useful closed-loop gains and supply voltages. Table 3. −3 dB Bandwidth vs. Closed-Loop Gain and flatness varies, to some extent, with feedback resistor tolerance. have different associated parasitic capacitance and inductance. those indicated are optimal for other resistor types. errors. Line lengths less than 1/4" are recommended. the resulting flatness is not affected by the length of the cable. paralleled capacitors) may be required in some cases.

in these errors and a slight improvement in gain flatness. performance can be achieved at much lower supplies as well. are plotted in Figure 45 and Figure 46, respectively. driving back-terminated 75 Ω cables. Figure 42. A Video Line Driver Operating at a Gain of +2 Figure 43. Closed-Loop Gain vs. Frequency, Gain = +2 Figure 44. Small Signal Pulse Response, Gain = +2, VS = ±15 V Figure 45. Differential Gain Error vs. Supply Voltage for Figure 46. Differential Phase Error vs. Supply Voltage for

maintained essentially constant—that is, independent of gain. drive a reverse-terminated load of 50 Ω or 75 Ω to ±2 V. these conditions is increased to ±9 V using ±12 V supplies. and fully symmetrical responses from the X and Y inputs. circuit operates from a ±12 V dual power supply. Figure 47. An 80 MHz Voltage-Controlled Amplifier

ential input X1−X2 is 0. This generates the second term. the bandwidth and damping factor to best suit the application. Figure 48. A Practical Video Keyer Circuit

Rev. E | Page 20 of 20 ORDERING GUIDE Model Temperature Range Package Description Package Option AD811AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package (PDIP) N-8 AD811ANZ1 −40°C to +85°C 8-Lead Plastic Dual In-Line Package (PDIP) N-8 AD811AR-16 −40°C to +85°C 16-LeadStandard Small Outline Package (SOIC) R-16 AD811AR-16-REEL −40°C to +85°C 16-LeadStandard Small Outline Package (SOIC) R-16 AD811AR-16-REEL7 −40°C to +85°C 16-LeadStandard Small Outline Package (SOIC) R-16 AD811AR-20 −40°C to +85°C 20-LeadStandard Small Outline Package (SOIC) R-20 AD811AR-20-REEL −40°C to +85°C 20-LeadStandard Small Outline Package (SOIC) R-20 AD811JR 0°C to +70°C 8-LeadStandard Small Outline Package (SOIC) R-8 AD811JR-REEL 0°C to +70°C 8-LeadStandard Small Outline Package (SOIC) R-8 AD811JR-REEL7 0°C to +70°C 8-LeadStandard Small Outline Package (SOIC) R-8 AD811JRZ1 0°C to +70°C 8-LeadStandard Small Outline Package (SOIC) R-8 AD811SQ/883B −55°C to +125°C 8-Lead Ceramic Dual In-Line Package (CERDIP) Q-8 5962-9313101MPA −55°C to +125°C 8-Lead Ceramic Dual In-Line Package (CERDIP) Q-8 AD811SE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier (LCC) E-20A 5962-9313101M2A −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier (LCC) E-20A AD811ACHIPS −40°C to +85°C DIE AD811SCHIPS −55°C to +125°C DIE 1 Z = Pb-free part. © 2004 A nalog Devices, Inc. All rig hts reserved. Trademarks and regis- tered trade marks are the property of their respective owners . C00866–0–7/04(E)