AD8110-EB

AD8111ASTZ AD | Alldatasheet

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REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD8110/AD8111 Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

260 MHz, 16 /H11547 8 Buffered

FEATURES

16 /H11547 8 High-Speed Nonblocking Switch Arrays AD8110: G = +1 AD8111: G = +2 Serial or Parallel Switch Array Control Serial Data Out Allows “Daisy Chaining” of Multiple Crosspoints to Create Larger Switch Arrays Pin-Compatible with AD8108/AD8109 8 /H11547 8 Switch Arrays For a 16 /H11547 16 Array See AD8116 Complete Solution Buffered Inputs Eight Output Amplifiers, AD8110 (G = +1), AD8111 (G = +2) Drives 150 V Loads Excellent Video Performance 60 MHz 0.1 dB Gain Flatness 0.02% Differential Gain Error (R L = 150 V)

0.028 Differential Phase Error (R L = 150 V)

260 MHz –3 dB Bandwidth

500 V/ms Slew Rate

Low All Hostile Crosstalk of –78 dB @ 5 MHz Output Disable Allows Direct Connection of Multiple Device Outputs Reset Pin Allows Disabling of All Outputs (Connected Through a Capacitor to Ground Provides “Power- On” Reset Capability) Excellent ESD Rating: Exceeds 4000 V Human Body Model 80-Lead LQFP Package (12 mm /H11547 12 mm)

APPLICATIONS

Routing of High-Speed Signals Including: Composite Video (NTSC, PAL, S, SECAM) Component Video (YUV, RGB) Compressed Video (MPEG, Wavelet) 3-Level Digital Video (HDB3) FUNCTIONAL BLOCK DIAGRAM AD8110/AD8111 SWITCH MATRIX OUTPUT BUFFER G = +1, G = +2 128 40-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING PARALLEL LATCH DECODE 8 /H11547 5:16 DECODERS CLK DATA IN UPDATE CE RESET

16 INPUTS

8 OUTPUTS

TO "OFF" SER/PAR D0 D1 D2 D3 ENABLE/DISABLE PRODUCT DESCRIPTION The AD8110 and AD8111 are high-speed 16 × 8 video cross- point switch matrices. They offer a –3 dB signal band width greater than 260 MHz, and channel switch times of less than 25 ns with 1% settling. With –78 dB of crosstalk and –97 dB isolation (@ 5 MHz), the AD8110/AD8111 are useful in many high-speed applications. The differential gain and differential phase of better than 0.02% and 0.02 ° respectively, along with 0.1 dB flatness out to 60 MHz, make the AD8110/AD8111 ideal for video signal switching. The AD8110 and AD8111 include eight independent output buffers that can be placed into a high impedance state for paral- leling crosspoint outputs so that off channels do not load the output bus. The AD8110 has a gain of +1, while the AD 8111 offers a gain of +2. They operate on voltage supplies of ± 5 V while consuming only 50 mA of idle current. The channel switching is performed via a serial digital control (which can accommodate “daisy chaining” of several devices) or via a parallel control, allowing updating of an individual output without repro- gramming the entire array. The AD8110/AD8111 is packaged in an 80-lead LQFP package and is available over the extended industrial temperature range of –40°C to +85°C.

IMPORTANT LINKS for the AD8110_8111* Last content update 08/23/2013 03:27 pm PARAMETRIC SELECTION TABLES Find Similar Products By Operating Parameters DOCUMENTATION AN-282: Fundamentals of Sampled Data Systems Data-acquisition system uses fault protection CMOS Switches Offer High Performance in Low Power, Wideband Enhanced Multiplexing for MEMS Optical Cross Connects Video Amplifier Products FOR THE AD8110 AN-214: Ground Rules for High Speed Circuits EVALUATION KITS & SYMBOLS & FOOTPRINTS View the Evaluation Boards and Kits page for the AD8110 View the Evaluation Boards and Kits page for the AD8111 DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc DESIGN SUPPORT Submit your support request here: Linear and Data Converters Embedded Processing and DSP Telephone our Customer Interaction Centers toll free: Americas: 1-800-262-5643 Europe: 00800-266-822-82 China: 4006-100-006 India: 1800-419-0108 Russia: 8-800-555-45-90 Quality and Reliability Lead(Pb)-Free Data SAMPLE & BUY AD8110 AD8111 View Price & Packaging Request Evaluation Board Request Samples Check Inventory & Purchase Find Local Distributors * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page (labeled 'Important Links') does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. Powered by TCPDF (www.tcpdf.org)

REV. A–2– AD8110/AD8111–SPECIFICATIONS(VS = /H115505 V, TA = +25/H11543C, RL = 1 k/H9024 unless otherwise noted.) AD8110/AD8111 Parameter Conditions Min Typ Max Unit Reference DYNAMIC PERFORMANCE –3 dB Bandwidth 200 mV p-p, R L = 150 Ω 300/190 390/260 MHz TPC 1, 7

2 V p-p, RL = 150 Ω 150 MHz TPC 1, 7

Propagation Delay 2 V p-p, R L = 150 Ω 5n s Slew Rate 2 V Step, R L = 150 Ω 500 V/ µs Settling Time 0.1%, 2 V Step, R L = 150 Ω 40 ns TPC 6, 12 Gain Flatness 0.05 dB, 200 mV p-p, R L = 150 Ω 60/40 MHz TPC 1, 7 0.05 dB, 2 V p-p, R L = 150 Ω 65/40 MHz TPC 1, 7 0.1 dB, 200 mV p-p, R L = 150 Ω 80/57 MHz TPC 1, 7 0.1 dB, 2 V p-p, R L = 150 Ω 70/57 MHz TPC 1, 7 NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL, R L = 1 kΩ 0.01 % NTSC or PAL, R L =150 Ω 0.02 % Differential Phase Error NTSC or PAL, R L = 1 kΩ 0.01 Degrees NTSC or PAL, R L = 150 Ω 0.02 Degrees Crosstalk, All Hostile f = 5 MHz 78/85 dB TPC 2, 8 f = 10 MHz 70/80 dB TPC 2, 8 Off Isolation, Input-Output f = 10 MHz, RL =150 Ω, One Channel 93/99 dB TPC 17, 23 Input Voltage Noise 0.01 MHz to 50 MHz 15 nV/ √Hz TPC 14, 20 DC PERFORMANCE Gain Error R L = 1 kΩ 0.04/0.1 0.07/0.5 % RL = 150 Ω 0.15/0.25 % Gain Matching No Load, Channel-Channel 0.02/1.0 % RL = 1 kΩ, Channel-Channel 0.09/1.0 % Gain Temperature Coefficient 0.5/8 ppm/ °C OUTPUT CHARACTERISTICS Output Impedance DC, Enabled 0.2 Ω 18, 24 Disabled 10/0.001 M Ω 15, 21 Output Disable Capacitance Disabled 2 pF Output Leakage Current Disabled, AD8110 Only 1/NA µA Output Voltage Range No Load ±2.5 ±3V Output Current 20 40 mA Short Circuit Current 65 mA INPUT CHARACTERISTICS Input Offset Voltage Worst Case (All Configurations) 5 20 mV 29, 35 Temperature Coefficient 12 µV/°C 30, 36 Input Voltage Range ±2.5/±1.25 ±3/±1.5 V Input Capacitance Any Switch Configuration 2.5 pF Input Resistance 1 10 M Ω Input Bias Current Per Output Selected 2 5 µA SWITCHING CHARACTERISTICS Enable On Time 60 ns Switching Time, 2 V Step 50% UPDATE to 1% Settling 25 ns Switching Transient (Glitch) Measured at Output 20/30 mV p-p 16, 22 POWER SUPPLIES Supply Current AVCC, Outputs Enabled, No Load 38 mA AVCC, Outputs Disabled 15 mA AVEE, Outputs Enabled, No Load 38 mA AVEE, Outputs Disabled 15 mA DVCC 11 mA Supply Voltage Range ±4.5 to ±5.5 V PSRR f = 100 kHz 75/78 dB 13, 19 f = 1 MHz –55/–58 dB OPERATING TEMPERATURE RANGE Temperature Range Operating (Still Air) –40 to +85 °C θJA Operating (Still Air) 48 °C/W Specifications subject to change without notice.

Figure 1. Timing Diagram, Serial Mode

Figure 2. Timing Diagram, Parallel Mode

are recommended to avoid performance degradation or loss of functionality. conditions for extended periods may affect device reliability. 80-lead plastic LQFP (ST): θJA = 48 °C/W. due to a change in the stresses exerted on the die by the package. period can result in device failure. Figure 3. Maximum Power Dissipation vs. Temperature

1 X X X X X X No change in logic. parallel latches that control the switch array. X X X X X 0 X Asynchronous operation. All outputs are di sabled. Remainder of logic is unchanged.

3 TO 8 DECODER

Figure 4. Logic Diagram

INxx 66, 68, 70, 72, 74, 76, 78, Analog Inputs; xx = Channel Numbers 00 Through 15. DATA IN 57 Serial Data Input, TTL Compatible. CLK 58 Clock, TTL Compatible. Falling Edge Triggered. DATA OUT 59 Serial Data Out, TTL Compatible. CE 60 Chip Enable, Enable “Low.” Must be “low” to clock in and latch data. SER/PAR 55 Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected. OUTyy 41, 38, 35, 32, 29, 26, 23, 20 Analog Outputs yy = Channel Numbers 00 Through 07. AGND 2, 4, 6, 8, 10, 12, 14, 16, 46 Analog Ground for Inputs and Switch Matrix. DVCC 63, 79 5 V for Digital Circuitry. DGND 62, 80 Ground for Digital Circuitry. AVEE 17, 45 –5 V for Inputs and Switch Matrix. AVCC 18, 44 +5 V for Inputs and Switch Matrix. AGNDxx 42, 39, 36, 33, 30, 27, 24, 21 Gr ound for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected. AVCCxx/yy 43, 37, 31, 25, 22, 19 +5 V for Out put Amplifier that is shared by Channel Numbers xx and yy. Must be connected. AVEExx/yy 40, 34, 28, 22 –5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. A0 54 Parallel Data Input, TTL Compatible (Output Select LSB). A1 53 Parallel Data Input, TTL Compatible (Output Select). A2 52 Parallel Data Input, TTL Compatible (Output Select MSB). D0 51 Parallel Data Input, TTL Compatible (Input Select LSB). D1 50 Parallel Data Input, TTL Compatible (Input Select). D2 49 Parallel Data Input, TTL Compatible (Input Select). D3 48 Parallel Data Input, TTL Compatible (Input Select MSB). D4 47 Parallel Data Input, TTL Compatible (Output Enable). Figure 5. I/O Schematics

REV. A AD8110/AD8111 –8– PIN CONFIGURATION PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) 0.5mm LEAD PITCH AD8110/AD8111 16 /H11547 8 80L LQFP (12mm /H11547 12mm) DGND DVCC IN07 AGND IN06 AGND IN05 AGND IN04 AGND IN03 AGND IN02 AGND IN01 AGND IN00 DVCC DGND RESET AGND07 AVEE06/07 OUT06 AGND06 AVCC05/06 OUT05 AGND05 AVEE04/05 OUT04 AGND04 AVCC03/04 OUT03 AGND03 AVEE02/03 OUT02 AGND02 AVCC01/02 OUT01 AGND01 CE DATA OUT CLK DATA IN UPDATE SER/PAR AGND AVEE AVCC AVCC00 AGND00 OUT00 IN08 AGND IN09 AGND IN10 AGND IN11 AGND IN12 AGND IN13 AGND IN14 AGND IN15 AGND AVEE AVCC AVCC07 OUT07 AVEE00/01

REV. A –9– Typical Performance Characteristics– AD8110/AD8111 FREQUENCY – Hz GAIN – dB 100k 1M 1G 10M 100M FLATNESS – dB 0.2 0.1 –0.1 –0.2 –0.3 GAIN FLATNESS 0.34 200mV p-p 2V p-p RL = 150/H9024 TPC 1. AD8110 Frequency Response FREQUENCY – MHz CROSSTALK – dB –30 –40 –100 0.3 1 200 10 100 –50 –60 –70 –80 –90 ADJACENT ALL HOSTILE RL = 1k/H9024 TPC 2. AD8110 Crosstalk vs. Frequency FREQUENCY – Hz DISTORTION – dB 100k 1M 100M 10M –100 –40 –50 –60 –70 –80 –90 2ND HARMONIC 3RD HARMONIC RL = 150/H9024 VOUT = 2V p-p TPC 3. AD8110 Distortion vs. Frequency /H1154625 /H1154650 25ns/DIV 25mV/DIV RL = 150/H9024 TPC 4. AD8110 Step Response, 100 mV Step 0.5 /H115460.5 /H115461 25ns/DIV 0.5V/DIV RL = 150/H9024 TPC 5. AD8110 Step Response, 2 V Step 2V STEP RL = 150/H9024 0 1 02 03 04 05 06 07 08 0 10ns/DIV 0.1%/DIV TPC 6. AD8110 Settling Time

REV. A AD8110/AD8111 –10– FREQUENCY – Hz GAIN – dB 100k 1M 1G 10M 100M FLATNESS – dB 0.4 0.2 –0.2 –0.4 0.6 GAIN FLATNESS –0.6 0.8 200mV p-p 2V p-p –0.8 TPC 7. AD8111 Frequency Response FREQUENCY – MHz CROSSTALK – dB –20 –30 –90 0.3 1 200 10 100 –40 –50 –60 –70 –80 –100 –110 RL = 1k/H9024 ADJACENT ALL HOSTILE TPC 8. AD8111 Crosstalk vs. Frequency FREQUENCY /H11546 Hz DISTORTION /H11546 dB /H1154630 /H1154640 /H11546100 100k 1M 100M 10M /H1154650 /H1154660 /H1154670 /H1154680 /H1154690 2ND HARMONIC 3RD HARMONIC RL = 150/H9024 VOUT = 2V p-p TPC 9. AD8111 Distortion vs. Frequency /H1154625 /H1154650 25ns/DIV 25mV/DIV TPC 10. AD8111 Step Response, 100 mV Step 0.5 /H115460.5 /H115461 25ns/DIV 500mV/DIV TPC 11. AD8111 Step Response, 2 V Step 2V STEP RTO RL = 150/H9024 0 1 02 03 04 05 06 07 08 0 10ns/DIV 0.1%/DIV TPC 12. AD8111 Settling Time

REV. A AD8110/AD8111 –11– FREQUENCY /H11546 Hz POWER SUPPLY REJECTION /H11546 dB /H1154630 /H1154640 10k 100k 10M 1M /H1154650 /H1154660 /H1154670 /H1154680 /H1154690 RL = 150/H9024 TPC 13. AD8110 PSRR vs. Frequency FREQUENCY /H11546 Hz 100 56.3 10 1k 10M 100k 31.6 17. 5.63 3.16 100 10k 1M nV/ Hz TPC 14. AD8110 Voltage Noise vs. Frequency FREQUENCY /H11546 MHz OUTPUT IMPEDANCE /H11546 /H9024 0.1 1 500 10 100k 10k 100 100 TPC 15. AD8110 Output Impedance, Disabled UPDATE INPUT TYPICAL VIDEO OUT (RTO) –10 50ns/DIV 10mV/DIV 1V/DIV SWITCHING BETWEEN TWO INPUTS TPC 16. AD8110 Switching Transient (Glitch) FREQUENCY – Hz OFF ISOLATION – dB 100k 1M 500M 10M 100M VIN = 2V p-p RL = 150/H9024 –50 –60 –70 –80 –90 –100 –110 –120 –130 TPC 17. AD8110 Off Isolation, Input-Output 10,000 1000 100 0.1 FREQUENCY – Hz OUTPUT IMPEDANCE – /H9024 100k 1M 500M 10M 100M TPC 18. AD8110 Output Impedance, Enabled

REV. A AD8110/AD8111 –12– FREQUENCY – Hz POWER SUPPLY REJECTION – dB RTI 10k 100k 1M 10M –30 –40 –50 –60 –70 –80 RL = 150/H9024 TPC 19. AD8111 PSRR vs. Frequency FREQUENCY /H11546 Hz 100 56.3 10 1k 10M 100k 31.6 17.8 5.63 3.16 100 10k 1M nV/ Hz TPC 20. AD8111 Voltage Noise vs. Frequency FREQUENCY /H11546 MHz OUTPUT IMPEDANCE /H11546 /H9024 100k 0.1 1 500 10 10k 100 100 TPC 21. AD8111 Output Impedance, Disabled 1V/DIV UPDATE INPUT TYPICAL VIDEO OUT (RTO) 10mV/DIV –10 50ns/DIV SWITCHING BETWEEN TWO INPUTS TPC 22. AD8111 Switching Transient (Glitch) FREQUENCY – Hz OFF ISOLATION – dB 100k 1M 500M 10M 100M –60 –80 –100 –120 –130 –110 –90 –70 –50 VOUT = 2V p-p RL = 150/H9024 –40 TPC 23. AD8111 Off Isolation, Input-Output FREQUENCY /H11546 Hz OUTPUT IMPEDANCE /H11546 /H9024 100k 1M 500M 10M 100 0.1 100M TPC 24. AD8111 Output Impedance, Enabled

REV. A AD8110/AD8111 –13– INPUT IMPEDANCE – /H9024 100k 10k 100 10M 30k 100k 1M 10M 100M 500M FREQUENCY – Hz TPC 25. AD8110 Input Impedance vs. Frequency FREQUENCY – Hz GAIN – dB 0.1M 1M 10M 100M 1G 18pF = 7.7dB 12pF = 4.5dB VIN = 200mV p-p RL = 150/H9024 TPC 26. AD8110 Frequency Response vs. Capacitive Load FREQUENCY – Hz FLATNESS – dB 0.7 0.6 –0.2 0.1M 1M 10M 100M 1G 0.5 0.4 0.3 0.2 0.1 –0.1 VIN = 200mV p-p RL = 150/H9024 CL = 18pF CL = 12pF TPC 27. AD8110 Flatness vs. Capacitive Load VOUT UPDATE INPUT 1 AT +1V INPUT 0 AT –1V 50ns/DIV 2V/DIV 1V/DIV TPC 28. AD8110 Switching Time OFFSET VOLTAGE – Volts FREQUENCY 260 –0.020 –0.010 0.000 0.010 240 180 160 120 220 200 140 100 0.020 TPC 29. AD8110 Offset Voltage Distribution TEMPERATURE – /H11543C VOS – mV 2.0 –2.0 –60 –40 100–20 0 20 40 60 80 1.5 –0.5 –1.0 –1.5 1.0 0.5 TPC 30. AD8110 Offset Voltage vs. Temperature (Normalized at 25°C)

REV. A AD8110/AD8111 –14– FREQUENCY – Hz INPUT IMPEDANCE – /H9024 30k 1M 500M 10M 100M 100k 10k 100 100k 10M TPC 31. AD8111 Input Impedance vs. Frequency GAIN – dB FREQUENCY – Hz 0.1M 1M 10M 100M 1G 3G 18pF 12pF TPC 32. AD8111 Frequency Response vs. Capacitive Load GAIN – dB 0.7 0.6 –0.1 0.5 0.4 0.3 0.2 0.1 –0.2 –0.3 FREQUENCY – Hz 0.1M 1M 10M 100M 1G 3G 12pF 18pF VIN = 100mV RL = 150/H9024 TPC 33. AD8111 Flatness vs. Capacitive Load VOUT UPDATE INPUT 1 AT +1V INPUT 0 AT –1V 50ns/DIV 2V/DIV 1V/DIV TPC 34. AD8111 Switching Time OFFSET VOLTAGE – Volts FREQUENCY 120 480 360 320 240 160 440 400 280 200 TPC 35. AD8111 Offset Voltage Distribution (RTI) TEMPERATURE – /H11543C VOS – mV 2.0 –2.0 –60 –40 100–20 0 20 40 60 80 1.5 –0.5 –1.0 –1.5 1.0 0.5 TPC 36. AD8111 Offset Voltage Drift vs. Temperature (Normalized at 25°C)

REV. A AD8110/AD8111 –15– THEORY OF OPERATION The AD8110 (G = +1) and AD8111 (G = +2) share a common core architecture consisting of an array of 128 transconductance (gm) input stages organized as eight 16:1 multiplexers with a common, 16-line analog input bus. Each multiplexer is basically a folded-cascode high-speed voltage feedback amplifier with 16 input stages. The input stages are NPN differential pairs whose differential current outputs are combined at the output stage, which contains the high impedance node, compensation and a complementary emitter follower output buffer. In the AD8110, the output of each multiplexer is fed directly back to the inverting inputs of its 16 gm stages. In the AD8111, the feedback network is a voltage divider consisting of two equal resistors. This switched-gm architecture results in a low power crosspoint switch that is able to directly drive a back terminated video load (150 Ω) with low distortion (differential gain and differential phase errors are better than 0.02% and 0.02°, respectively). This design also achieves high input resistance and low input ca paci- tance without the signal degradation and power dissipation of additional input buffers. However, the small input bias current at any input will increase almost linearly with the number of out- puts programmed to that input. The output disable feature of these crosspoints allows larger switch matrices to be built simply by busing together the outputs of multiple 16 × 8 ICs. However, while the disabled output imped- ance of the AD8110 is very high (10 M Ω), that of the AD8111 is limited by the resistive feedback network (which has a nominal total resistance of 1 kΩ) that appears in parallel with the disabled output. If the outputs of multiple AD8111s are connected through separate back termination resistors, the loading due to these finite output impedances will lower the effective back termination impedance of the overall matrix. This problem is eliminated if the outputs of multiple AD8111s are connected directly and share a single back termination resistor for each output of the overall matrix. This configuration increases the capacitive loading of the disabled AD8111 on the output of the enabled AD8111. The AD8110/AD8111 have two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 40 bits can be provided that will update the entire matrix each time. The second option allows for changing a single output’s programming via a parallel interface. The serial option requires fewer signals, but requires more time (clock cycles) for changing the programming, while the parallel programming tech- nique requires m ore signals, but can change a single output at a time and requires fewer clock cycles to complete programming. Serial Programming The serial programming mode uses the device pins CE, CLK, DATA IN, UPDATE, and SER/PAR. The first step is to assert a LOW on SER/PAR in order to enable the serial programming mode. CE for the chip must be LOW to allow data to be clocked into the device. The CE signal can be used to address an indi- vidual device when devices are connected in parallel. The UPDATE signal should be HIGH during the time that data is shifted into the device’s serial port. Although the data will still shift in when UPDATE is LOW, the transparent, asynchronous latches will allow the shifting data to reach the matrix. This will cause the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in at every down edge of CLK. A total of 40 data bits must be shifted in to complete the program- ming. For each of the eight outputs, there are four bits (D0–D3) that determine the source of its input followed, by one bit (D4) that determines the enabled state of the output. If D4 is LOW (output disabled) the four associated bits (D0–D3) do not matter, because no input will be switched to that output. The most significant output address data is shifted in first, then following in sequence until the least significant output address data is shifted in. At this point UPDATE can be taken LOW, which will cause the programming of the device according to the data that was just shifted in. The UPDATE registers are asyn- chronous and when UPDATE is LOW (and CE is LOW), they are transparent. If more than one AD8110/AD8111 device is to be serially pro- grammed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK, CE, UPDATE and SER/PAR pins should be connected in parallel and operated as described above. The serial data is input to the DATA IN pin of the first device of the chain, and it will ripple on through to the last. Therefore, the data for the last device in the chain should come at the begin- ning of the programming sequence. The length of the programming sequence will be 40 times the number of devices in the chain. Parallel Programming When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modification of a single output at a time. Since this takes only one CLK/ UPDATE cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RESET signal does not reset all registers in the AD8110/ AD8111. When taken low, the RESET signal will only set each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal registers in the device will generally have random data, even though the RESET signal was asserted. If parallel programming is used to program one output, that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up.

REV. A AD8110/AD8111 –16– This will ensure that the programming matrix is always in a known state. From then on, parallel programming can be used to modify a single output or more at a time. In a similar fashion, if both CE and UPDATE are taken LOW after initial power-up, the random power-up data in the shift register will be programmed into the matrix. Therefore, in order to prevent the crosspoint from being programmed into an unknown state do not apply low logic levels to both CE and UPDATE after power is initially applied. Programming the full shift register one time to a desired state by either serial or parallel programming after initial power-up will eliminate the possibility of program- ming the matrix to an unknown state. To change an output’s programming via parallel programming, SER/PAR and UPDATE should be taken HIGH and CE should be taken LOW. The CLK signal should be in the HIGH state. The address of the output that is to be programmed should be put on A0–A2. The first four data bits (D0–D3) should contain the information that identifies the input that is programmed to the output that is addressed. The fourth data bit (D4) will determine the enabled state of the output. If D4 is LOW (output disabled), the data on D0–D3 does not matter. After the desired address and data signals have been established, they can be latched into the shift register by a HIGH-to-LOW transition of the CLK signal. The matrix will not be programmed, however, until the UPDATE signal is taken low. Thus, it is possible to latch in new data for several or all of the outputs first via successive negative transitions of CLK while UPDATE is held high, and then have all the new data take effect when UPDATE goes LOW. This technique should be used when programming the device for the first time after power-up when using parallel programming. POWER-ON RESET When powering up the AD8110/AD8111 it is usually desirable to have the outputs come up in the disabled state. The RESET pin, when taken LOW will cause all outputs to be in the dis- abled state. However, the RESET signal does not reset all registers in the AD8110/AD8111. This is important when operating in the parallel programming mode. Please refer to that section for information about programming internal registers after power- up. Serial programming will program the entire matrix each time, so no special considerations apply. Since the data in the shift register is random after power-up, it should not be used to program the matrix or else the matrix can enter unknown states. To prevent this, do not apply logic low signals to both CE and UPDATE initially after power-up. The shift register should first be loaded with the desired data, and then UPDATE can be taken LOW to program the device. The RESET pin has a 20 kΩ pull-up resistor to DVDD that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground will hold RESET LOW for some time while the rest of the device stabilizes. The LOW condition will cause all the outputs to be disabled. The capacitor will then charge through the pull-up resistor to the HIGH state; thus allowing full programming capability of the device. GAIN SELECTION The 16 × 8 crosspoints come in two versions depending on the desired gain of the analog circuit paths. The AD8110 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. The AD8110 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used. The AD8110 outputs have a very high impedance when their outputs are disabled. For devices that will be used to drive a terminated cable with its outputs, the AD8111 can be used. This device has a built-in gain of two that eliminates the need for a gain-of-two buffer to drive a video line. Because of the presence of the feedback network in these devices, the disabled output impedance is about 1 k Ω. If external amplifiers are used to provide a gain = +2, Analog Devices’ AD8079 provides a fixed G = +2 function. CREATING LARGER CROSSPOINT ARRAYS The AD8110/AD8111 are high-density building blocks for creating crosspoint arrays of dimensions larger than 16 × 8. Various features such as output disable, chip enable, and gain- of-one- and-two options are useful for creating larger arrays. For very large arrays, they can be used along with the AD8116, a 16 × 16 video crosspoint device. In addition, when required for customizing a crosspoint array size, they can be used with the AD8108 and AD8109, a pair (unity gain and gain-of-two) of 8 × 8 video crosspoint switches. The first consideration in constructing a larger crosspoint is to determine the minimum number of devices that are required. The 16 × 8 architecture of the AD8110/AD8111 contains 128 “points,” which is a factor of 32 greater than a 4 × 1 crosspoint. The PC board area and power consumption savings are readily apparent when compared to using these smaller devices. For a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. Nonblocking requires that the programming of a given input to one or more outputs does not restrict the avail- ability of that input to be a source for any other outputs. Some nonblocking crosspoint architectures will require more than this minimum as calculated above. Also, there are blocking architectures that can be constructed with fewer devices than this minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system.

Figure 6. A 32 × 8 Crosspoint Array Using Two AD8110s outputs of each device wire-ORed together in groups of eight. disabled output impedance than the AD8111. Figure 7. A Gain-of-Two 128 × 8 Nonblocking Crosspoint Array (128 × 16 Blocking)

REV. A AD8110/AD8111 –18– Multichannel Video The excellent video specifications of the AD8110/AD8111 make them ideal candidates for creating composite video cross point switches. These can be made quite dense by taking advantage of the AD8110/AD8111’s high level of integration and the fact that composite video requires only one crosspoint channel per system video channel. There are, however, other video formats that can be routed with the AD8110/AD8111 requiring more than one crosspoint channel per video channel. Some systems use twisted-pair wiring to carry video signals. These systems utilize differential signals and can lower costs because they use lower cost cables, connectors and termination methods. They also have the ability to lower crosstalk and reject common-mode signals, which can be important for equip ment that operates in noisy environments or where common-mode volt- ages are present between transmitting and receiving equipment. In such systems, the video signals are differential; there is a positive and negative (or inverted) version of the signals. These complementary signals are transmitted onto each of the two wires of the twisted pair, yielding a first order zero common- mode signal. At the receive end, the signals are differentially received and converted back into a single-ended signal. When switching these differential signals, two channels are required in the switching element to handle the two differential signals that make up the video channel. Thus, one differential video channel is assigned to a pair of crosspoint channels, both input and output. For a single AD8110/AD8111, eight differen- tial video channels can be assigned to the 16 inputs and four to the outputs. This will effectively form an 8 × 4 differential cross- point switch. Programming such a device will require that inputs and outputs be programmed in pairs. This information can be deduced by inspection of the programming format of the AD8110/AD8111 and the requirements of the system. There are other analog video formats requiring more than one analog circuit per video channel. One two-circuit format that is commonly being used in systems such as satellite TV, digital cable boxes and higher quality VCRs, is called S-video or Y/C video. This format carries the brightness (luminance or Y) portion of the video signal on one channel and the color (chromi- nance, chroma or C) on a second channel. Since S-video also uses two separate circuits for one video chan- nel, creating a crosspoint system requires assigning one video channel to two crosspoint channels as in the case of a differential video system. Aside from the nature of the video format, other aspects of these two systems will be the same. There are yet other video formats using three channels to carry the video information. Video cameras produce RGB (red, green, blue) directly from the image sensors. RGB is also the usual format used by computers internally for graphics. RGB can also be converted to Y, R-Y, B-Y format, sometimes called YUV format. These three-circuit, video standards are referred to as component analog video. The component video standards require three crosspoint chan- nels per video channel to handle the switching function. In a fashion similar to the two-circuit video formats, the inputs and outputs are assigned in groups of three and the appropriate logic programming is performed to route the video signals. CROSSTALK Many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in proximity in a system, as will undoubtedly be the case in a system that uses the AD8110/ AD8111, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more AD8110/AD8111s. Types of Crosstalk Crosstalk can be propagated by means of any of three meth- ods. These fall into the categories of electric field, magnetic field and sharing of common impedances. This section will explain these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propa- gates across a stray capacitance (e.g., free space) and couples with the receiver and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields will then generate voltages in any other conductors whose paths they link. The undes- ired induced voltages in these other channels are crosstalk signals. The channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. The power supplies, grounds and other signal return paths of a multichannel system are generally shared by the various chan- nels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the com- mon impedance. All these sources of crosstalk are vector quantities, so the magnitudes cannot be simply added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in paral- lel in a given configuration can actually reduce the crosstalk. Areas of Crosstalk For a practical AD8110/AD8111 circuit, it is required that it be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evalu- ation board) that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that a system’s crosstalk is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. It is important to try to separate these two areas of crosstalk when attempting to minimize its effect. In addition, crosstalk can occur among the inputs to a cross- point and among the outputs. It can also occur from input to output. Techniques will be discussed for diagnosing which part of a system is contributing to crosstalk.

REV. A AD8110/AD8111 –19– Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by: XT Asel s Atest s= () ()()20 10log / where s = jw is the Laplace transform variable, Asel(s) is the amplitude of the crosstalk-induced signal in the selected channel and Atest(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal will have a phase relative to the test signal asso- ciated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magni- tude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 16 /H11003 8 matrix of the AD8110/AD8111, we can examine the number of crosstalk terms that can be considered for a single channel, say IN00 input. IN00 is programmed to connect to one of the AD8110/AD8111 outputs where the measurement can be made. We can first measure the crosstalk terms associated with driving a test signal into each of the other 15 inputs one at a time. We can then measure the crosstalk terms associated with driving a parallel test signal into all 15 other inputs taken two at a time in all possible combinations; and then three at a time, etc., until, finally, there is only one way to drive a test signal into all 15 other inputs. Each of these cases is legitimately different from the others and might yield a unique value depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then to specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other (not used for measurement) outputs are taken into consideration, the numbers rather quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8110/AD8111s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure “all hostile” crosstalk. Su˘s term means that the crosstalk to the selected channel is measured, while all other system channels are driven in parallel. In general, this will yield the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worst-case measure for any other one-channel or two-channel crosstalk measurements. Input and Output Crosstalk The flexible programming capability of the AD8110/AD8111 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input channel (IN07 in the middle for this example) can be programmed to drive OUT03. The input to IN07 is just terminated to ground (via 50 or 75 Ω) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT03 disabled. Since grounded IN07 is programmed to drive OUT03, there should be no signal present. Any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven. (They are all disabled.) Thus, this method measures the all-hostile input contribution to crosstalk into IN07. Of course, the method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel (IN00 for example) is driven and all outputs other than a given output (IN03 in the middle) are programmed to connect to IN00. OUT03 is programmed to connect to IN15 (far away from IN00), which is terminated to ground. Thus OUT03 should not have a signal present since it is listening to a quiet input. Any signal measured at the OUT03 can be attributed to the output crosstalk of the other seven hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termi- nation resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies the magnitude of the crosstalk will be given by: XT R C s SM= () ×[]20 10log where RS is the source resistance, CM is the mutual capacitance between the test signal circuit and the selected circuit, and s is the Laplace transform variable. From the equation it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8110/AD8111 is specified with excellent differential gain and phase when driving a standard 150 Ω video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. These currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8110/AD8111.

59 DATA OUT

59 DATA IN

80 DGNDP2-5

Figure 9. Evaluation Board Schematic

REV. A AD8110/AD8111 –26– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead Plastic LQFP (ST-80A) SEATING PLANE 0.063 (1.60) MAX 0.030 (0.75) 0.020 (0.50) 0.003 (0.08) MAX 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) 0.011 (0.27) 0.007 (0.17) 0.559 (14.20) 0.543 (13.80) 0.476 (12.10) 0.469 (11.90) 0.476 (12.10) 0.469 (11.90) 0.559 (14.20) 0.543 (13.80) TOP VIEW (PINS DOWN) 6180 0.020 (0.50) BSC CONTROLLING DIMENSIONS ARE IN MILLIMETERS

REV. A AD8110/AD8111 –27–

Revision History

Data Sheet changed from REV. 0 to REV. A. Universal change in nomenclature from MQFP to LQFP

REV. A–28– C01069–0–2/02(A) PRINTED IN U.S.A.

Summary

260 MHz, 16 8 Buffered Video Crosspoint Switches REV. A

Description