AD8109AST

AD8108 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD8108/AD8109* Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1997

325 MHz, 8 3 8 Buffered Video

G = +1, G = +2 32-BIT SHIFT REGISTER WITH 4-BIT PARALLEL LOADING PARALLEL LATCH DECODE 8 3 4:8 DECODERS CLK DATA IN UPDATE CE RESET

8 INPUTS

8 OUTPUTS

TO "OFF" SER/PAR D0 D1 D2 D3 ENABLE/DISABLE

FEATURES

8 3 8 High Speed Nonblocking Switch Arrays AD8108: G = +1 AD8109: G = +2 Serial or Parallel Programming of Switch Array Serial Data Out Allows “Daisy Chaining” of Multiple 8 3 8s to Create Larger Switch Arrays Output Disable Allows Connection of Multiple Devices Pin Compatible with AD8110/AD8111 16 3 8 Switch Arrays For 16 3 16 Arrays See AD8116 Complete Solution Buffered Inputs Eight Output Amplifiers, AD8108 (G = +1), AD8109 (G = +2) Drives 150 V Loads Excellent Video Performance 60 MHz 0.1 dB Gain Flatness 0.02%/0.02 8 Differential Gain/Differential Phase Error L = 150 V) Excellent AC Performance AD8108 AD8109 –3 dB Bandwidth 325 MHz 250 MHz Slew Rate 400 V/ ms 480 V/ ms Low Power of 45 mA Low All Hostile Crosstalk of –83 dB @ 5 MHz Reset Pin Allows Disabling of All Outputs (Connected Through a Capacitor to Ground Provides “Power- On” Reset Capability) Excellent ESD Rating: Exceeds 4000 V Human Body Model 80-Lead TQFP Package (12 mm 3 12 mm)

APPLICATIONS

Routing of High Speed Signals Including: Composite Video (NTSC, PAL, S, SECAM.) Component Video (YUV, RGB) Compressed Video (MPEG, Wavelet) 3-Level Digital Video (HDB3) PRODUCT DESCRIPTION The AD8108 and AD8109 are high speed 8 × 8 video cross- point switch matrices. They offer a –3 dB signal bandwidth greater than 250 MHz and channel switch times of less than 25 ns with 1% settling. With –83 dB of crosstalk and –98 dB isolation (@ 5 MHz), the AD8108/AD8109 are useful in many high speed applications. The differential gain and differential phase of better than 0.02% and 0.02 ° respectively along with 0.1 dB flatness out to 60 MHz make the AD8108/AD8109 ideal for video signal switching. The AD8108 and AD8109 include eight independent output buffers that can be placed into a high impedance state for paral- leling crosspoint outputs so that off channels do not load the output bus. The AD8108 has a gain of +1, while the AD8109 offers a gain of +2. They operate on voltage supplies of ± 5 V while consuming only 45 mA of idle current. The channel switch- ing is performed via a serial digital control (which can accommo- date “daisy chaining” of several devices) or via a parallel control allowing updating of an individual output without re-programing the entire array. The AD8108/AD8109 is packaged in an 80-lead TQFP package and is available over the extended industrial temperature range of –40°C to +85°C. *Patent Pending.

–2– REV. 0 AD8108/AD8109–SPECIFICATIONS AD8108/AD8109 Reference Parameter Conditions Min Typ Max Units Figure No. DYNAMIC PERFORMANCE –3 dB Bandwidth 200 mV p-p, R L = 150 Ω 240/150 325/250 MHz 6, 12

2 V p-p, RL = 150 Ω 140/160 MHz 6, 12

Propagation Delay 2 V p-p, R L = 150 Ω 5n s Slew Rate 2 V Step, R L = 150 Ω 400/480 V/ µs Settling Time 0.1%, 2 V Step, R L = 150 Ω 40 ns 11, 17 Gain Flatness 0.05 dB, 200 mV p-p, R L = 150 Ω 60/50 MHz 6, 12 0.05 dB, 2 V p-p, R L = 150 Ω 60/50 MHz 6, 12 0.1 dB, 200 mV p-p, R L = 150 Ω 70/65 MHz 6, 12 0.1 dB, 2 V p-p, R L = 150 Ω 80/50 MHz 6, 12 NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL, R L = 1 kΩ 0.01 % NTSC or PAL, R L = 150 Ω 0.02 % Differential Phase Error NTSC or PAL, R L = 1 kΩ 0.01 Degrees NTSC or PAL, R L = 150 Ω 0.02 Degrees Crosstalk, All Hostile f = 5 MHz 83/85 dB 7, 13 f = 10 MHz 76/83 dB 7, 13 Off Isolation, Input-Output f = 10 MHz, RL =150 Ω , One Channel 93/98 dB 22, 28 Input Voltage Noise 0.01 MHz to 50 MHz 15 nV/ √Hz 19, 25 DC PERFORMANCE Gain Error R L = 1 kΩ 0.04/0.1 0.07/0.5 % RL = 150 Ω 0.15/0.25 % Gain Matching No Load, Channel-Channel 0.02/1.0 % RL = 1 kΩ , Channel-Channel 0.09/1.0 % Gain Temperature Coefficient 0.5/8 ppm/ °C OUTPUT CHARACTERISTICS Output Impedance DC, Enabled 0.2 Ω 23, 29 Disabled 10/0.001 M Ω 20, 26 Output Disable Capacitance Disabled 2 pF Output Leakage Current Disabled, AD8108 Only 1/NA µA Output Voltage Range No Load ± 2.5 ± 3V Output Current 20 40 mA Short Circuit Current 65 mA INPUT CHARACTERISTICS Input Offset Voltage Worst Case (All Configurations) 5 20 mV 34, 40 Temperature Coefficient 12 µV/°C 35, 41 Input Voltage Range ± 2.5/± 1.25 ± 3/± 1.5 V Input Capacitance Any Switch Configuration 2.5 pF Input Resistance 1 10 M Ω Input Bias Current Per Output Selected 2 5 µA SWITCHING CHARACTERISTICS Enable On Time 60 ns Switching Time, 2 V Step 50% UPDATE to 1% Settling 25 ns Switching Transient (Glitch) Measured at Output 20/30 mV p-p 21, 27 POWER SUPPLIES Supply Current AVCC, Outputs Enabled, No Load 33 mA AVCC, Outputs Disabled 10 mA AVEE, Outputs Enabled, No Load 33 mA AVEE, Outputs Disabled 10 mA DVCC 10 mA Supply Voltage Range ± 4.5 to ± 5.5 V PSRR f = 100 kHz 73/78 dB 18, 24 f = 1 MHz 55/58 dB OPERATING TEMPERATURE RANGE Temperature Range Operating (Still Air) –40 to +85 °C θJA Operating (Still Air) 48 °C/W Specifications subject to change without notice. (VS = 65 V, TA = +258C, RL = 1 kV unless otherwise noted)

Figure 1. Timing Diagram, Serial Mode

Figure 2. Timing Diagram, Parallel Mode

accumulate on the human body and test equipment and can discharge without detection. ESD precautions are recommended to avoid performance degradation or loss of functionality. conditions for extended periods may affect device reliability. 80-lead plastic TQFP (ST): θJA = 48°C/W. tended period can result in device failure. tion temperature (+150 °C) is not exceeded under all conditions. mum power derating curves shown in Figure 3. Figure 3. Maximum Power Dissipation vs. Temperature

1 X X X X X X No change in logic. parallel latches that control the switch array. X X X X X 0 X Asynchronous operation. All outputs are di sabled. Remainder of logic is unchanged.

3 TO 8 DECODER

Figure 4. Logic Diagram

INxx 1, 3, 5, 7, 9, 11, 13, 15 Analog Inputs; xx = Channel Numbers 00 Through 07. DATA IN 57 Serial Data Input, TTL Compatible. CLK 58 Clock, TTL Compatible. Falling Edge Triggered. DATA OUT 59 Serial Data Out, TTL Compatible. CE 60 Chip Enable, Enable “Low.” Must be “low” to clock in and latch data. SER/PAR 55 Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected. OUTyy 41, 38, 35, 32, 29, 26, 23, 20 Analog Outputs yy = Channel Numbers 00 Through 07. AGND 2, 4, 6, 8, 10, 12, 14, 16, 46 Analog Ground for Inputs and Switch Matrix. DVCC 63, 79 +5 V for Digital Circuitry. DGND 62, 80 Ground for Digital Circuitry. AVEE 17, 45 –5 V for Inputs and Switch Matrix. AGNDxx 42, 39, 36, 33, 30, 27, 24, 21 Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected. AVCCxx/yy 43, 37, 31, 25, 22, 19 +5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. AVEExx/yy 40, 34, 28, 22 –5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected. A0 54 Parallel Data Input, TTL Compatible (Output Select LSB). A1 53 Parallel Data Input, TTL Compatible (Output Select). A2 52 Parallel Data Input, TTL Compatible (Output Select MSB). D0 51 Parallel Data Input, TTL Compatible (Input Select LSB). D1 50 Parallel Data Input, TTL Compatible (Input Select). D2 49 Parallel Data Input, TTL Compatible (Input Select MSB). D3 48 Parallel Data Input, TTL Compatible (Output Enable). Figure 5. I/O Schematics

–8– REV. 0 PIN CONFIGURATION PIN 1 IDENTIFIER TOP VIEW (Not to Scale) DGND DVCC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DVCC DGND RESET AGND07 AVEE06/07 OUT06 AGND06 AVCC05/06 OUT05 AGND05 AVEE04/05 OUT04 AGND04 AVCC03/04 OUT03 AGND03 AVEE02/03 OUT02 AGND02 AVCC01/02 OUT01 AGND01 AVEE00/01 CE DATA OUT CLK DATA IN UPDATE SER/PAR NC AGND AVEE AVCC AVCC00 AGND00 OUT00 AD8108/AD8109 NC = NO CONNECT IN00 IN01 AGND AGND IN03 IN04 AGND AGND IN06 IN07 AGND AVCC AVCC07 OUT07 AGND IN02 AGND IN05 AGND AVEE

Figure 30. AD8108 Input Impedance vs. Frequency

8 FREQUENCY – Hz

Figure 31. AD8108 Frequency Response vs. Capacitive Load Figure 32. AD8108 Flatness vs. Capacitive Load Figure 33. AD8108 Switching Time Figure 34. AD8108 Offset Voltage Distribution Figure 35. AD8108 Offset Voltage Drift vs. Temperature

Figure 36. AD8109 Input Impedance vs. Frequency Figure 37. AD8109 Frequency Response vs. Capacitive Load

0.4 FREQUENCY – Hz

Figure 38. AD8109 Flatness vs. Capacitive Load Figure 39. AD8109 Switching Time Figure 40. AD8109 Offset Voltage Distribution (RTI) Figure 41. AD8109 Offset Voltage Drift vs. Temperature

–15–REV. 0 THEORY OF OPERATION: The AD8108 (G = +1) and AD8109 (G = +2) share a common core architecture consisting of an array of 64 transconductance (gm) input stages organized as eight 8:1 multiplexers with a common, 8-line analog input bus. Each multiplexer is basically a folded-cascode high impedance voltage feedback amplifier with eight input stages. The input stages are NPN differential pairs whose differential current outputs are combined at the output stage, which contains the high impedance node, com- pensation and a complementary emitter follower output buffer. In the AD8108, the output of each multiplexer is fed back di- rectly to the inverting inputs of its eight gm stages. In the AD8109, the feedback network is a voltage divider consisting of a two equal resistors. This switched-gm architecture results in a low power crosspoint switch that is able to directly drive a back terminated video load (150 Ω ) with low distortion (differential gain and differential phase errors are better than 0.02% and 0.02 °, respectively). This design also achieves high input resistance and low input capacitance without the signal degradation and power dissipa- tion of additional input buffers. However, the small input bias current at any input will increase almost linearly with the num- ber of outputs programmed to that input. The output disable feature of these crosspoints allows larger switch matrices to be built by simply busing together the out- puts of multiple 8 × 8 ICs. However, while the disabled output impedance of the AD8108 is very high (10 M Ω ), that of the AD8109 is limited by the resistive feedback network (which has a nominal total resistance of 1 k Ω that appears in parallel with the disabled output. If the outputs of multiple AD8109s are connected through separate back termination resistors, the loading due to these finite output impedances will lower the effective back termination impedance of the overall matrix. This problem is eliminated if the outputs of multiple AD8109s are connected directly and share a single back termination resistor for each output of the overall matrix. This configuration in- creases the capacitive loading of the disabled AD8109s on the output of the enabled AD8109. The AD8108/AD8109 have two options for changing the pro- gramming of the crosspoint matrix. In the first, a serial word of 32 bits can be provided that will update the entire matrix each time. The second option allows for changing a single output’s programming via a parallel interface. The serial option requires fewer signals, but requires more time (clock cycles) for c hanging the programming, while the parallel programming technique re- quires more signals, but can change a single output at a time and requires fewer clock cycles to complete programming. Serial Programming The serial programming mode uses the device pins CE, CLK, DATA IN, UPDATE, and SER/PAR. The first step is to assert a LOW on SER/PAR in order to enable the serial program- ming mode. CE for the chip must be LOW to allow data to be clocked into the device. The CE signal can be used to address an individual device when devices are connected in parallel. The UPDATE signal should be HIGH during the time that data is shifted into the device’s serial port. Although the data will still shift in when UPDATE is LOW, the transparent, asynchronous latches will allow the shifting data to reach the matrix. This will cause the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in at every down edge of CLK. A total of 32 data bits must be shifted in to complete the pro- gramming. For each of the eight outputs, there are three bits (D0–D2) that determine the source of its input followed by one bit (D3) that determines the enabled state of the output. If D3 is LOW (output disabled), the three associated bits (D0–D2) do not matter because no input will be switched to that output. The most-significant-output-address data is shifted in first, then following in sequence until the least-significant-output-address data is shifted in. At this point UPDATE can be taken LOW, which will cause the programming of the device according to the data that was just shifted in. The UPDATE registers are asyn- chronous and when UPDATE is LOW, they are transparent. If more than one AD8108/AD8109 device is to be serially pro- grammed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK, CE, UPDATE and SER/PAR pins should be connected in parallel and operated as de- scribed above. The serial data is input to the DATA IN pin of the first device of the chain, and it will ripple on through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence will be 32 times the number of devices in the chain. PARALLEL PROGRAMMING When using the parallel programming mode, it is not neces- sary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modifica- tion of a single output at a time. Since this takes only one CLK/ UPDATE cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RESET signal DOES NOT RESET ALL REGISTERS in the AD8108/AD8109. When taken low, the RESET signal will only set each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs will not be active at the same time. After initial power-up, the internal registers in the device will generally have random data, even though the RESET signal was asserted. If parallel programming is used to program one out- put, that output will be properly programmed but the rest of the device will have a random program state depending on the inter- nal register content at power-up. Therefore, when using parallel programming, it is essential that ALL OUTPUTS BE PRO- GRAMMED TO A DESIRED STATE AFTER POWER-UP. This will ensure that the programming matrix is always in a known state. From then on, parallel programming can be used to modify a single, or more, output at a time.

–16– REV. 0 In a similar fashion, if both CE and UPDATE are taken LOW after initial power-up, the random power-up data in the shift register will be programmed into the matrix. Therefore, in order to prevent the crosspoint from being programmed into an un- known state DO NOT APPLY LOW LOGIC LEVELS TO BOTH CE AND UPDATE AFTER POWER IS INITIALLY APPLIED. Programming the full shift register one time to a desired state by either serial or parallel programming after initial power-up will eliminate the possibility of programming the matrix to an unknown state. To change an output’s programming via parallel programming, SER/PAR and UPDATE should be taken HIGH and CE should be taken LOW. The CLK signal should be in the HIGH state. The address of the output that is to be programmed should be put on A0–A2. The first three data bits (D0–D2) should contain the information that identifies the input that is programmed to the output that is addressed. The fourth data bit (D3) will de- termine the enabled state of the output. If D3 is LOW (output disabled) the data on D0–D2 does not matter. After the desired address and data signals have been established, they can be latched into the shift register by a HIGH to LOW transition of the CLK signal. The matrix will not be programmed, however, until the UPDATE signal is taken low. Thus, it is possible to latch in new data for several or all of the outputs first via successive negative transitions of CLK while UPDATE is held high, and then have all the new data take effect when UPDATE goes LOW. This is the technique that should be used when programming the device for the first time after power-up when using parallel programming. POWER-ON RESET When powering up the AD8108/AD8109 it is usually desirable to have the outputs come up in the disabled state. The RESET pin, when taken LOW will cause all outputs to be in the dis- abled state. However, the RESET signal DOES NOT RESET ALL REGISTERS in the AD8108/AD8109. This is important when operating in the parallel programming mode. Please refer to that section for information about programming internal registers after power-up. Serial programming will program the entire matrix each time, so no special considerations apply. Since the data in the shift register is random after power-up, they should not be used to program the matrix or else the matrix can enter unknown states. To prevent this, DO NOT APPLY LOGIC LOW SIGNALS TO BOTH CE AND UPDATE INITIALLY AFTER POWER-UP. The shift register should first be loaded with the desired data, and then UPDATE can be taken LOW to program the device. The RESET pin has a 20 kΩ pull-up resistor to DVDD that can be used to create a simple power-up reset circuit. A capacitor from RESET to ground will hold RESET LOW for some time while the rest of the device stabilizes. The LOW condition will cause all the outputs to be disabled. The capacitor will then charge through the pull-up resistor to the HIGH state, thus allowing full programming capability of the device. Gain Selection The 8 × 8 crosspoints come in two versions depending on the desired gain of the analog circuit paths. The AD8108 device is unity gain and can be used for analog logic switching and other applications where unity gain is desired. The AD8108 can also be used for the input and interior sections of larger crosspoint arrays where termination of output signals is not usually used. The AD8108 outputs have a very high impedance when their outputs are disabled. For devices that will be used to drive a terminated cable with its outputs, the AD8109 can be used. This device has a built-in gain of two that eliminates the need for a gain-of-two buffer to drive a video line. Because of the presence of the feedback net- work in these devices, the disabled output impedance is about 1 kΩ . If external amplifiers will be used to provide a G = +2, our AD8079 is a fixed gain of +2 buffer. Creating Larger Crosspoint Arrays The AD8108/AD8109 are high density building blocks for cre- ating crosspoint arrays of dimensions larger than 8 × 8. Various features such as output disable, chip enable, and gain-of-one and -two options are useful for creating larger arrays. For very large arrays, they can be used along with the AD8116, a 16 × 16 video crosspoint device. In addition, systems that require more inputs than outputs can use the AD8110 and/or the AD8111, which are (gain-of-one and gain-of-two) 16 × 8 crosspoint switches. The first consideration in constructing a larger crosspoint is to determine the minimum number of devices required. The 8 × 8 architecture of the AD8108/AD8109 contains 64 “points,” which is a factor of 16 greater than a 4 × 1 crosspoint. The PC board area and power consumption savings are readily apparent when compared to using these smaller devices. For a nonblocking crosspoint, the number of points required is the product of the number of inputs multiplied by the number of outputs. Nonblocking requires that the programming of a given input to one or more outputs does not restrict the avail- ability of that input to be a source for any other outputs. Some nonblocking crosspoint architectures will require more than this minimum as calculated above. Also, there are blocking architectures that can be constructed with fewer devices than this minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system. The basic concept in constructing larger crosspoint arrays is to connect inputs in parallel in a horizontal direction and to “wire- OR” the outputs together in the vertical direction. The meaning of horizontal and vertical can best be understood by looking at a diagram. An 8 input by 16 output crosspoint array can be constructed as shown in Figure 42. This configuration parallels two inputs per channel and does not require paralleling of any outputs. Inputs are easier to parallel than outputs, because there are lower parasitics involved. For a 16 × 8 crosspoint, the AD8110 (gain of one) or AD8111 (gain of two) device can be used. These devices are already configured into a 16 × 8 crosspoint in a single device.

16 OUTPUTS

Figure 42. 8 × 16 Crosspoint Array Using Two AD8108s Figure 43. 16 × 16 Crosspoint Array Using Four Figure 44. 24 × 24 Crosspoint Array Using Nine AD8108s according to which system specifications are most important. which has a higher disabled output impedance than the AD8109. Figure 45. Nonblocking 64 × 8 Array with Gain-of-Two than one crosspoint channel per video channel.

–18– REV. 0 Some systems use twisted-pair wiring to carry video signals. These systems utilize differential signals and can lower costs because they use lower cost cables, connectors and termination methods. They also have the ability to lower crosstalk and reject common-mode signals, which can be important for equipment that operates in noisy environments or where common-mode voltages are present between transmitting and receiving equipment. In such systems, the video signals are differential; there is a positive and negative (or inverted) version of the signals. These complementary signals are transmitted onto each of the two wires of the twisted pair, yielding a first order zero common- mode signal. At the receive end, the signals are differentially received and converted back into a single-ended signal. When switching these differential signals, two channels are required in the switching element to handle the two differential signals that make up the video channel. Thus, one differential video channel is assigned to a pair of crosspoint channels, both input and output. For a single AD8108/AD8109, four differen- tial video channels can be assigned to the eight inputs and eight outputs. This will effectively form a 4 × 4 differential crosspoint switch. Programming such a device will require that inputs and outputs be programmed in pairs. This information can be deduced by inspection of the programming format of the AD8108/AD8109 and the requirements of the system. There are other analog video formats requiring more than one analog circuit per video channel. One two-circuit format that is commonly being used in systems such as satellite TV, digital cable boxes and higher quality VCRs, is called S-video or Y/C video. This format carries the brightness (luminance or Y) por- tion of the video signal on one channel and the color (chromi- nance, chroma or C) on a second channel. Since S-video also uses two separate circuits for one video chan- nel, creating a crosspoint system requires assigning one video channel to two crosspoint channels as in the case of a differen- tial video system. Aside from the nature of the video format, other aspects of these two systems will be the same. There are yet other video formats using three channels to carry the video information. Video cameras produce RGB (red, green, blue) directly from the image sensors. RGB is also the usual format used by computers internally for graphics. RGB can also be converted to Y, R–Y, B–Y format, sometimes called YUV format. These three-circuit, video standards are referred to as component analog video. The component video standards require three crosspoint chan- nels per video channel to handle the switching function. In a fashion similar to the two-circuit video formats, the inputs and outputs are assigned in groups of three and the appropriate logic programming is performed to route the video signals. CROSSTALK Many systems, such as broadcast video, that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in close proximity in a system, as will undoubtedly be the case in a system that uses the AD8108/ AD8109, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more AD8108/AD8109s. TYPES OF CROSSTALK Crosstalk can be propagated by means of any of three methods. These fall into the categories of electric field, magnetic field and sharing of common impedances. This section will explain these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propa- gates across a stray capacitance (e.g., free space) and couples with the receiver and induces a voltage. This voltage is an un- wanted crosstalk signal in any channel that receives it. Currents flowing in conductors create magnetic fields that circu- late around the currents. These magnetic fields will then gener- ate voltages in any other conductors whose paths they link. The undesired induced voltages in these other channels are crosstalk signals. The channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. The power supplies, grounds and other signal return paths of a multichannel system are generally shared by the various chan- nels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the com- mon impedance. All these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving addi- tional circuits in parallel in a given configuration can actually reduce the crosstalk. Areas of Crosstalk For a practical AD8108/AD8109 circuit, it is required that it be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrin- sic device. This, however, raises the issue that a system’s crosstalk is a combination of the intrinsic crosstalk of the devices in addi- tion to the circuit board to which they are mounted. It is impor- tant to try to separate these two areas of crosstalk when attempting to minimize its effect. In addition, crosstalk can occur among the inputs to a cross- point and among the outputs. It can also occur from input to output. Techniques will be discussed for diagnosing which part of a system is contributing to crosstalk. Measuring Crosstalk Crosstalk is measured by applying a signal to one or more chan- nels and measuring the relative strength of that signal on a de- sired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by: |XT| = 20 log 10 (Asel(s)/Atest(s))

–19–REV. 0 where s = jω is the Laplace transform variable, Asel(s) is the amplitude of the crosstalk-induced signal in the selected channel and Atest(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal will have a phase relative to the test signal asso- ciated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magni- tude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can be- come extremely large. For example, in the case of the 8 × 8 matrix of the AD8108/AD8109, we can examine the number of crosstalk terms that can be considered for a single channel, say IN00 input. IN00 is programmed to connect to one of the AD8108/AD8109 outputs where the measurement can be made. We can first measure the crosstalk terms associated with driving a test signal into each of the other seven inputs one at a time. We can then measure the crosstalk terms associated with driving a parallel test signal into all seven other inputs taken two at a time in all possible combinations; and then three at a time, etc., until, finally, there is only one way to drive a test signal into all seven other inputs. Each of these cases is legitimately different from the others and might yield a unique value depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then to specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addi- tion, if the possible combinations and permutations for connect- ing inputs to the other (not used for measurement) outputs are taken into consideration, the numbers rather quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8108/AD8109s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One com- mon method is to measure “all hostile” crosstalk. This term means that the crosstalk to the selected channel is measured, while all other system channels are driven in parallel. In general, this will yield the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements will generally be higher than those of more distant channels, so they can serve as a worst case measure for any other one-channel or two-channel crosstalk measurements. Input and Output Crosstalk The flexible programming capability of the AD8108/AD8109 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustra- tive. A given input channel (IN03 in the middle for this ex- ample) can be programmed to drive OUT03. The input to IN03 is just terminated to ground (via 50 Ω or 75 Ω ) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT03 disabled. Since grounded IN03 is programmed to drive OUT03, there should be no signal present. Any signal that is present can be attributed to the other seven hostile input signals, because no other outputs are driven (they are all disabled). Thus, this method measures the all- hostile input contribution to crosstalk into IN03. Of course, the method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel is driven (IN00 for example) and all outputs other than a given output (IN03 in the middle) are programmed to connect to IN00. OUT03 is programmed to connect to IN07 (far away from IN00), which is terminated to ground. Thus OUT03 should not have a signal present since it is listening to a quiet input. Any signal measured at the OUT03 can be attributed to the output crosstalk of the other seven hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output imped- ance of the sources that drive the inputs. The lower the im- pedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termi- nation resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies the magnitude of the crosstalk will be given by: |XT| = 20 log 10 [(RS CM) × s] where RS is the source resistance, CM is the mutual capacitance between the test signal circuit and the selected circuit, and s is the Laplace transform variable. From the equation it can be observed that this crosstalk mecha- nism has a high pass nature; it can also be minimized by reduc- ing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8108/AD8109 is specified with excellent differential gain and phase when driving a standard 150 Ω video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. These currents will induce crosstalk via the mutual inductance of the output pins and bond wires of the AD8108/AD8109.

–20– REV. 0 All trademarks are property of their respective holders. From a circuit standpoint, this output crosstalk mechanism looks like a transformer, with a mutual inductance between the windings, that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by: |XT| = 20 log 10 (Mxy × s/RL) where Mxy is the mutual inductance of output x to output y and RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing R L. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. PCB Layout Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that must be carefully detailed are grounding, shielding, signal routing and supply bypassing. The packaging of the AD8108/AD8109 is designed to help keep the crosstalk to a minimum. Each input is separated from each other input by an analog ground pin. All of these AGNDs should be directly connected to the ground plane of the circuit board. These ground pins provide shielding, low impedance return paths and physical separation for the inputs. All of these help to reduce crosstalk. Each output is separated from its two neighboring outputs by an analog ground pin in addition to an analog supply pin of one polarity or the other. Each of these analog supply pins provides power to the output stages of only the two nearest outputs. These supply pins and analog grounds provide shielding, physi- cal separation and a low impedance supply for the outputs. Individual bypassing of each of these supply pins, with a 0.01 µF chip capacitor directly to the ground plane, minimizes high frequency output crosstalk via the mechanism of sharing com- mon impedances. Each output also has an on-chip compensation capacitor that is individually tied the nearby analog ground pins AGND00 through AGND07. This technique reduces crosstalk by prevent- ing the currents that flow in these paths from sharing a common impedance on the IC and in the package pins. These AGNDxx signals should all be directly connected to the ground plane. The input and output signals will have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. Vias should be located as close to the IC as possible to carry the inputs and outputs to the inner layer. The only place the input and output signals surface is at the input termination resistors and the out- put series back termination resistors. These signals should also be separated, to the extent possible, as soon as they emerge from the IC package. Evaluation Board A four-layer evaluation board for the AD8108/AD8109 is avail- able. The exact same board and external components are used for each device. The only difference is the device itself, which offers a selection of a gain of unity or gain of two through the analog channels. This board has been carefully laid out and tested to demonstrate the specified high speed performance of the device. Figure 46 shows the schematic of the evaluation board. Figure 47 shows the component side silk-screen. The layouts of the board’s four layers are given in Figures 48, 49, 50 and 51. The evaluation board package includes the following:

• Fully populated board with BNC-type connectors.
• Windows™ based software for controlling the board from a PC via the printer port.
• Custom cable to connect evaluation board to PC.
• Disk containing Gerber files of board layout.

59 DATA OUT

57 DATA IN

Figure 46. Evaluation Board Schematic

–26– REV. 0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead Plastic TQFP (ST-80A) SEATING PLANE 0.063 (1.60) MAX 0.030 (0.75) 0.020 (0.50) 0.003 (0.08) MAX 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) 0.011 (0.27) 0.007 (0.17) 0.559 (14.20) 0.543 (13.80) 0.476 (12.10) 0.469 (11.90) 0.476 (12.10) 0.469 (11.90) 0.559 (14.20) 0.543 (13.80) TOP VIEW (PINS DOWN) 6180 0.020 (0.50) BSC

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–28– C3209–8–10/97PRINTED IN U.S.A.