AD8105ABPZ

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600 MHz, 32 × 16 Buffered

Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

High channel count, 32 × 16 high speed, nonblocking switch array Differential or single-ended operation Differential G = +1 (AD8104) or G = +2 (AD8105) Pin compatible with AD8117/AD8118, 32 × 32 switch arrays Flexible power supplies Single +5 V supply, or dual ±2.5 V supplies Serial or parallel programming of switch array High impedance output disable allows connection of multiple devices with minimal loading on output bus Excellent video performance >50 MHz 0.1 dB gain flatness 0.05% differential gain error (RL = 150 Ω) 0.05° phase error (RL = 150 Ω) Excellent ac performance Bandwidth: 600 MHz Slew rate: 1800 V/µs Settling time: 2.5 ns to 1% Low power of 1.7 W Low all hostile crosstalk < −70 dB at 5 MHz < −40 dB at 600 MHz Reset pin allows disabling of all outputs (connected through a capacitor to ground provides power-on reset capability) 304-ball BGA package (31 mm × 31 mm)

APPLICATIONS

Routing of high speed signals including RGB and component video routing KVM Compressed video (MPEG, wavelet) Data communications FUNCTIONAL BLOCK DIAGRAM INPUT RECEIVER G = +1* G = +2** OUTPUT BUFFER G = +1 512 SET INDIVIDUAL, OR RESET ALL OUTPUTS TO OFF ENABLE/DISABLE VPOS VNEG VOCM

32 INPUT PAIRS

16 OUTPUT PAIRS

D0 D1 D2 D3 D4 D5 VDD DGND AD8104/ AD8105 192-BIT SHIFT REGISTER WITH 6-BIT PARALLEL LOADING PARALLEL LATCH DECODE 16 × 6:32 DECODERS *AD8104 ONLY **AD8105 ONLY 06612-001 NO CONNECT Figure 1. GENERAL DESCRIPTION The AD8104/AD8105 are high speed, 32 × 16 analog crosspoint switch matrices. They offer 600 MHz bandwidth and slew rate of

1800 V/µs for high resolution computer graphics (RGB) signal

switching. With less than −70 dB of crosstalk and −90 dB isola- tion (at 5 MHz), the AD8104/AD8105 are useful in many high speed applications. The 0.1 dB flatness, which is greater than

50 MHz, makes the AD8104/AD8105 ideal for composite video

switching. The AD8104/AD8105 include 16 independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus. The AD8104 has a differential gain of +1, while the AD8105 has a differential gain of +2 for ease of use in back-terminated load applications. They operate as fully differential devices or can be configured for single-ended operation. Either a single +5 V supply or dual ±2.5 V supplies can be used, while consuming only 340 mA of idle current with all outputs enabled. The channel switching is performed via a double-buffered, serial digital control (which can accommodate daisy-chaining of several devices), or via a parallel control, allowing updating of an individual output without reprogram- ming the entire array. The AD8104/AD8105 are packaged in a 304-ball BGA package and are available over the extended industrial temperature range of −40°C to +85°C.

Rev. A | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

4/16—Rev. 0 to Rev. A 6/07—Revision 0: Initial Version

Rev. A | Page 3 of 36 SPECIFICATIONS VS = ±2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted. Table 1. AD8104/AD8105 Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth 200 mV p-p, typical channel 600 MHz

2 V p-p, typical channel 420/525 MHz

Gain Flatness 0.1 dB, 200 mV p-p 100/50 MHz 0.1 dB, 2 V p-p 70/50 MHz Propagation Delay 2 V p-p 1.3 ns Settling Time 1%, 2 V step 2.5 ns Slew Rate 2 V step, peak 1800 V/µs

2 V step, 10% to 90% 1500 V/µs

NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL, RL = 150 Ω 0.05 % Differential Phase Error NTSC or PAL, RL = 150 Ω 0.05 Degrees Crosstalk, All Hostile f = 5 MHz −80/−70 dB f = 10 MHz −72/−68 dB f = 100 MHz −48/−50 dB f = 600 MHz −40/−50 dB Off Isolation, Input to Output f = 5 MHz, one channel −92 dB Input Voltage Noise 0.1 MHz to 50 MHz 45/53 nV/√Hz DC PERFORMANCE Voltage Gain Differential +1/+2 V/V Gain Error ±1 % No load ±1 ±3 % Gain Matching Channel-to-channel ±1 % Differential Offset ±5 ±25 mV Common-Mode Offset ±25 ±90 mV OUTPUT CHARACTERISTICS Output Impedance DC, enabled 0.1 Ω Disabled, differential 30 kΩ Output Disable Capacitance Disabled 4 pF Output Leakage Current Disabled 1 µA Output Voltage Range No load 2.8 3.8 V p-p VOCM Input Range VOUT, diff = 2 V p-p −0.5 +0.8 V VOUT, diff = 2.8 V p-p −0.25 +0.6 V Output Swing Limit Single-ended output −1.3 +1.3 V Output Current Maximum operating signal 30 mA INPUT CHARACTERISTICS Input Voltage Range Common mode, VIN, diff = 2 V p-p −2 +2 V Differential 2/1 V Common-Mode Rejection Ratio f = 10 MHz 48 dB Input Capacitance Any switch configuration 2 pF Input Resistance Differential 5 kΩ Input Offset Current 1 μA VOCM Input Bias Current 64 µA VOCM Input Impedance 4 kΩ

Rev. A | Page 4 of 36 AD8104/AD8105 Parameter Test Conditions/Comments Min Typ Max Unit SWITCHING CHARACTERISTICS Enable On Time 50% update to 1% settling 100 ns Switching Time, 2 V Step 50% update to 1% settling 100 ns Switching Transient (Glitch) Differential 40 mV p-p POWER SUPPLIES Supply Current VPOS, outputs enabled, no load 340 420 mA VPOS, outputs disabled 210 240 mA VNEG, outputs enabled, no load 340 420 mA VNEG, outputs disabled 210 240 mA VDD, outputs enabled, no load 1.2 mA Supply Voltage Range 4.5 to 5.5 V PSRR VNEG, VPOS, f = 1 MHz 85 dB VOCM, f = 1 MHz 75 dB OPERATING TEMPERATURE RANGE Temperature Range Operating (still air) −40 to +85 °C θJA Operating (still air) 14 °C/W θJC Operating (still air) 1 °C/W

Specifications subject to change without notice. Figure 2. Timing Diagram, Serial Mode Table 3. Logic Levels

0.5 V max

Specifications subject to change without notice. Figure 3. Timing Diagram, Parallel Mode Table 5. Logic Levels

soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature

Figure 5. 304-Ball BGA Pin Configuration (Bottom View)

Figure 6. 304-Ball BGA Pin Configuration (Top View) Table 8. Pin Function Descriptions A1 VPOS Analog Positive Power Supply. A2 VPOS Analog Positive Power Supply. A3 VPOS Analog Positive Power Supply. A20 VPOS Analog Positive Power Supply. A21 VPOS Analog Positive Power Supply. A22 VPOS Analog Positive Power Supply. A23 VPOS Analog Positive Power Supply. B1 VPOS Analog Positive Power Supply. B2 VPOS Analog Positive Power Supply. B3 VPOS Analog Positive Power Supply. B4 VPOS Analog Positive Power Supply.

Rev. A | Page 10 of 36 Pin No. Mnemonic Description B10 NC No Connect. B11 NC No Connect. B12 NC No Connect. B13 NC No Connect. B14 NC No Connect. B15 NC No Connect. B16 NC No Connect. B17 NC No Connect. B18 NC No Connect. B19 NC No Connect. B20 NC No Connect. B21 VPOS Analog Positive Power Supply. B22 VPOS Analog Positive Power Supply. B23 VPOS Analog Positive Power Supply. C1 VPOS Analog Positive Power Supply. C2 VPOS Analog Positive Power Supply. C3 VPOS Analog Positive Power Supply. C4 VPOS Analog Positive Power Supply. C5 VNEG Analog Negative Power Supply. C6 VNEG Analog Negative Power Supply. C7 VNEG Analog Negative Power Supply. C8 VNEG Analog Negative Power Supply. C9 VNEG Analog Negative Power Supply. C10 VNEG Analog Negative Power Supply. C11 VPOS Analog Positive Power Supply. C12 VPOS Analog Positive Power Supply. C13 VPOS Analog Positive Power Supply. C14 VNEG Analog Negative Power Supply. C15 VNEG Analog Negative Power Supply. C16 VNEG Analog Negative Power Supply. C17 VNEG Analog Negative Power Supply. C18 VNEG Analog Negative Power Supply. C19 VNEG Analog Negative Power Supply. C20 VPOS Analog Positive Power Supply. C21 VPOS Analog Positive Power Supply. C22 VPOS Analog Positive Power Supply. C23 VPOS Analog Positive Power Supply. D1 VPOS Analog Positive Power Supply. D2 IP0 Input Number 0, Positive Phase. D3 VPOS Analog Positive Power Supply. D4 VNEG Analog Negative Power Supply. D5 VOCM Output Common-Mode Reference Supply. D6 VNEG Analog Negative Power Supply. D7 VNEG Analog Negative Power Supply. D8 VNEG Analog Negative Power Supply. D9 VNEG Analog Negative Power Supply. D10 VNEG Analog Negative Power Supply. D11 VPOS Analog Positive Power Supply. D12 VPOS Analog Positive Power Supply. D13 VPOS Analog Positive Power Supply. D14 VNEG Analog Negative Power Supply. D15 VNEG Analog Negative Power Supply. Pin No. Mnemonic Description D16 VNEG Analog Negative Power Supply. D17 VNEG Analog Negative Power Supply. D18 VNEG Analog Negative Power Supply. D19 VOCM Output Common-Mode Reference Supply. D20 VNEG Analog Negative Power Supply. D21 VPOS Analog Positive Power Supply. D22 VPOS Analog Positive Power Supply. D23 IN16 Input Number 16, Negative Phase. E1 IP1 Input Number 1, Positive Phase. E2 IN0 Input Number 0, Negative Phase. E3 VNEG Analog Negative Power Supply. E4 VOCM Output Common-Mode Reference Supply. E20 VOCM Output Common-Mode Reference Supply. E21 VNEG Analog Negative Power Supply. E22 IN17 Input Number 17, Negative Phase. E23 IP16 Input Number 16, Positive Phase. F1 IN1 Input Number 1, Negative Phase. F2 IP2 Input Number 2, Positive Phase. F3 VNEG Analog Negative Power Supply. F4 VDD Logic Positive Power Supply. F20 VDD Logic Positive Power Supply. F21 VNEG Analog Negative Power Supply. F22 IP17 Input Number 17, Positive Phase. F23 IN18 Input Number 18, Negative Phase. G1 IP3 Input Number 3, Positive Phase. G2 IN2 Input Number 2, Negative Phase. G3 VNEG Analog Negative Power Supply. G4 DGND Logic Negative Power Supply. G20 DGND Logic Negative Power Supply. G21 VNEG Analog Negative Power Supply. G22 IN19 Input Number 19, Negative Phase. G23 IP18 Input Number 18, Positive Phase. H1 IN3 Input Number 3, Negative Phase. H2 IP4 Input Number 4, Positive Phase. H3 VNEG Analog Negative Power Supply. H4 DATA OUT Control Pin: Serial Data Out. H20 RESET Control Pin: Second Rank Data Reset. H21 VNEG Analog Negative Power Supply. H22 IP19 Input Number 19, Positive Phase. H23 IN20 Input Number 20, Negative Phase. J1 IP5 Input Number 5, Positive Phase. J2 IN4 Input Number 4, Negative Phase. J3 VNEG Analog Negative Power Supply. J4 CLK Control Pin: Serial Data Clock. J20 UPDATE Control Pin: Second Rank Write Strobe. J21 VNEG Analog Negative Power Supply. J22 IN21 Input Number 21, Negative Phase. J23 IP20 Input Number 20, Positive Phase. K1 IN5 Input Number 5, Negative Phase.

Rev. A | Page 11 of 36 Pin No. Mnemonic Description K2 IP6 Input Number 6, Positive Phase. K3 VNEG Analog Negative Power Supply. K4 DATA IN Control Pin: Serial Data In. K20 WE Control Pin: First Rank Write Strobe. K21 VNEG Analog Negative Power Supply. K22 IP21 Input Number 21, Positive Phase. K23 IN22 Input Number 22, Negative Phase. L1 IP7 Input Number 7, Positive Phase. L2 IN6 Input Number 6, Negative Phase. L3 VPOS Analog Positive Power Supply. L4 SER/PAR Control Pin: Serial/Parallel Mode Select. L20 D5 Control Pin: Input Address Bit 5. L21 VPOS Analog Positive Power Supply. L22 IN23 Input Number 23, Negative Phase. L23 IP22 Input Number 22, Positive Phase. M1 IN7 Input Number 7, Negative Phase. M2 IP8 Input Number 8, Positive Phase. M3 VPOS Analog Positive Power Supply. M4 DGND Logic Negative Power Supply M20 D4 Control Pin: Input Address Bit 4. M21 VPOS Analog Positive Power Supply. M22 IP23 Input Number 23, Positive Phase. M23 IN24 Input Number 24, Negative Phase. N1 IP9 Input Number 9, Positive Phase. N2 IN8 Input Number 8, Negative Phase. N3 VPOS Analog Positive Power Supply. N4 A3 Control Pin: Output Address Bit 3. N20 D3 Control Pin: Input Address Bit 3. N21 VPOS Analog Positive Power Supply. N22 IN25 Input Number 25, Negative Phase. N23 IP24 Input Number 24, Positive Phase. P1 IN9 Input Number 9, Negative Phase. P2 IP10 Input Number 10, Positive Phase. P3 VNEG Analog Negative Power Supply. P4 A2 Control Pin: Output Address Bit 2. P20 D2 Control Pin: Input Address Bit 2. P21 VNEG Analog Negative Power Supply. P22 IP25 Input Number 25, Positive Phase. P23 IN26 Input Number 26, Negative Phase. R1 IP11 Input Number 11, Positive Phase. R2 IN10 Input Number 10, Negative Phase. R3 VNEG Analog Negative Power Supply. R4 A1 Control Pin: Output Address Bit 1. R20 D1 Control Pin: Input Address Bit 1. R21 VNEG Analog Negative Power Supply. R22 IN27 Input Number 27, Negative Phase. R23 IP26 Input Number 26, Positive Phase. T1 IN11 Input Number 11, Negative Phase. T2 IP12 Input Number 12, Positive Phase. T3 VNEG Analog Negative Power Supply. T4 A0 Control Pin: Output Address Bit 0. T20 D0 Control Pin: Input Address Bit 0. Pin No. Mnemonic Description T21 VNEG Analog Negative Power Supply. T22 IP27 Input Number 27, Positive Phase. T23 IN28 Input Number 28, Negative Phase. U1 IP13 Input Number 13, Positive Phase. U2 IN12 Input Number 12, Negative Phase. U3 VNEG Analog Negative Power Supply. U4 VDD Logic Positive Power Supply. U20 VDD Logic Positive Power Supply. U21 VNEG Analog Negative Power Supply. U22 IN29 Input Number 29, Negative Phase. U23 IP28 Input Number 28, Positive Phase. V1 IN13 Input Number 13, Negative Phase. V2 IP14 Input Number 14, Positive Phase. V3 VNEG Analog Negative Power Supply. V4 DGND Logic Negative Power Supply. V20 DGND Logic Negative Power Supply. V21 VNEG Analog Negative Power Supply. V22 IP29 Input Number 29, Positive Phase. V23 IN30 Input Number 30, Negative Phase. W1 IP15 Input Number 15, Positive Phase. W2 IN14 Input Number 14, Negative Phase. W3 VNEG Analog Negative Power Supply. W4 VOCM Output Common-Mode Reference Supply. W20 VOCM Output Common-Mode Reference Supply. W21 VNEG Analog Negative Power Supply. W22 IN31 Input Number 31, Negative Phase. W23 IP30 Input Number 30, Positive Phase. Y1 IN15 Input Number 15, Negative Phase. Y2 VPOS Analog Positive Power Supply. Y3 VPOS Analog Positive Power Supply. Y4 VNEG Analog Negative Power Supply. Y5 VOCM Output Common-Mode Reference Supply. Y6 VNEG Analog Negative Power Supply. Y7 VNEG Analog Negative Power Supply. Y8 VNEG Analog Negative Power Supply. Y9 VNEG Analog Negative Power Supply. Y10 VNEG Analog Negative Power Supply. Y11 VPOS Analog Positive Power Supply. Y12 VPOS Analog Positive Power Supply. Y13 VPOS Analog Positive Power Supply. Y14 VNEG Analog Negative Power Supply. Y15 VNEG Analog Negative Power Supply. Y16 VNEG Analog Negative Power Supply. Y17 VNEG Analog Negative Power Supply. Y18 VNEG Analog Negative Power Supply. Y19 VOCM Output Common-Mode Reference Supply. Y20 VNEG Analog Negative Power Supply. Y21 VPOS Analog Positive Power Supply. Y22 IP31 Input Number 31, Positive Phase.

Rev. A | Page 12 of 36 Pin No. Mnemonic Description Y23 VPOS Analog Positive Power Supply. AA1 VPOS Analog Positive Power Supply. AA2 VPOS Analog Positive Power Supply. AA3 VPOS Analog Positive Power Supply. AA4 VPOS Analog Positive Power Supply. AA5 VNEG Analog Negative Power Supply. AA6 VNEG Analog Negative Power Supply. AA7 VNEG Analog Negative Power Supply. AA8 VNEG Analog Negative Power Supply. AA9 VNEG Analog Negative Power Supply. AA10 VNEG Analog Negative Power Supply. AA11 VPOS Analog Positive Power Supply. AA12 VPOS Analog Positive Power Supply. AA13 VPOS Analog Positive Power Supply. AA14 VNEG Analog Negative Power Supply. AA15 VNEG Analog Negative Power Supply. AA16 VNEG Analog Negative Power Supply. AA17 VNEG Analog Negative Power Supply. AA18 VNEG Analog Negative Power Supply. AA19 VNEG Analog Negative Power Supply. AA20 VPOS Analog Positive Power Supply. AA21 VPOS Analog Positive Power Supply. AA22 VPOS Analog Positive Power Supply. AA23 VPOS Analog Positive Power Supply. AB1 VPOS Analog Positive Power Supply. AB2 VPOS Analog Positive Power Supply. AB3 VPOS Analog Positive Power Supply. AB4 OP0 Output Number 0, Positive Phase. AB5 ON0 Output Number 0, Negative Phase. AB6 OP2 Output Number 2, Positive Phase. AB7 ON2 Output Number 2, Negative Phase. AB8 OP4 Output Number 4, Positive Phase. AB9 ON4 Output Number 4, Negative Phase. AB10 OP6 Output Number 6, Positive Phase. AB11 ON6 Output Number 6, Negative Phase. AB12 OP8 Output Number 8, Positive Phase. AB13 ON8 Output Number 8, Negative Phase. Pin No. Mnemonic Description AB14 OP10 Output Number 10, Positive Phase. AB15 ON10 Output Number 10, Negative Phase. AB16 OP12 Output Number 12, Positive Phase. AB17 ON12 Output Number 12, Negative Phase. AB18 OP14 Output Number 14, Positive Phase. AB19 ON14 Output Number 14, Negative Phase. AB20 VPOS Analog Positive Power Supply. AB21 VPOS Analog Positive Power Supply. AB22 VPOS Analog Positive Power Supply. AB23 VPOS Analog Positive Power Supply. AC1 VPOS Analog Positive Power Supply. AC2 VPOS Analog Positive Power Supply. AC3 VPOS Analog Positive Power Supply. AC4 VPOS Analog Positive Power Supply. AC5 OP1 Output Number 1, Positive Phase. AC6 ON1 Output Number 1, Negative Phase. AC7 OP3 Output Number 3, Positive Phase. AC8 ON3 Output Number 3, Negative Phase. AC9 OP5 Output Number 5, Positive Phase. AC10 ON5 Output Number 5, Negative Phase. AC11 OP7 Output Number 7, Positive Phase. AC12 ON7 Output Number 7, Negative Phase. AC13 OP9 Output Number 9, Positive Phase. AC14 ON9 Output Number 9, Negative Phase. AC15 OP11 Output Number 11, Positive Phase. AC16 ON11 Output Number 11, Negative Phase. AC17 OP13 Output Number 13, Positive Phase. AC18 ON13 Output Number 13, Negative Phase. AC19 OP15 Output Number 15, Positive Phase. AC20 ON15 Output Number 15, Negative Phase. AC21 VPOS Analog Positive Power Supply. AC22 VPOS Analog Positive Power Supply. AC23 VPOS Analog Positive Power Supply.

Table 9. Operation Truth Table of logic in 192-bit shift register is unchanged. register appears at DATA OUT 192 clock cycles later.

0 X X D0…D52

loaded into the shift register location addressed by A0 to A3. transfers into the parallel latches that control the switch array. 1 X X X X 1 1 No change in logic.

4 TO 16 DECODER

Figure 7. Logic Diagram

Rev. A | Page 25 of 36 THEORY OF OPERATION The AD8104/AD8105 are fully differential crosspoint arrays with 16 outputs, each of which can be connected to any one of 32 inputs. Organized by output row, 32 switchable input transconductance stages are connected to each output buffer to form 32-to-1 multiplexers. There are 16 of these multiplexers, each with its inputs wired in parallel, for a total array of 512 transconductance stages forming a multicast-capable crosspoint switch. Decoding logic for each output selects one (or none) of the transconductance stages to drive the output stage. The enabled transconductance stage drives the output stage, and feedback forms a closed-loop amplifier with a differential gain of +1 (the difference between the output voltages is equal to the difference between the input voltages). A second feedback loop controls the common-mode output level, forcing the average of the differential output voltages to match the voltage on the VOCM reference pin. Although each output has an independent common-mode control loop, the VOCM reference is common for the entire chip, and as such needs to be driven with a low impedance to avoid crosstalk. Each differential input to the AD8104/AD8105 is buffered by a receiver. The purpose of this receiver is to provide an extended input common-mode range, and to remove this common mode from the signal chain. Like the output multiplexers, the input receiver has both a differential loop and a common-mode control loop. A mask-programmable feedback network sets the closed-loop differential gain. For the AD8104, this differential gain is +1, and for the AD8105, this differential gain is +2. The receiver has an input stage that does not respond to the common mode of the signal. This architecture, along with the attenuating feedback network, allows the user to apply input voltages that extend from rail to rail. Excess differential loop gain bandwidth product reduces the effect of the closed-loop gain on the bandwidth of the device. The output stage of the AD8104/AD8105 is designed for low differential gain and phase error when driving composite video signals. It also provides slew current for fast pulse response when driving component video signals. Unlike many multi- plexer designs, these requirements are balanced such that large signal bandwidth is very similar to small signal bandwidth. The design load is 150 Ω, but provisions are made to drive loads as low as 75 Ω as long as on-chip power dissipation limits are not exceeded. The outputs of the AD8104/AD8105 can be disabled to minimize on-chip power dissipation. When disabled, there is a feedback network of 25 kΩ between the differential outputs. This high impedance allows multiple ICs to be bussed together without additional buffering. Care must be taken to reduce output capacitance, which results in more overshoot and frequency domain peaking. A series of internal amplifiers drive internal nodes such that a wideband high impedance is presented at the disabled output, even while the output bus is under large signal swings. When the outputs are disabled and driven externally, the voltage applied to them should not exceed the valid output swing range for the AD8104/AD8105 in order to keep these internal amplifiers in their linear range of operation. Applying excess differential voltages to the disabled outputs can cause damage to the AD8104/AD8105 and should be avoided (see the Absolute Maximum Ratings section for guidelines). The connection of the AD8104/AD8105 is controlled by a flexible TTL-compatible logic interface. Either parallel or serial loading into a first rank of latches preprograms each output. A global update signal moves the programming data into the second rank of latches, simultaneously updating all outputs. In serial mode, a serial-out pin allows devices to be daisy-chained together for single-pin programming of multiple ICs. A power- on reset pin is available to avoid bus conflicts by disabling all outputs. This power-on reset clears the second rank of latches, but does not clear the first rank of latches. In parallel mode, to quickly clear the first rank, a broadcast parallel programming feature is available. In serial mode, preprogramming individual inputs is not possible and the entire shift register needs to be flushed. The AD8104/AD8105 can operate on a single +5 V supply, powering both the signal path (with the VPOS/VNEG supply pins), and the control logic interface (with the VDD/DGND supply pins). However, to easily interface to ground-referenced video signals, split supply operation is possible with ±2.5 V supplies. In this case, a flexible logic interface allows the control logic supplies (VDD/DGND) to be run off +2 V/0 V to +5 V/0 V while the core remains on split supplies. Additional flexibility in the analog output common-mode level facilitates unequal split supplies. If +3 V/–2 V supplies to +2 V/–3 V supplies are desired, the VOCM pin can still be set to 0 V for ground- referenced video signals.

Rev. A | Page 26 of 36 APPLICATIONS INFORMATION PROGRAMMING The AD8104/AD8105 have two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 192 bits can be provided to update the entire matrix each time. The second option allows for changing the programming of a single output via a parallel interface. The serial option requires fewer signals, but more time (clock cycles) for changing the programming, while the parallel programming technique requires more signals, but can change a single output at a time and requires fewer clock cycles to complete programming. Serial Programming Description The serial programming mode uses the CLK, DATA IN, UPDATE, and SER/PAR device pins. The first step is to assert a low on SER/PAR in order to enable the serial programming mode. The parallel clock WE should be held high during the entire serial programming operation. The UPDATE signal should be high during the time that data is shifted into the serial port of the device. Although the data still shifts in when UPDATE is low, the transparent, asynchronous latches allow the shifting data to reach the matrix. This causes the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in at every falling edge of CLK. A total of 192 bits must be shifted in to complete the program- ming. For each of the 16 outputs, there are five bits (D0 to D4) that determine the source of its input followed by one bit (D5) that determines the enabled state of the output. If D5 is low (output disabled), the five associated bits (D0 to D4) do not matter, because no input is switched to that output. These comprise the first 96 bits of DATA IN. The remaining 96 bits of DATA IN should be set to zero. If a string of 96 zeros is not suffixed to the first 96 bits of DATA IN, a certain test mode is employed that can cause the device to draw up to 40% more supply current. The most significant output address data, the enable bit (D5), is shifted in first, followed by the input address (D4 to D0) entered sequentially with D4 first and D0 last. Each remaining output is programmed sequentially, until the least significant output address data is shifted in. At this point, UPDATE can be taken low, which programs the device according to the data that was just shifted in. The UPDATE latches are asynchronous and when UPDATE is low, they are transparent. If more than one AD8104/AD8105 device is to be serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK, UPDATE, and SER/PAR pins should be connected in parallel and operated as described previously. The serial data is input to the DATA IN pin of the first device of the chain, and it ripples through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence is 192 bits times the number of devices in the chain. Parallel Programming Description When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. In fact, parallel programming allows the modification of a single output at a time. Because this takes only one WE/UPDATE cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RESET signal does not reset all registers in the AD8104/ AD8105. When taken low, the RESET signal only sets each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs are not active at the same time. After initial power-up, the internal registers in the device generally have random data, even though the RESET signal has been asserted. If parallel programming is used to program one output, then that output is properly programmed, but the rest of the device has a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up. This ensures that the programming matrix is always in a known state. From then on, parallel programming can be used to modify a single output or more at a time. In similar fashion, if UPDATE is taken low after initial power-up, the random power-up data in the shift register is programmed into the matrix. Therefore, in order to prevent the crosspoint from being programmed into an unknown state, do not apply a low logic level to UPDATE after power is initially applied. Programming the full shift register one time to a desired state, by either serial or parallel programming after initial power-up, eliminates the possibility of programming the matrix to an unknown state. To change the programming of an output via parallel program- ming, SER/PAR and UPDATE should be taken high. The serial programming clock, CLK, should be left high during parallel programming. The parallel clock, WE, should start in the high state. The 4-bit address of the output to be programmed should be put on A0 to A3. The first five data bits (D0 to D4) should contain the information that identifies the input that is pro- grammed to the output that is addressed. The sixth data bit (D5) determines the enabled state of the output. If D5 is low (output disabled), then the data on D0 to D4 does not matter. After the desired address and data signals have been established, they can be latched into the shift register by a high to low transition of the WE signal. The matrix is not programmed,

pin, when taken low, causes all outputs to be in the disabled state. matrix each time; therefore, no special considerations apply. can be taken low to program the device. device out of any test mode. The AD8104/AD8105 has fully differential inputs and outputs. mode voltage, such as from a remote source over twisted pair. Figure 65. Input Receiver Equivalent Circuit ance appear to be 5 kΩ across the inputs. a back-terminated 75 Ω source).

equal to the difference applied between the two input terminals. applied input difference voltage is +2. mode gain for the AD8104 and AD8105 is +1 to the output. directly follows the reference voltage applied to the VOCM input. being a source of noise, offset, and crosstalk in the signal path. rate and bandwidth (an effective 150 Ω differential load). Figure 68. Example of Back-Terminated Differential Load respect to the ground (or VOCM) reference and is not rejected. a net increase in observed offset.

of +0.5. An AD8105 has a single-ended gain of +1. specifications for single-ended output designs. used, at an additional cost of one half the signal gain. that the crosstalk-inducing supply fluctuation is minimized. the two outputs were balanced. Figure 69. Example of Back-Terminated Single-Ended Load VNEG supply to a lower value than that from the VPOS supply. subject to a least amount of noise. common-mode control loop of all receivers and output drivers.

Rev. A | Page 32 of 36 Short-Circuit Output Conditions Although there is short-circuit current protection on the AD8104/AD8105 outputs, the output current can reach values of 80 mA into a grounded output. Any sustained operation with too many shorted outputs can exceed the maximum die temperature and can result in device failure (see the Absolute Maximum Ratings section). Crosstalk Many systems, such as broadcast video and KVM switches, that handle numerous analog signal channels, have strict require- ments for keeping the various signals from influencing any of the others in the system. Crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. When there are many signals in close proximity in a system, as is undoubtedly the case in a system that uses the AD8104/AD8105, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more crosspoint devices. Types of Crosstalk Crosstalk can be propagated by means of any of three methods. These fall into the categories of electric field, magnetic field, and sharing of common impedances. This section explains these effects. Every conductor can be both a radiator of electric fields and a receiver of electric fields. The electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance (for example, free space), couples with the receiver, and induces a voltage. This voltage is an unwanted crosstalk signal in any channel that receives it. Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields then generate voltages in any other conductors whose paths they link. The undesired induced voltages in these other channels are crosstalk signals. The channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to another. The power supplies, grounds, and other signal return paths of a multichannel system are generally shared by the various channels. When a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channels that share the common impedance. All these sources of crosstalk are vector quantities; therefore, the magnitudes cannot simply be added together to obtain the total crosstalk. In fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. Because the AD8104/AD8105 are fully differential designs, many sources of crosstalk either destructively cancel, or are common mode to the signal and can be rejected by a differential receiver. Areas of Crosstalk A practical AD8104/AD8105 circuit must be mounted to some sort of circuit board in order to connect it to power supplies and measurement equipment. Great care must be taken to create an evaluation board that adds minimum crosstalk to the intrinsic device. This, however, raises the issue that the crosstalk of a system is a combination of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. It is important to try to separate these two areas when attempting to minimize the effect of crosstalk. In addition, crosstalk can occur among the inputs to a cross- point and among the outputs. It can also occur from input to output. Techniques are discussed in the following sections for diagnosing which part of a system is contributing to crosstalk. Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as dB down from the magnitude of the test signal. The crosstalk is expressed by )(log20 10 sA sAXT TEST SEL where: s = jω, the Laplace transform variable. ASEL(s) is the amplitude of the crosstalk induced signal in the selected channel. ATEST(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal has a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure crosstalk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 32 × 16 matrix of the AD8104/AD8105, look at the number of crosstalk terms that can be considered for a single channel, for example, the input IN00. IN00 is programmed to connect to one of the AD8104/AD8105 outputs where the measurement can be made. First, the crosstalk terms associated with driving a test signal into each of the other 31 inputs can be measured one at a time, while applying no signal to IN00. Then the crosstalk terms associated with driving a parallel test signal into all 31 other inputs can be measured two at a time in all possible combinations, then three at a time, and so on, until, finally,

Rev. A | Page 33 of 36 there is only one way to drive a test signal into all 31 other inputs in parallel. Each of these cases is legitimately different from the others and may yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers rather quickly grow to astronomical proportions. If a larger crosspoint array of multiple AD8104/ AD8105 devices is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all-hostile crosstalk; this means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. In general, this yields the worst crosstalk number, but this is not always the case, due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements are generally higher than those of more distant channels, so they can serve as a worst-case measure for any other one-channel or two-channel crosstalk measurements. Input and Output Crosstalk Capacitive coupling is voltage-driven (dV/dt), but is generally a constant ratio. Capacitive crosstalk is proportional to input or output voltage, but this ratio is not reduced by simply reducing signal swings. Attenuation factors must be changed by changing impedances (lowering mutual capacitance), or destructive canceling must be utilized by summing equal and out of phase components. For high input impedance devices such as the AD8104/AD8105, capacitances generally dominate input- generated crosstalk. Inductive coupling is proportional to current (dI/dt), and often scales as a constant ratio with signal voltage, but also shows a dependence on impedances (load current). Inductive coupling can also be reduced by constructive canceling of equal and out of phase fields. In the case of driving low impedance video loads, output inductances contribute highly to output crosstalk. The flexible programming capability of the AD8104/AD8105 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input pair (IN07 in the middle for this example) can be programmed to drive OUT07 (also in the middle). The inputs to IN07 are just terminated to ground (via 50 Ω or 75 Ω) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT07 disabled. Since grounded IN07 is programmed to drive OUT07, no signal should be present. Any signal that is present can be attributed to the other 31 hostile input signals, because no other outputs are driven (they are all disabled). Thus, this method measures the all hostile input contribution to crosstalk into IN07. Of course, the method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN07 in the middle) are programmed to connect to IN00. OUT07 is programmed to connect to IN15 (far away from IN00), which is terminated to ground. Thus OUT07 should not have a signal present since it is listening to a quiet input. Any signal measured at the OUT07 can be attributed to the output crosstalk of the other 16 hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations. Effect of Impedances on Crosstalk The input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termi- nation resistors and the loops that drive them. Thus, the PC board on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies, the magnitude of the crosstalk is given by ( )sCRXT MS ×= )(log20 10 where: RS is the source resistance. CM is the mutual capacitance between the test signal circuit and the selected circuit. s is the Laplace transform variable. From the preceding equation, it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer.

and bond wires of the AD8104/AD8105. MXY is the mutual inductance of Output X to Outpu t Y. RL is the load resistance on the measured output. conductors and minimizing their parallel length. routing, and supply bypassing. array is arranged such that similar board routing can be achieved. be used to take the input rows to a lower signal plane if desired. separated as soon as they emerge from the IC package. manufacturers have the most experience with this application). layers are referenced to different ground planes. Figure 72. Fly-By Input Termination, Grounds for the Two Transmission Lines

Rev. A | Page 35 of 36 If multiple AD8104/AD8105 devices are to be driven in parallel, a fly-by input termination scheme is very useful, but the distance from each AD8104/AD8105 input to the driven input transmis- sion line is a stub that should be minimized in length and parasitics using the discussed guidelines. When driving the AD8104/AD8105 single-endedly, the undriven input is often terminated with a resistance to balance the input stage. It can be seen that by terminating the undriven input with a resistor of one half the characteristic impedance, the input stage is perfectly balanced (37.5 Ω, for example, to balance the two parallel 75 Ω terminations on the driven input). However, due to the feedback in the input receiver, there is high speed signal current leaving the undriven input. To terminate this high speed signal, proper transmission line techniques should be used. One solution is to adjust the trace width to create a transmission line of half the characteristic impedance and terminate the far end with this resistance (37.5 Ω in a 75 Ω system). This is not often practical as trace widths become large. In most cases, the best practical solution is to place the half- characteristic impedance resistor as close as possible (preferably less than 1.5 cm away) and to reduce the parasitics of the stub (by removing the ground plane under the stub, for example). In either case, the designer must decide if the layout complexity created by a balanced, terminated solution is preferable to simply grounding the undriven input at the ball with no trace. Although the examples discussed so far are for input termina- tion, the theory is similar for output back-termination. Taking the AD8104/AD8105 as an ideal voltage source, any distance of routing between the AD8104/AD8105 and a back-termination resistor is an impedance mismatch that potentially creates reflections. For this reason, back-termination resistors should also be placed close to the AD8104/AD8105. In practice, because back-termination resistors are series elements, they can be placed close to the AD8104/AD8105 outputs.

Rev. A | Page 36 of 36 OUTLINE DIMENSIONS *COMPLIANT TO JEDEC STANDARDS MO-192-BAN-2 WITH THE EXCEPTION TO PACKAGE HEIGHT. DETAIL A A B C D E F G H J K L M N P R T U V W Y AA AB AC 13 5791115 171921 23 13 46810 12 216 1820 22 14 27.94 BSC SQ BOTTOM VIEW A1 CORNER INDEX AREA 1.27 BSC TOP VIEW 31.00 BSC SQ BALL A1 INDICATOR

0.10 MIN

0.70 0.63 0.56 1.07 0.99 0.92 COPLANARITY 0.20 0.90 0.75 0.60 SEATING PLANEBALL DIAMETER DETAIL A*1.765 MAX 022206-A

0.25 MIN

(4 ) F igure 73. 304-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] (BP-304) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD8104ABPZ −40°C to +85°C 304-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-304 AD8105ABPZ −40°C to +85°C 304-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-304 1 Z = RoHS Compliant Part. ©2007–2016 Analog Devices, Inc. All rights reserved. Tr ademarks and registered trademarks are the property of their respective owners. D06612-0-4/16(A)