AD80066KRSZ

AD80066 AD | Alldatasheet

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Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

16-bit, 24 MSPS analog-to-digital converter (ADC) 4-channel operation up to 24 MHz (6 MHz/channel) 3-channel operation up to 24 MHz (8 MHz/channel) Selectable input range: 3 V or 1.5 V peak-to-peak Input clamp circuitry Correlated double sampling 1×~6× programmable gain ±300 mV programmable offset Internal voltage reference Multiplexed byte-wide output Optional single-byte output mode 3-wire serial digital interface

3 V/5 V digital I/O compatibility

Power dissipation: 490 mW at 24 MHz operation Reduced power mode and sleep mode available 28-lead SSOP package

APPLICATIONS

The AD80066 is a complete analog signal processor for imaging applications. It features a 4-channel architecture designed to sample and condition the outputs of linear charged coupled device (CCD) or contact image sensor (CIS) arrays. Each channel consists of an input clamp, correlated double sampler (CDS), offset digital- to-analog converter (DAC), and programmable gain amplifier (PGA), multiplexed to a high performance 16-bit ADC. For maximum flexibility, the AD80066 can be configured as a 4-channel, 3-channel, 2-channel, or 1-channel device. The CDS amplifiers can be disabled for use with sensors that do not require CDS, such as CIS and CMOS sensors. The 16-bit digital output is multiplexed into an 8-bit output word, which is accessed using two read cycles. There is an optional single-byte output mode. The internal registers are programmed through a 3-wire serial interface and enable adjustment of the gain, offset, and operating mode. The AD80066 operates from a

5 V power supply, typically consumes 490 mW of power, and is

packaged in a 28-lead SSOP . FUNCTIONAL BLOCK DIAGRAM DOUT (D[0:7]) SCLK SLOAD SDATA ADCCLK OFFSET AVDD AVSS CML AVDD CAPT CAPB AD80066 DRVDD DRVSS GAIN REGISTERS OFFSET REGISTERS 4:1 MUX 16-BIT ADC CH. A CH. B CH. C CH. D 816 CH. A CH. B CH. C CH. D PGA PGA PGA CDS CDS CDS AVSS VIND VINC VINB VINA CDS DIGITAL CONTROL INTERFACE INPUT CLAMP BIAS 9-BIT DAC 9-BIT DAC 9-BIT DAC 9-BIT DAC PGA CONFIGURATION REGISTER MUX REGISTER CDSCLK2CDSCLK1 BAND GAP REFERENCE 16:8 MUX 08552-001 Figure 1.

Rev. A | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

4/10—Revision A: Initial Version

Rev. A | Page 3 of 20 SPECIFICATIONS ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = 5 V , DRVDD = 5 V , CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, PGA gain = 1, unless otherwise noted. Table 1. Parameter Min Typ Max Unit MAXIMUM CONVERSION RATE 4-Channel Mode with CDS 24 MSPS 3-Channel Mode with CDS 24 MSPS 2-Channel Mode with CDS 24 MSPS 1-Channel Mode with CDS 12 MSPS ACCURACY (ENTIRE SIGNAL PATH) ADC Resolution 16 Bits Integral Nonlinearity (INL) +20/−5 LSB Differential Nonlinearity (DNL) ±0.5 LSB No Missing Codes Guaranteed ANALOG INPUTS Input Signal Range1 1.5/3.0 V p-p Allowable Reset Transient1 2.0 V Input Limits2 AVSS − 0.3 AVDD + 0.3 V Input Capacitance 10 pF Input Bias Current 10 nA AMPLIFIERS PGA Gain Range 1 5.9 V/V PGA Gain Resolution2 64 Steps PGA Gain Monotonicity Guaranteed Programmable Offset Range −305 +295 mV Programmable Offset Resolution 512 Steps Programmable Offset Monotonicity Guaranteed NOISE AND CROSSTALK Total Output Noise at PGA Minimum 9.5 LSB rms Total Output Noise at PGA Maximum 35 LSB rms Channel-to-Channel Crosstalk @ 24 MSPS 70 dB @ 12 MSPS 90 dB POWER SUPPLY REJECTION AVDD = 5 V ± 0.25 V 0.1 % FSR VOLTAGE REFERENCE (TA = 25°C) CAPT − CAPB 0.75 V TEMPERATURE RANGE Operating 0 70 °C Storage −65 +150 °C POWER SUPPLIES AVDD 4.5 5.0 5.25 V DRVDD 3.0 3.3 5.25 V OPERATING CURRENT AVDD 95 mA DRVDD 4 mA Power-Down Mode Current 300 μA

3 Measured with Bit D1 of the configuration register set high for 8 MHz, low power operation. Figure 2. Input Signal with the CCD Reference Level Clamped to 3 V TMIN to TMAX, AVDD = 5 V , DRVDD = 5 V , CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, CL = 10 pF, unless otherwise noted.

TMIN to TMAX, AVDD = 5 V , DRVDD = 5 V . 1 CDSCLKx falling edges should not occur within the first 10 ns following an ADCCLK edge. Figure 3. 4-Channel CDS Mode Timing

soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance

Rev. A | Page 10 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD80066 TOP VIEW (Not to Scale) AVDD AVSS (LSB) D0 CDSCLK1 CDSCLK2 ADCCLK DRVDD DRVSS (MSB) D7 VINA OFFSET VINB CML VINC CAPT CAPB VIND AVDD SLOAD SCLK SDATA AVSS 8 21 9 20 10 19 11 18 12 17 13 16 14 15 08552-013 Figure 13. Pin Configuration Table 6. Pin Function Descriptions

Description

1 AVDD P 5 V Analog Supply. 2 CDSCLK1 DI CDS Reference Level Sampling Clock. 3 CDSCLK2 DI CDS Data Level Sampling Clock. 4 ADCCLK DI ADC Sampling Clock. 5 DRVDD P Digital Output Driver Supply (3 V or 5 V). 6 DRVSS P Digital Output Driver Ground. 7 D7 (MSB) DO Data Output MSB. ADC DB15 high byte; ADC DB7 low byte. 8 D6 DO Data Output. ADC DB14 high byte; ADC DB6 low byte. 9 D5 DO Data Output. ADC DB13 high byte; ADC DB5 low byte. 10 D4 DO Data Output. ADC DB12 high byte; ADC DB4 low byte. 11 D3 DO Data Output. ADC DB11 high byte; ADC DB3 low byte. 12 D2 DO Data Output. ADC DB10 high byte; ADC DB2 low byte. 13 D1 DO Data Output. ADC DB9 high byte; ADC DB1 low byte. 14 D0 (LSB) DO Data Output LSB. ADC DB8 high byte; ADC DB0 low byte. 15 SDATA DI/DO Serial Interface Data Input/Output. 16 SCLK DI Serial Interface Clock Input. 17 SLOAD DI Serial Interface Load Pulse. 18 AVDD P 5 V Analog Supply. 19 AVSS P Analog Ground. 20 VIND AI Analog Input, D Channel. 21 CAPB AO ADC Bottom Reference Voltage Decoupling. 22 CAPT AO ADC Top Reference Voltage Decoupling. 23 VINC AI Analog Input, C Channel. 24 CML AO Internal Bias Level Decoupling. 25 VINB AI Analog Input, B Channel. 26 OFFSET AO Clamp Bias Level Decoupling. 27 VINA AI Analog Input, A Channel. 28 AVSS P Analog Ground. 1 AI = analog input, AO = analog output, DI = digital input, DO = digital output, and P = power.

Rev. A | Page 12 of 20 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. The point used as zero scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value; therefore, every code must have a finite width. No missing codes guaranteed to 16-bit resolution indicates that all 65,536 codes must be present over all operating ranges. Offset Error The first ADC code transition should occur at a level ½ LSB above the nominal zero-scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level. Gain Error The last code transition should occur for an analog value 1½ LSB below the nominal full-scale voltage. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. Input-Referred Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and converted to an equivalent voltage, using the relationship 1 LSB = 1.5 V/65,536 = 23 μV . The noise is then referred to the input of the AD80066 by dividing by the PGA gain. Channel-to-Channel Crosstalk In an ideal 3-channel system, the signal in one channel does not influence the signal level of another channel. The channel-to- channel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. In the AD80066, one channel is grounded and the other two channels are exercised with full-scale input signals. The change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB. Aperture Delay The aperture delay is the delay that occurs from when a sampling edge is applied to the AD80066 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low; therefore, the aperture delay is measured from each falling edge of the clock to when the internal sample is taken. Power Supply Rejection The power supply rejection specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits.

Rev. A | Page 13 of 20 THEORY OF OPERATION The AD80066 can be operated in several different modes, including 4-channel CDS mode, 4-channel SHA mode, 1-channel CDS mode, and 1-channel SHA mode. Each mode is selected by programming the configuration register through the serial interface. For more information on CDS or SHA mode operation, see the Circuit Operation section. 4-CHANNEL CDS MODE In 4-channel CDS mode, the AD80066 simultaneously samples the A, B, C, and D input voltages from the CCD outputs. The sampling points for each CDS are controlled by CDSCLK1 and CDSCLK2 (see Figure 17 and Figure 18). The CDSCLK1 falling edge samples the reference level of the CCD waveform, and the CDSCLK2 falling edge samples the data level of the CCD wave- form. Each CDS amplifier outputs the difference between the CCD reference level and the data level. The output voltage of each CDS amplifier is then level-shifted by an offset DAC. The voltages are scaled by the four PGAs before being multiplexed through the 16-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The offset and gain values for the A, B, C, and D channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the mux register. Timing for this mode is shown in Figure 3. The falling edge of CDSCLK2 should occur coincident with or before the rising edge of ADCCLK. However, this is not required to satisfy the minimum timing constraints. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by t ADC2. The output data latency is 3 ADCCLK cycles. 4-CHANNEL SHA MODE In 4-channel SHA mode, the AD80066 simultaneously samples the A, B, C, and D input voltages. The sampling point is controlled by CDSCLK2. The falling edge of CDSCLK2 samples the input waveforms on each channel. The output voltages from the three SHAs are modified by the offset DACs and then scaled by the four PGAs. The outputs of the PGAs are then multiplexed through the 16-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The input signal is sampled with respect to the voltage applied to the OFFSET pin (see Figure 19). With the OFFSET pin grounded, a 0 V input corresponds to the zero-scale output of the ADC. The OFFSET pin can also be used as a coarse offset adjustment pin. A voltage applied to this pin is subtracted from the voltages applied to the A, B, C, and D inputs in the first amplifier stage of the AD80066. The input clamp is disabled in this mode. For more information, see the Analog Inputs—SHA Mode section. The offset and gain values for the A, B, C, and D channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the mux register. Timing for this mode is shown in Figure 7. The CDSCLK1 pin should be grounded in this mode. Although not required, the falling edge of CDSCLK2 should occur coincident with or before the rising edge of ADCCLK. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by t ADC2. The output data latency is 3 ADCCLK cycles. 1-CHANNEL CDS MODE The 1-channel CDS mode operates in the same way as the 4-channel CDS mode, except the multiplexer remains fixed. Only the channel specified in the mux register is processed. Timing for this mode is shown in Figure 6. 1-CHANNEL SHA MODE The 1-channel SHA mode operates in the same way as the 4-channel SHA mode, except the multiplexer remains fixed. Only the channel specified in the mux register is processed. Timing for this mode is shown in Figure 8. The CDSCLK1 pin should be grounded in this mode of operation.

Table 7. Internal Register Map

and bias levels. The D8, D7, and D6 bits should always be set low. is set high, the 16-bit ADC output is multiplexed into two bytes. figured for slow operation (8 MHz) to reduce power consumption. are retained while the AD80066 is in the power-down state. D channel. The multiplexer remains stationary in 1-channel mode. the gain range in 64 increments. See Figure 22 for the PGA gain vs. Table 8. Configuration Register Settings Table 9. Mux Register Settings Table 10. PGA Gain Register Settings

Table 11. Offset Register Settings

0.05 MIN

0.65 BSC

2.00 MAX

Figure 25. 28-Lead Shrink Small Outline Package [SSOP] registered trademarks are the prop erty of their respective owners.