AD8003

AD8003 (Rev. C)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 16

Technical content

Triple, 1.5 GHz Op Amp Data Sheet AD8003 Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2005–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

1650 MHz (G = +1)

730 MHz (G = +2, VO = 2 V p-p)

4300 V/µs (G = +2, 4 V step)

Settling time 12 ns to 0.1%, 2 V step Excellent for QXGA resolution video Gain flatness 0.1 dB to 190 MHz 0.05% differential gain error, RL = 150 Ω 0.01° differential phase error, RL = 150 Ω Low voltage offset: 0.7 mV (typical) Low input bias current: 7 µA (typical) Low noise: 1.8 nV/√Hz Low distortion over wide bandwidth: SFDR −73 dBc @ 20 MHz High output drive: 100 mA output load drive Supply operation: +5 V to ±5 V voltage supply Supply current: 9.5 mA/amplifier

APPLICATIONS

High resolution video graphics Professional video Consumer video High speed instrumentation Muxing CONNECTION DIAGRAM 7 8 9 10 11 12 24 23 22 21 20 19 +VS3 FEEDBACK 3 –IN 3 +IN 3 POWER DOWN 3 –VS3 –VS2 POWER DOWN 2 +IN 2 –IN 2 FEEDBACK 2 +VS2 +VS1 FEEDBACK 1 –IN 1 +IN 1 POWER DOWN 1 –VS1 NC NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD (LFCSP ONLY): THE EXPOSED PAD CAN BE CONNECTED TO GND OR POWER PLANES, OR IT CAN BE LEFT FLOATING. OUT 1 NC OUT 2 NC OUT 3 05721-001 Figure 1. 24-Lead, 4 mm × 4 mm LFCSP_WQ (CP-24) The AD8003 is a triple ultrahigh speed current feedback amplifier. maximum and a dc input voltage of 0.7 mV. gain of 0.05% and a differential gain of 0.01°. output current, the AD8003 is ideal for a variety of applications. reduces the quiescent current even further to 1.6 mA. industrial temperature range of −40°C to +85°C. Figure 2. Large Signal Frequency Response for Various Gains

Rev. C | Page 2 of 16 TABLE OF CONTENTS

REVISION HISTORY

3/14—Rev. B to Rev. C 9/08—Rev. A to Rev. B 2/06—Rev. 0 to Rev. A 10/05—Revision 0: Initial Version

Rev. C | Page 3 of 16 SPECIFICATIONS WITH ±5 V SUPPLY TA = 25°C, VS = ±5 V, RL = 150 Ω, Gain = +2, RF = 464 Ω, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, Vo = 0.2 V p-p, RF = 432 Ω 1650 MHz G = +2, Vo = 2 V p-p 730 MHz G = +10, Vo = 0.2 V p-p 290 MHz G = +5, Vo = 2 V p-p 330 MHz Bandwidth for 0.1 dB Flatness Vo = 2 V p-p 190 MHz Slew Rate G = +2, Vo = 2 V step, RL = 150 Ω 3800 V/µs Settling Time to 0.1% G = +2, Vo = 2 V step 12 ns Overload Recovery Input/Output 30/40 ns NOISE/HARMONIC PERFORMANCE Second/Third Harmonic @ 5 MHz G = +1, Vo = 2 V p-p 76/97 dBc Second/Third Harmonic @ 20 MHz G = +1, Vo = 2 V p-p 79/73 dBc Input Voltage Noise f = 1 MHz 1.8 nV/√Hz Input Current Noise (I−/I+) f = 1 MHz 36/3 pA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.05 % Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.01 Degree DC PERFORMANCE Input Offset Voltage −9.3 +0.7 +9.3 mV TMIN − TMAX 1.08 mV Input Offset Voltage Drift 7.4 µV/°C Input Bias Current +IB/−IB −19/−40 −7/−7 +4/+50 µA TMIN − TMAX (+IB/−IB) −3.8/+29.5 µA Input Offset Current ±14.2 µA Transimpedance Vo = ±2.5 V 400 600 1100 kΩ INPUT CHARACTERISTICS Noninverting Input Impedance 1.6/3 MΩ/pF Input Common-Mode Voltage Range ±3.6 V Common-Mode Rejection Ratio VCM = ±2.5 V −51 −48 −46 dB OUTPUT CHARACTERISTICS Output Voltage Swing RL = 150 Ω ±3.85 ±3.9 ±3.92 V Linear Output Current VO = 2 V p-p, second harmonic < −50 dBc 100 mA Capacitive Load Drive 40% over shoot 27 pF POWER DOWN PINS Power-Down Input Voltage Power down <VS − 2.5 V Enable >VS − 2.5 V Turn-Off Time 50% of power-down voltage to 10% of VOUT final, VIN = 0.5 V p-p 40 ns Turn-On Time 50% of power-down voltage to 90% of VOUT final, VIN = 0.5 V p-p 130 ns Input Current Enabled 0.1 µA Power-Down −365 −235 −85 µA POWER SUPPLY Operating Range 4.5 10 V Quiescent Current per Amplifier Enabled 8.1 9.5 10.2 mA Quiescent Current per Amplifier Power down 1.2 1.4 1.6 mA Power Supply Rejection Ratio (+PSRR/−PSRR) −59/−57 −57/−53 −55/−50 dB

Rev. C | Page 4 of 16 SPECIFICATIONS WITH +5 V SUPPLY TA = 25°C, VS = 5 V, RL = 150 Ω, Gain = +2, RF = 464 Ω, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, Vo = 0.2 V p-p, RF = 432 Ω 1050 MHz G = +2, Vo = 2 V p-p 590 MHz G = +10, Vo = 0.2 V p-p 290 MHz G = +5, Vo = 2 V p-p 310 MHz Bandwidth for 0.1 dB Flatness Vo = 2 V p-p 83 MHz Slew Rate G = +2, Vo = 2 V step, RL = 150 Ω 2860 V/µs Settling Time to 0.1% G = +2, Vo = 2 V step 12 ns Overload Recovery Input/Output 40/60 ns NOISE/HARMONIC PERFORMANCE Second/Third Harmonic @ 5 MHz G = +1, Vo = 2 V p-p 75/78 dBc Second/Third Harmonic @ 20 MHz G = +1, Vo = 2 V p-p 66/61 dBc Input Voltage Noise f = 1 MHz 1.8 nV/√Hz Input Current Noise (I−/I+) f = 1 MHz 36/3 pA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.04 % Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.01 Degree DC PERFORMANCE Input Offset Voltage −6.5 +2.7 +11 mV TMIN − TMAX 2.06 mV Input Offset Voltage Drift 14.2 µV/°C Input Bias Current (+IB/−IB) −21/−50 −7.7/−2.3 +5/+48 µA TMIN − TMAX (+IB/−IB) −4/−27.8 µA Input Offset Current ±5.4 µA Transimpedance 300 530 1500 kΩ INPUT CHARACTERISTICS Noninverting Input Impedance 1.6/3 MΩ/pF Input Common-Mode Voltage Range 1.3 to 3.7 V Common-Mode Rejection Ratio −50 −48 −45 dB OUTPUT CHARACTERISTICS Output Voltage Swing RL = 150 Ω ±1.52 ±1.57 ±1.62 V Linear Output Current VO = 2 V p-p, second harmonic < −50 dBc 70 mA Capacitive Load Drive 45% over shoot 27 pF POWER DOWN PINS Power-Down Input Voltage Power down <VS − 2.5 V Enable >VS − 2.5 V Turn-Off Time 50% of power-down voltage to 10% of VOUT final, VIN = 0.5 V p-p 125 ns Turn-On Time 50% of power-down voltage to 90% of VOUT final, VIN = 0.5 V p-p 80 ns Input Current Enabled 0.1 µA Power-Down −160 −43 +80 µA POWER SUPPLY Operating Range 4.5 10 V Quiescent Current per Amplifier Enabled 6.3 7.9 9.4 mA Quiescent Current per Amplifier Power down 0.8 0.9 1.1 mA Power Supply Rejection Ratio (+PSRR/−PSRR) −59/−56 −57/−53 −55/−50 dB

Figure 28. Offset Voltage vs. Input Common-Mode Range Figure 29. Inverting Input Bias Current Linearity Figure 30. POWER DOWN Pin Current and Supply Current vs.

10 VS =± 5 V VS =+ 5 V

Figure 31. Noninverting Input Bias Current vs. Common-Mode Range Figure 32. Disable Switching Time for Various Supplies Figure 33. POWER DOWN Pin Current and Supply Current vs.

Rev. C | Page 13 of 16 PRINTED CIRCUIT BOARD LAYOUT Printed circuit board (PCB) layout is usually one of the last steps in the design process and often proves to be one of the most critical. A high performance design can be rendered mediocre due to poor or sloppy layout. Because the AD8003 can operate into the RF frequency spectrum, high frequency board layout considerations must be taken into account. The PCB layout, signal routing, power supply bypassing, and grounding must all be addressed to ensure optimal performance. LOW DISTORTION PINOUT The AD8003 LFCSP features ADI’s low distortion pinout. The pinout lowers the second harmonic distortion and simplifies the circuit layout. The close proximity of the noninverting input and the negative supply pin creates a source of second harmonic distortion. Physical separation of the noninverting input pin and the negative power supply pin reduces this distortion. By providing an additional output pin, the feedback resistor can be connected directly between the feedback pin and the inverting input. This greatly simplifies the routing of the feedback resistor and allows a more compact circuit layout, which reduces its size and helps to minimize parasitics and increase stability. SIGNAL ROUTING To minimize parasitic inductances, ground planes should be used under high frequency signal traces. However, the ground plane should be removed from under the input and output pins to minimize the formation of parasitic capacitors, which degrades phase margin. Signals that are susceptible to noise pickup should be run on the internal layers of the PCB, which can provide maximum shielding. EXPOSED PADDLE The AD8003 features an exposed paddle, which lowers the thermal resistance by approximately 40% compared to a standard SOIC plastic package. The paddle can be soldered directly to the ground plane of the board. Thermal vias or heat pipes can also be incorporated into the design of the mounting pad for the exposed paddle. These additional vias improve the thermal transfer from the package to the PCB. Using a heavier weight copper also reduces the overall thermal resistance path to ground. POWER SUPPLY BYPASSING Power supply bypassing is a critical aspect of the PCB design process. For best performance, the AD8003 power supply pins need to be properly bypassed. Each amplifier has its own supply pins brought out for the utmost flexibility. Supply pins can be commoned together or routed to a dedicated power plane. Commoned supply connections can also reduce the need for bypass capacitors on each supply line. The exact number and values of the bypass capacitors are dictated by the design specifications of the actual circuit. A parallel combination of different value capacitors from each of the power supply pins to ground tends to work the best. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins see a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier. Starting directly at the power supply pins, the smallest value and physical-sized component should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier, and connected to the ground plane. This process should be repeated for the next largest capacitor value. It is recommended that a 0.1 µF ceramic 0508 case be used for the AD8003. The 0508 offers low series inductance and excellent high frequency performance. The 0.1 µF case provides low impedance at high frequencies. A 10 µF electrolytic capacitor should be placed in parallel with the 0.1 µF . The 10 µF capacitor provides low ac impedance at low frequencies. Smaller values of electrolytic capacitors can be used depending on the circuit requirements. Additional smaller value capacitors help provide a low impedance path for unwanted noise out to higher frequencies but are not always necessary. Placement of the capacitor returns (grounds), where the capacitors enter into the ground plane, is also important. Returning the capacitor grounds close to the amplifier load is critical for distortion performance. Keeping the capacitors distance short, but equal from the load, is optimal for performance. In some cases, bypassing between the two supplies can help improve PSRR and maintain distortion performance in crowded or difficult layouts. Designers should note this as another option for improving performance.

Rev. C | Page 14 of 16 Minimizing the trace length and widening the trace from the capacitors to the amplifier reduces the trace inductance. A series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. This additional inductance can also contribute to increased distortion due to high frequency compression at the output. The use of vias should be minimized in the direct path to the amplifier power supply pins because vias can introduce parasitic inductance, which can lead to instability. When required, use multiple large diameter vias because this lowers the equivalent parasitic inductance. GROUNDING The use of ground and power planes is encouraged as a method of proving low impedance returns for power supply and signal currents. Ground and power planes can also help to reduce stray trace inductance and provide a low thermal path for the amplifier. Ground and power planes should not be used under any of the pins of the AD8003. The mounting pads and the ground or power planes can form a parasitic capacitance at the amplifiers input. Stray capacitance on the inverting input and the feedback resistor form a pole, which degrades the phase margin, leading to instability. Excessive stray capacitance on the output also forms a pole, which degrades phase margin.

COMPLIANT TOJEDEC STANDARDS MO-220-WGGD-8.

0.20 REF

0.25 MIN

0.05 MAX

0.02 NOM

Figure 41. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Rev. C | Page 16 of 16 NOTES ©2005–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05721-0-3/14(C)