AD8002ARM-EBZ

AD8002_V01 AD | Alldatasheet

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Dual 600 MHz, 50 mW Current Feedback Amplifier Data Sheet AD8002 Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Excellent video specifications (RL = 150 Ω, G = +2) Gain flatness: 0.1 dB to 60 MHz Differential gain error: 0.01% Differential phase error: 0.02° Low power Maximum power supply current (50 mW): 5.0 mA/amp High speed and fast settling −3 dB bandwidth (G = +1): 600 MHz −3 dB bandwidth (G = +2): 500 MHz Slew rate: 1200 V/µs Settling time to 0.1%: 16 ns Low distortion THD at fC = 5 MHz: −65 dBc Third-order intercept at f1 = 10 MHz: 33 dBm SFDR at f = 5 MHz: −66 dB Crosstalk at f = 5 MHz: −60 dB High output drive Over 70 mA output current Drives up to eight back terminated 75 Ω loads (four loads/side) while maintaining good differential gain/phase performance (0.01%/0.17°) Available in 8-lead SOIC and MSOP packages

APPLICATIONS

The AD8002 is a dual, low power, high speed amplifier designed to operate on ±5 V supplies. The AD8002 features unique transimpedance linearization circuitry, which allows the AD8002 to drive video loads with excellent differential gain and phase performance on only 50 mW of power per amplifier. The AD8002 is a current feedback amplifier and features gain flatness of 0.1 dB to 60 MHz while offering differential gain and phase error of 0.01% and 0.02°, which makes the AD8002 ideal for professional video electronics such as cameras and video switchers. Additionally, the low distortion and fast settling of the AD8002 make it ideal for buffer high speed analog-to- digital converters (ADCs). PIN CONNECTION BLOCK DIAGRAM OUT1 –IN1 +IN1 OUT2 –IN2 +IN2 01044-001 AD8002 F igure 1. T he AD8002 offers a low power of 5.0 mA/amp maximum (VS = ±5 V) and can run on a single 12 V power supply, yet is capable of delivering over 70 mA of load current. It is offered in 8-lead SOIC and MSOP packages. These features make this amplifier ideal for portable and battery-powered applications where size and power are critical. The bandwidth of 600 MHz along with 1200 V/µs of slew rate make the AD8002 useful in many general-purpose high speed applications where dual power supplies of up to ±6 V and single supplies from 6 V to 12 V are needed. The AD8002 is available in the industrial temperature range of −40°C to +85°C. 01044-003 G = +2 1V STEP SIDE 1 200mV SIDE 2 5ns F igure 2. 1 V Step Response, G = +1

Rev. E | Page 2 of 21 TABLE OF CONTENTS

REVISION HISTORY

8/15—Rev. D to Rev. E Added Pin Configurations and Function Descriptions Section, 4/01—Rev. C to Rev. D

Rev. E | Page 3 of 21 SPECIFICATIONS At TA = 25°C, VS = ±5 V, RL = 100 Ω, RC1 = 75 Ω, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth R Package G = +2, RF = 681 Ω 500 MHz G = +1, RF = 953 Ω 600 MHz G = +1, RF = 1 kΩ 600 MHz Bandwidth for 0.1 dB Flatness R Package G = +2, RF = 681 Ω 90 MHz Slew Rate G = +2, VOUT = 2 V step 700 V/µs G = −1, VOUT = 2 V step 1200 V/µs Settling Time to 0.1% G = +2, VOUT = 2 V step 16 ns Rise and Fall Time G = +2, VOUT = 2 V step, RF = 750 Ω 2.4 ns NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion (THD) fC = 5 MHz, VOUT = 2 V p-p, G = +2, RL = 100 Ω −65 dBc Crosstalk (Output to Output) f = 5 MHz, G = +2 −60 dB Input Voltage Noise f = 10 kHz, RC = 0 Ω 2.0 nV/√Hz Input Current Noise f = 10 kHz, +IN1,+IN2 2.0 pA/√Hz f = 10 kHz, −IN1, −IN2 18 pA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 % Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.02 Degrees Third-Order Intercept f1= 10 MHz 33 dBm 1 dB Gain Compression f = 10 MHz 14 dBm Spurious-Free Dynamic Range (SFDR) f = 5 MHz −66 dB DC PERFORMANCE Input Offset Voltage 2.0 6 mV TMIN to TMAX 2.0 9 mV Offset Drift 10 µV/°C Input Bias Current (−IN1, −IN2) −25 +5.0 +25 µA TMIN to TMAX −35 +35 µA Input Bias Current (+IN1, +IN2) −6.0 +3.0 +6.0 µA TMIN to TMAX −10 +10 µA Open-Loop Transresistance VOUT = ±2.5 V 250 900 kΩ TMIN to TMAX 175 kΩ INPUT CHARACTERISTICS Input Resistance +IN1, +IN2 10 MΩ −IN1, −IN2 50 Ω Input Capacitance +IN1, +IN2 1.5 pF Input Common-Mode Voltage Range ±3.2 V Common-Mode Rejection Ratio Offset Voltage VCM = ±2.5 V 49 54 dB Input Current (−IN1, −IN2) VCM = ±2.5 V, TMIN to TMAX 0.3 1.0 µA/V Input Current (+IN1, +IN2) VCM = ±2.5 V, TMIN to TMAX 0.2 0.9 µA/V OUTPUT CHARACTERISTICS Output Voltage Swing RL = 150 Ω ±2.7 ±3.1 V Output Current2 70 mA Short-Circuit Current2 85 110 mA

Rev. E | Page 4 of 21 Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Range ±3.0 ±6.0 V Quiescent Current/Both Amplifiers TMIN to TMAX 10.0 11.5 mA Power Supply Rejection Ratio +VS = +4 V to +6 V, −VS = −5 V 60 75 dB −VS = −4 V to −6 V, +VS = +5 V 49 56 dB Input Current (−IN1, −IN2) TMIN to TMAX 0.5 2.5 µA/V Input Current (+IN1, +IN2) TMIN to TMAX 0.1 0.5 µA/V 1 RC is recommended to reduce peaking and minimize input reflections at frequencies above 300 MHz. However, RC is not required. 2 Output current is limited by the maximum power dissipation in the package. See Figure 3.

1 Specification is for device in free air:

an extended period can result in device failure. temperature (150°C) is not exceeded under all conditions. maximum power derating curves. Figure 3. Maximum Power Dissipation vs. Ambient Temperature

Figure 4. 8-Lead SOIC Figure 5. 8-Lead MSOP Table 3. Pin Function Descriptions

1 OUT1 Output 1

4 V− VEE or Negative Supply

7 OUT2 Output 2

8 V+ VCC or Positive Supply

Figure 12. Distortion vs. Frequency, G = +2, RL = 1 kΩ Figure 13. Crosstalk (Output to Output) vs. Frequency Figure 14. Pulse Crosstalk, Worst Case, 1 V Step

2 BACK TERMINATED

1 BACK TERMINATED

Figure 15. Differential Gain and Differential Phase (per Amplifier) Figure 16. Gain vs. Frequency Response, G = +1 (See Figure 42) Figure 17. Distortion vs. Frequency, G = +1, RL = 100 Ω

more than 3 V p-p into a 20 Ω load for each output at 20 MHz. components in the feedback network. mode output signal was measured as −50 dB at 1 MHz. (opposite polarity of Output 2). is used as the output reference, the gain is positive. common-mode rejection (CMR). peaking and realize a −3 dB bandwidth of more than 200 MHz. the third harmonic is −43 dBc. Figure 56. Differential Driver Frequency Response

careful attention to board layout and component selection. the input pins to reduce stray capacitance. to keep the stray capacitance at this node to a minimum. significantly affects high speed performance. Table 4 and Table 5 show the recommended component values. Figure 57. Inverting Configuration Figure 58. Supply Bypassing Figure 59. Noninverting Configuration Table 4. AD8002AR (SOIC) Recommended Component Values1

1 N/A means not applicable

2 RC is recommended to reduce peaking, and minimizes input reflections at frequencies above 300 MHz. However, RC is not required. Table 5. AD8002ARM (MSOP) Recommended Component Values1 2 RC is recommended to reduce peaking, and minimizes input reflections at frequencies above 300 MHz. However, RC is not required.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 72. 8-Lead Standard Small Outline Package [SOIC_N]

0.65 BSC

1.10 MAX

Figure 73. 8-Lead Mini Small Outline Package [MSOP] registered trademarks are the prop erty of their respective owners.